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+/*
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+ * U-boot - Configuration file for BlackStamp board
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+ * Configuration by Ben Matthews for UR LLE using bf533-stamp.h
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+ * as a template
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+ * See http://blackfin.uclinux.org/gf/project/blackstamp/
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+ */
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+
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+#ifndef __CONFIG_BLACKSTAMP_H__
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+#define __CONFIG_BLACKSTAMP_H__
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+
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+#include <asm/blackfin-config-pre.h>
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+
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+/*
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+ * Debugging: Set these options if you're having problems
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+ */
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+/*
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+ * #define CONFIG_DEBUG_EARLY_SERIAL
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+ * #define DEBUG
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+ * #define CONFIG_DEBUG_DUMP
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+ * #define CONFIG_DEBUG_DUMP_SYMS
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+*/
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+#define CONFIG_PANIC_HANG 0
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+
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+/* CPU Options
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+ * Be sure to set the Silicon Revision Correctly
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+ */
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+#define CONFIG_BFIN_CPU bf532-0.5
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+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
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+
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+/*
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+ * Board settings
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+ */
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+#define CONFIG_DRIVER_SMC91111 1
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+#define CONFIG_SMC91111_BASE 0x20300300
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+
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+/* FLASH/ETHERNET uses the same address range
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+ * Depending on what you have the CPLD doing
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+ * this probably isn't needed
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+ */
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+#define SHARED_RESOURCES 1
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+
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+/* Is I2C bit-banged? */
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+#undef CONFIG_SOFT_I2
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+
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+/*
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+ * Clock Settings
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+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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+ */
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+/* CONFIG_CLKIN_HZ is any value in Hz */
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+#define CONFIG_CLKIN_HZ 25000000
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+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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+/* 1 = CLKIN / 2 */
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+#define CONFIG_CLKIN_HALF 0
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+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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+/* 1 = bypass PLL */
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+#define CONFIG_PLL_BYPASS 0
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+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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+/* Values can range from 0-63 (where 0 means 64) */
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+#define CONFIG_VCO_MULT 16
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+/* CCLK_DIV controls the core clock divider */
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+/* Values can be 1, 2, 4, or 8 ONLY */
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+#define CONFIG_CCLK_DIV 1
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+/* SCLK_DIV controls the system clock divider */
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+/* Values can range from 1-15 */
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+#define CONFIG_SCLK_DIV 3
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+
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+/*
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+ * Network settings
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+ */
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+
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+#ifdef CONFIG_DRIVER_SMC91111
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+#define CONFIG_IPADDR 192.168.0.15
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+#define CONFIG_NETMASK 255.255.255.0
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+#define CONFIG_GATEWAYIP 192.168.0.1
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+#define CONFIG_SERVERIP 192.168.0.2
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+#define CONFIG_HOSTNAME blackstamp
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+#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
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+#define CONFIG_SYS_AUTOLOAD "no"
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+
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+/* To remove hardcoding and enable MAC storage in EEPROM */
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+/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
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+#endif
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+
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+#define CONFIG_ENV_IS_IN_SPI_FLASH
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+#define CONFIG_ENV_OFFSET 0x4000
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+#define CONFIG_ENV_SIZE 0x2000
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+#define CONFIG_ENV_SECT_SIZE 0x40000
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+#define ENV_IS_EMBEDDED_CUSTOM
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+
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+/*
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+ * SDRAM settings & memory map
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+ */
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+
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+#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
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+#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
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+
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+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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+#define CONFIG_SYS_MALLOC_LEN (384 << 10)
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+
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+/*
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+ * Command settings
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+ */
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+
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+#define CONFIG_SYS_LONGHELP 1
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+#define CONFIG_CMDLINE_EDITING 1
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+#define CONFIG_AUTO_COMPLETE 1
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+#define CONFIG_ENV_OVERWRITE 1
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+
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+#include <config_cmd_default.h>
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+
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+#ifdef CONFIG_DRIVER_SMC91111
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+# define CONFIG_CMD_DHCP
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+# define CONFIG_CMD_PING
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+#else
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+# undef CONFIG_CMD_NET
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+#endif
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+
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+#ifdef CONFIG_SOFT_I2C
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+# define CONFIG_CMD_I2C
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+#endif
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+
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+#define CONFIG_CMD_BOOTLDR
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+#define CONFIG_CMD_CACHE
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+#define CONFIG_CMD_CPLBINFO
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+#define CONFIG_CMD_DATE
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+#define CONFIG_CMD_SF
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+#define CONFIG_CMD_ELF
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+
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+#define CONFIG_BOOTDELAY 5
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+#define CONFIG_BOOTCOMMAND "run ramboot"
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+#define CONFIG_BOOTARGS \
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+ "root=/dev/mtdblock0 rw " \
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+ "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
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+ "earlyprintk=" \
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+ "serial," \
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+ "uart" MK_STR(CONFIG_UART_CONSOLE) "," \
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+ MK_STR(CONFIG_BAUDRATE) " " \
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+ "console=ttyBF0," MK_STR(CONFIG_BAUDRATE)
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+
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+#if defined(CONFIG_CMD_NET)
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+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
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+# define UBOOT_ENV_FILE "u-boot.bin"
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+# else
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+# define UBOOT_ENV_FILE "u-boot.ldr"
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+# endif
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+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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+# ifdef CONFIG_SPI
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+# define UBOOT_ENV_UPDATE \
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+ "eeprom write $(loadaddr) 0x0 $(filesize)"
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+# else
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+# define UBOOT_ENV_UPDATE \
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+ "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
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+ "sf erase 0 0x40000;" \
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+ "sf write $(loadaddr) 0 $(filesize)"
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+# endif
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+# else
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+# define UBOOT_ENV_UPDATE \
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+ "protect off 0x20000000 0x2003FFFF;" \
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+ "erase 0x20000000 0x2003FFFF;" \
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+ "cp.b $(loadaddr) 0x20000000 $(filesize)"
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+# endif
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+# define NETWORK_ENV_SETTINGS \
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+ "ubootfile=" UBOOT_ENV_FILE "\0" \
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+ "update=" \
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+ "tftp $(loadaddr) $(ubootfile);" \
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+ UBOOT_ENV_UPDATE \
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+ "\0" \
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+ "addip=set bootargs $(bootargs) " \
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+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
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+ "$(hostname):eth0:off" \
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+ "\0" \
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+ "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
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+ "ramboot=" \
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+ "tftp $(loadaddr) uImage;" \
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+ "run ramargs;" \
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+ "run addip;" \
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+ "bootm" \
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+ "\0" \
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+ "nfsargs=set bootargs " \
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+ "root=/dev/nfs rw " \
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+ "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
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+ "\0" \
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+ "nfsboot=" \
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+ "tftp $(loadaddr) vmImage;" \
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+ "run nfsargs;" \
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+ "run addip;" \
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+ "bootm" \
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+ "\0"
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+#else
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+# define NETWORK_ENV_SETTINGS
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+#endif
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+
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+/*
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+ * Console settings
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+ */
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+#define CONFIG_BAUDRATE 57600
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+#define CONFIG_LOADS_ECHO 1
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+#define CONFIG_UART_CONSOLE 0
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+
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+/*
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+ * I2C settings
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+ * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
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+ * Located on the expansion connector on pins 86/85
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+ * Note these pins are arbitrarily chosen because we aren't using
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+ * them yet. You can (and probably should) change these values!
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+ */
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+#ifdef CONFIG_SOFT_I2C
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+
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+#define PF_SCL PF9
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+#define PF_SDA PF8
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+
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+#define I2C_INIT do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0)
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+#define I2C_ACTIVE do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0)
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+#define I2C_TRISTATE do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0)
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+#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
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+#define I2C_SDA(bit) \
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+ do { \
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+ if (bit) \
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+ *pFIO_FLAG_S = PF_SDA; \
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+ else \
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+ *pFIO_FLAG_C = PF_SDA; \
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+ SSYNC(); \
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+ } while (0)
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+#define I2C_SCL(bit) \
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+ do { \
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+ if (bit) \
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+ *pFIO_FLAG_S = PF_SCL; \
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+ else \
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+ *pFIO_FLAG_C = PF_SCL; \
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+ SSYNC(); \
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+ } while (0)
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+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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+
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+#define CONFIG_SYS_I2C_SPEED 50000
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+#define CONFIG_SYS_I2C_SLAVE 0xFE
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+#endif
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+
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+/*
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+ * Miscellaneous configurable options
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+ */
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+#define CONFIG_RTC_BFIN 1
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+
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+/*
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+ * Serial Flash Infomation
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+ */
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+#define CONFIG_BFIN_SPI
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+/* For the M25P64 SCK Should be Kept < 20Mhz */
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+#define CONFIG_ENV_SPI_MAX_HZ 20000000
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+#define CONFIG_SF_DEFAULT_HZ 20000000
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+#define CONFIG_SPI_FLASH
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+#define CONFIG_SPI_FLASH_STMICRO
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+
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+/*
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+ * FLASH organization and environment definitions
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+ */
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+
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+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
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+#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
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+#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
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+#define CONFIG_EBIU_SDRRC_VAL 0x268
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+#define CONFIG_EBIU_SDGCTL_VAL 0x911109
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+
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+/* Even though Rev C boards have Parallel Flash
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+ * We aren't supporting it. Newer versions of the
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+ * hardware don't support Parallel Flash at all.
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+ */
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+#define CONFIG_SYS_NO_FLASH
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+#undef CONFIG_CMD_IMLS
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+#undef CONFIG_CMD_JFFS2
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+#undef CONFIG_CMD_FLASH
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+
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+#include <asm/blackfin-config-post.h>
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+
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+#endif
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