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@@ -347,6 +347,37 @@ static int genmii_read_status (struct uec_mii_info *mii_info)
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return 0;
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}
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+static int bcm_init(struct uec_mii_info *mii_info)
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+{
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+ struct eth_device *edev = mii_info->dev;
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+ uec_private_t *uec = edev->priv;
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+
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+ gbit_config_aneg(mii_info);
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+
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+ if (uec->uec_info->enet_interface == ENET_1000_RGMII_RXID) {
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+ u16 val;
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+ int cnt = 50;
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+
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+ /* Wait for aneg to complete. */
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+ do
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+ val = phy_read(mii_info, PHY_BMSR);
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+ while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
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+
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+ /* Set RDX clk delay. */
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+ phy_write(mii_info, 0x18, 0x7 | (7 << 12));
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+
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+ val = phy_read(mii_info, 0x18);
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+ /* Set RDX-RXC skew. */
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+ val |= (1 << 8);
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+ val |= (7 | (7 << 12));
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+ /* Write bits 14:0. */
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+ val |= (1 << 15);
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+ phy_write(mii_info, 0x18, val);
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+ }
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+
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+ return 0;
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+}
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+
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static int marvell_read_status (struct uec_mii_info *mii_info)
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{
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u16 status;
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@@ -515,6 +546,15 @@ static struct phy_info phy_info_marvell = {
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.config_intr = &marvell_config_intr,
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};
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+static struct phy_info phy_info_bcm5481 = {
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+ .phy_id = 0x0143bca0,
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+ .phy_id_mask = 0xffffff0,
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+ .name = "Broadcom 5481",
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+ .features = MII_GBIT_FEATURES,
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+ .read_status = genmii_read_status,
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+ .init = bcm_init,
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+};
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+
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static struct phy_info phy_info_genmii = {
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.phy_id = 0x00000000,
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.phy_id_mask = 0x00000000,
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@@ -528,6 +568,7 @@ static struct phy_info *phy_info[] = {
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&phy_info_dm9161,
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&phy_info_dm9161a,
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&phy_info_marvell,
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+ &phy_info_bcm5481,
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&phy_info_genmii,
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NULL
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};
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