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@@ -119,7 +119,7 @@ static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size
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/*
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* This function polls the NANDFC to wait for the basic operation to
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- * complete by checking the INT bit of config2 register.
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+ * complete by checking the INT bit.
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*/
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static void wait_op_done(struct mxc_nand_host *host, int max_retries,
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uint16_t param)
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@@ -127,10 +127,10 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries,
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uint32_t tmp;
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while (max_retries-- > 0) {
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- if (readw(&host->regs->config2) & NFC_INT) {
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- tmp = readw(&host->regs->config2);
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- tmp &= ~NFC_INT;
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- writew(tmp, &host->regs->config2);
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+ tmp = readnfc(&host->regs->config2);
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+ if (tmp & NFC_V1_V2_CONFIG2_INT) {
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+ tmp &= ~NFC_V1_V2_CONFIG2_INT;
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+ writenfc(tmp, &host->regs->config2);
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break;
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}
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udelay(1);
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@@ -149,8 +149,8 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
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{
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MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
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- writew(cmd, &host->regs->flash_cmd);
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- writew(NFC_CMD, &host->regs->config2);
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+ writenfc(cmd, &host->regs->flash_cmd);
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+ writenfc(NFC_CMD, &host->regs->operation);
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/* Wait for operation to complete */
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wait_op_done(host, TROP_US_DELAY, cmd);
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@@ -165,8 +165,8 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr)
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{
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MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
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- writew(addr, &host->regs->flash_addr);
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- writew(NFC_ADDR, &host->regs->config2);
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+ writenfc(addr, &host->regs->flash_addr);
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+ writenfc(NFC_ADDR, &host->regs->operation);
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/* Wait for operation to complete */
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wait_op_done(host, TROP_US_DELAY, addr);
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@@ -198,19 +198,19 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
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}
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}
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- writew(buf_id, &host->regs->buf_addr);
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+ writenfc(buf_id, &host->regs->buf_addr);
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/* Configure spare or page+spare access */
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if (!host->pagesize_2k) {
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- uint16_t config1 = readw(&host->regs->config1);
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+ uint16_t config1 = readnfc(&host->regs->config1);
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if (spare_only)
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- config1 |= NFC_SP_EN;
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+ config1 |= NFC_CONFIG1_SP_EN;
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else
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- config1 &= ~NFC_SP_EN;
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- writew(config1, &host->regs->config1);
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+ config1 &= ~NFC_CONFIG1_SP_EN;
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+ writenfc(config1, &host->regs->config1);
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}
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- writew(NFC_INPUT, &host->regs->config2);
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+ writenfc(NFC_INPUT, &host->regs->operation);
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/* Wait for operation to complete */
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wait_op_done(host, TROP_US_DELAY, spare_only);
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@@ -225,19 +225,19 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
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{
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MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
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- writew(buf_id, &host->regs->buf_addr);
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+ writenfc(buf_id, &host->regs->buf_addr);
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/* Configure spare or page+spare access */
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if (!host->pagesize_2k) {
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- uint32_t config1 = readw(&host->regs->config1);
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+ uint32_t config1 = readnfc(&host->regs->config1);
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if (spare_only)
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- config1 |= NFC_SP_EN;
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+ config1 |= NFC_CONFIG1_SP_EN;
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else
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- config1 &= ~NFC_SP_EN;
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- writew(config1, &host->regs->config1);
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+ config1 &= ~NFC_CONFIG1_SP_EN;
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+ writenfc(config1, &host->regs->config1);
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}
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- writew(NFC_OUTPUT, &host->regs->config2);
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+ writenfc(NFC_OUTPUT, &host->regs->operation);
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/* Wait for operation to complete */
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wait_op_done(host, TROP_US_DELAY, spare_only);
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@@ -265,14 +265,14 @@ static void send_read_id(struct mxc_nand_host *host)
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uint16_t tmp;
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/* NANDFC buffer 0 is used for device ID output */
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- writew(0x0, &host->regs->buf_addr);
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+ writenfc(0x0, &host->regs->buf_addr);
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/* Read ID into main buffer */
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- tmp = readw(&host->regs->config1);
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- tmp &= ~NFC_SP_EN;
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- writew(tmp, &host->regs->config1);
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+ tmp = readnfc(&host->regs->config1);
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+ tmp &= ~NFC_CONFIG1_SP_EN;
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+ writenfc(tmp, &host->regs->config1);
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- writew(NFC_ID, &host->regs->config2);
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+ writenfc(NFC_ID, &host->regs->operation);
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/* Wait for operation to complete */
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wait_op_done(host, TROP_US_DELAY, 0);
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@@ -292,14 +292,14 @@ static uint16_t get_dev_status(struct mxc_nand_host *host)
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/* store the main area1 first word, later do recovery */
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store = readl(main_buf);
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/* NANDFC buffer 1 is used for device status */
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- writew(1, &host->regs->buf_addr);
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+ writenfc(1, &host->regs->buf_addr);
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/* Read status into main buffer */
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- tmp = readw(&host->regs->config1);
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- tmp &= ~NFC_SP_EN;
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- writew(tmp, &host->regs->config1);
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+ tmp = readnfc(&host->regs->config1);
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+ tmp &= ~NFC_CONFIG1_SP_EN;
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+ writenfc(tmp, &host->regs->config1);
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- writew(NFC_STATUS, &host->regs->config2);
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+ writenfc(NFC_STATUS, &host->regs->operation);
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/* Wait for operation to complete */
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wait_op_done(host, TROP_US_DELAY, 0);
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@@ -328,13 +328,13 @@ static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct mxc_nand_host *host = nand_chip->priv;
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- uint16_t tmp = readw(&host->regs->config1);
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+ uint16_t tmp = readnfc(&host->regs->config1);
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if (on)
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- tmp |= NFC_ECC_EN;
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+ tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
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else
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- tmp &= ~NFC_ECC_EN;
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- writew(tmp, &host->regs->config1);
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+ tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
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+ writenfc(tmp, &host->regs->config1);
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}
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#ifdef CONFIG_MXC_NAND_HWECC
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@@ -667,7 +667,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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* additional correction. 2-Bit errors cannot be corrected by
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* HW ECC, so we need to return failure
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*/
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- uint16_t ecc_status = readw(&host->regs->ecc_status_result);
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+ uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
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if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
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MTDDEBUG(MTD_DEBUG_LEVEL0,
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@@ -1210,24 +1210,24 @@ int board_nand_init(struct nand_chip *this)
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#endif
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#ifdef MXC_NFC_V2_1
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- tmp = readw(&host->regs->config1);
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- tmp |= NFC_ONE_CYCLE;
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- tmp |= NFC_4_8N_ECC;
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- writew(tmp, &host->regs->config1);
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+ tmp = readnfc(&host->regs->config1);
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+ tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
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+ tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
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+ writenfc(tmp, &host->regs->config1);
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if (host->pagesize_2k)
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- writew(64/2, &host->regs->spare_area_size);
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+ writenfc(64/2, &host->regs->spare_area_size);
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else
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- writew(16/2, &host->regs->spare_area_size);
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+ writenfc(16/2, &host->regs->spare_area_size);
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#endif
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/*
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* preset operation
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* Unlock the internal RAM Buffer
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*/
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- writew(0x2, &host->regs->config);
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+ writenfc(0x2, &host->regs->config);
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/* Blocks to be unlocked */
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- writew(0x0, &host->regs->unlockstart_blkaddr);
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+ writenfc(0x0, &host->regs->unlockstart_blkaddr);
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/* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
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* unlockend_blkaddr, but the magic 0x4000 does not always work
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* when writing more than some 32 megabytes (on 2k page nands)
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@@ -1239,10 +1239,10 @@ int board_nand_init(struct nand_chip *this)
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* This might be NAND chip specific and the i.MX31 datasheet is
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* extremely vague about the semantics of this register.
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*/
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- writew(0xFFFF, &host->regs->unlockend_blkaddr);
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+ writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
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/* Unlock Block Command for given address range */
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- writew(0x4, &host->regs->wrprot);
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+ writenfc(0x4, &host->regs->wrprot);
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return 0;
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}
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