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@@ -55,6 +55,71 @@
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#define DP(x)
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#define DP(x)
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#endif
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#endif
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+static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
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+ {"PCI0DLL_1 "}, /* 30 */
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+ {"PCI0DLL_0 "}, /* 29 */
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+ {"PCI1DLL_2 "}, /* 28 */
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+ {"PCI1DLL_1 "}, /* 27 */
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+ {"PCI1DLL_0 "}, /* 26 */
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+ {"BbEP2En "}, /* 25 */
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+ {"SDRAMRdDataDel"}, /* 24 */
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+ {"SDRAMRdDel "}, /* 23 */
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+ {"SDRAMSync "}, /* 22 */
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+ {"SDRAMPipeSel_1"}, /* 21 */
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+ {"SDRAMPipeSel_0"}, /* 20 */
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+ {"SDRAMAddDel "}, /* 19 */
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+ {"SDRAMClkSel "}, /* 18 */
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+ {"Reserved(1!) "}, /* 17 */
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+ {"PCIRty "}, /* 16 */
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+ {"BootCSWidth_1 "}, /* 15 */
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+ {"BootCSWidth_0 "}, /* 14 */
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+ {"PCI1PadsCal "}, /* 13 */
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+ {"PCI0PadsCal "}, /* 12 */
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+ {"MultiMVId_1 "}, /* 11 */
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+ {"MultiMVId_0 "}, /* 10 */
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+ {"MultiGTEn "}, /* 09 */
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+ {"Int60xArb "}, /* 08 */
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+ {"CPUBusConfig_1"}, /* 07 */
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+ {"CPUBusConfig_0"}, /* 06 */
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+ {"DefIntSpc "}, /* 05 */
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+ {0 }, /* 04 */
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+ {"SROMAdd_1 "}, /* 03 */
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+ {"SROMAdd_0 "}, /* 02 */
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+ {"DRAMPadCal "}, /* 01 */
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+ {"SInitEn "}, /* 00 */
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+ {0 }, /* 31 */
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+ {0 }, /* 30 */
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+ {0 }, /* 29 */
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+ {0 }, /* 28 */
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+ {0 }, /* 27 */
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+ {0 }, /* 26 */
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+ {0 }, /* 25 */
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+ {0 }, /* 24 */
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+ {0 }, /* 23 */
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+ {0 }, /* 22 */
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+ {"JTAGCalBy "}, /* 21 */
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+ {"GB2Sel "}, /* 20 */
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+ {"GB1Sel "}, /* 19 */
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+ {"DRAMPLL_MDiv_5"}, /* 18 */
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+ {"DRAMPLL_MDiv_4"}, /* 17 */
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+ {"DRAMPLL_MDiv_3"}, /* 16 */
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+ {"DRAMPLL_MDiv_2"}, /* 15 */
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+ {"DRAMPLL_MDiv_1"}, /* 14 */
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+ {"DRAMPLL_MDiv_0"}, /* 13 */
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+ {"GB0Sel "}, /* 12 */
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+ {"DRAMPLLPU "}, /* 11 */
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+ {"DRAMPLL_HIKVCO"}, /* 10 */
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+ {"DRAMPLLNP "}, /* 09 */
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+ {"DRAMPLL_NDiv_7"}, /* 08 */
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+ {"DRAMPLL_NDiv_6"}, /* 07 */
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+ {"CPUPadCal "}, /* 06 */
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+ {"DRAMPLL_NDiv_5"}, /* 05 */
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+ {"DRAMPLL_NDiv_4"}, /* 04 */
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+ {"DRAMPLL_NDiv_3"}, /* 03 */
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+ {"DRAMPLL_NDiv_2"}, /* 02 */
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+ {"DRAMPLL_NDiv_1"}, /* 01 */
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+ {"DRAMPLL_NDiv_0"}}; /* 00 */
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+
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extern void flush_data_cache (void);
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extern void flush_data_cache (void);
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extern void invalidate_l1_instruction_cache (void);
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extern void invalidate_l1_instruction_cache (void);
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extern flash_info_t flash_info[];
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extern flash_info_t flash_info[];
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@@ -901,21 +966,37 @@ void board_prebootm_init ()
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dcache_disable ();
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dcache_disable ();
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}
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}
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-
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-int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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+int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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{
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unsigned int reset_sample_low;
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unsigned int reset_sample_low;
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unsigned int reset_sample_high;
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unsigned int reset_sample_high;
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+ unsigned int l, l1, l2;
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GT_REG_READ(0x3c4, &reset_sample_low);
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GT_REG_READ(0x3c4, &reset_sample_low);
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GT_REG_READ(0x3d4, &reset_sample_high);
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GT_REG_READ(0x3d4, &reset_sample_high);
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printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
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printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
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+ l2 = 0;
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+ for (l=0; l<63; l++) {
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+ if (show_config_tab[l][0] != 0) {
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+ printf("%14s:%1x ", show_config_tab[l],
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+ ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
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+ l2++;
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+ if ((l2 % 4) == 0)
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+ printf("\n");
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+ } else {
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+ l1++;
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+ }
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+ if (l == 32)
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+ reset_sample_low = reset_sample_high;
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+ }
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+ printf("\n");
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+
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return(0);
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return(0);
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}
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}
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U_BOOT_CMD(
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U_BOOT_CMD(
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- show_cfg, 1, 1, do_show_cfg,
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- "show_cfg- Show Marvell strapping register\n",
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+ show_config, 1, 1, do_show_config,
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+ "show_config - Show Marvell strapping register\n",
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"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
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"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
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);
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);
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