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fsl_esdhc: Set the eSHDC DMACTL[SNOOP] bit after resetting the controller

eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.

Signed-off-by: P.V.Suresh <pala@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P.V.Suresh 14 年之前
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2c1764efc2
共有 1 个文件被更改,包括 4 次插入4 次删除
  1. 4 4
      drivers/mmc/fsl_esdhc.c

+ 4 - 4
drivers/mmc/fsl_esdhc.c

@@ -384,10 +384,6 @@ static int esdhc_init(struct mmc *mmc)
 	int ret = 0;
 	int ret = 0;
 	u8 card_absent;
 	u8 card_absent;
 
 
-	/* Enable cache snooping */
-	if (cfg && !cfg->no_snoop)
-		esdhc_write32(&regs->scr, 0x00000040);
-
 	/* Reset the entire host controller */
 	/* Reset the entire host controller */
 	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
 	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
 
 
@@ -395,6 +391,10 @@ static int esdhc_init(struct mmc *mmc)
 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 		udelay(1000);
 		udelay(1000);
 
 
+	/* Enable cache snooping */
+	if (cfg && !cfg->no_snoop)
+		esdhc_write32(&regs->scr, 0x00000040);
+
 	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 
 
 	/* Set the initial clock speed */
 	/* Set the initial clock speed */