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+/*
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+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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+ *
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+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
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+ * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
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+ *
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+ * Parts are shamelessly stolen from various TI sources, original copyright
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+ * follows:
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+ *
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+ * Copyright (C) 2004 Texas Instruments.
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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+ */
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+
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+#include <common.h>
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+#include <i2c.h>
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+#include <asm/arch/hardware.h>
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+#include <asm/arch/emac_defs.h>
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+
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+#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
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+#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */
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+
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+#define INTEGRITY_SYSCFG_OFFSET 0x7E8
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+#define INTEGRITY_CHECKWORD_OFFSET 0x7F8
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+#define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+extern void timer_init(void);
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+extern int eth_hw_init(void);
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+extern phy_t phy;
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+
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+
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+/* Works on Always On power domain only (no PD argument) */
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+void lpsc_on(unsigned int id)
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+{
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+ dv_reg_p mdstat, mdctl;
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+
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+ if (id >= DAVINCI_LPSC_GEM)
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+ return; /* Don't work on DSP Power Domain */
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+
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+ mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
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+ mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
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+
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+ while (REG(PSC_PTSTAT) & 0x01);
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+
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+ if ((*mdstat & 0x1f) == 0x03)
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+ return; /* Already on and enabled */
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+
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+ *mdctl |= 0x03;
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+
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+ /* Special treatment for some modules as for sprue14 p.7.4.2 */
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+ switch (id) {
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+ case DAVINCI_LPSC_VPSSSLV:
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+ case DAVINCI_LPSC_EMAC:
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+ case DAVINCI_LPSC_EMAC_WRAPPER:
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+ case DAVINCI_LPSC_MDIO:
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+ case DAVINCI_LPSC_USB:
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+ case DAVINCI_LPSC_ATA:
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+ case DAVINCI_LPSC_VLYNQ:
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+ case DAVINCI_LPSC_UHPI:
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+ case DAVINCI_LPSC_DDR_EMIF:
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+ case DAVINCI_LPSC_AEMIF:
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+ case DAVINCI_LPSC_MMC_SD:
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+ case DAVINCI_LPSC_MEMSTICK:
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+ case DAVINCI_LPSC_McBSP:
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+ case DAVINCI_LPSC_GPIO:
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+ *mdctl |= 0x200;
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+ break;
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+ }
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+
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+ REG(PSC_PTCMD) = 0x01;
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+
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+ while (REG(PSC_PTSTAT) & 0x03);
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+ while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */
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+}
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+
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+#if !defined(CFG_USE_DSPLINK)
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+void dsp_on(void)
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+{
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+ int i;
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+
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+ if (REG(PSC_PDSTAT1) & 0x1f)
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+ return; /* Already on */
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+
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+ REG(PSC_GBLCTL) |= 0x01;
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+ REG(PSC_PDCTL1) |= 0x01;
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+ REG(PSC_PDCTL1) &= ~0x100;
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+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
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+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
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+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
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+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
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+ REG(PSC_PTCMD) = 0x02;
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+
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+ for (i = 0; i < 100; i++) {
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+ if (REG(PSC_EPCPR) & 0x02)
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+ break;
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+ }
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+
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+ REG(PSC_CHP_SHRTSW) = 0x01;
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+ REG(PSC_PDCTL1) |= 0x100;
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+ REG(PSC_EPCCR) = 0x02;
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+
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+ for (i = 0; i < 100; i++) {
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+ if (!(REG(PSC_PTSTAT) & 0x02))
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+ break;
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+ }
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+
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+ REG(PSC_GBLCTL) &= ~0x1f;
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+}
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+#endif /* CFG_USE_DSPLINK */
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+
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+int board_init(void)
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+{
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+ /* arch number of the board */
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+ gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
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+
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+ /* address of boot parameters */
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+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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+
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+ /* Workaround for TMS320DM6446 errata 1.3.22 */
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+ REG(PSC_SILVER_BULLET) = 0;
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+
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+ /* Power on required peripherals */
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+ lpsc_on(DAVINCI_LPSC_EMAC);
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+ lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
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+ lpsc_on(DAVINCI_LPSC_MDIO);
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+ lpsc_on(DAVINCI_LPSC_I2C);
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+ lpsc_on(DAVINCI_LPSC_UART0);
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+ lpsc_on(DAVINCI_LPSC_TIMER1);
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+ lpsc_on(DAVINCI_LPSC_GPIO);
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+
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+#if !defined(CFG_USE_DSPLINK)
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+ /* Powerup the DSP */
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+ dsp_on();
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+#endif /* CFG_USE_DSPLINK */
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+
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+ /* Bringup UART0 out of reset */
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+ REG(UART0_PWREMU_MGMT) = 0x0000e003;
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+
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+ /* Enable GIO3.3V cells used for EMAC */
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+ REG(VDD3P3V_PWDN) = 0;
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+
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+ /* Enable UART0 MUX lines */
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+ REG(PINMUX1) |= 1;
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+
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+ /* Enable EMAC and AEMIF pins */
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+ REG(PINMUX0) = 0x80000c1f;
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+
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+ /* Enable I2C pin Mux */
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+ REG(PINMUX1) |= (1 << 7);
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+
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+ /* Set the Bus Priority Register to appropriate value */
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+ REG(VBPR) = 0x20;
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+
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+ timer_init();
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+
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+ return(0);
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+}
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+
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+/* Read ethernet MAC address from Integrity data structure inside EEPROM. */
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+int read_mac_address(uint8_t *buf)
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+{
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+ u_int32_t value, mac[2], address;
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+
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+ /* Read Integrity data structure checkword. */
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+ if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
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+ CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
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+ goto err;
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+ if (value != INTEGRITY_CHECKWORD_VALUE)
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+ return 1;
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+
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+ /* Read SYSCFG structure offset. */
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+ if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
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+ CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
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+ goto err;
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+ address = 0x800 + (int) value; /* Address of SYSCFG structure. */
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+
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+ /* Read NET CONFIG structure offset. */
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+ if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
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+ CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
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+ goto err;
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+ address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
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+ address += 12; /* Address of NET INTERFACE CONFIG structure. */
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+
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+ /* Read NET INTERFACE CONFIG 2 structure offset. */
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+ if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
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+ CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
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+ goto err;
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+ address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE
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+ * CONFIG 2 structure. */
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+
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+ /* Read MAC address. */
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+ if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
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+ CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
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+ goto err;
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+
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+ buf[0] = mac[0] >> 24;
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+ buf[1] = mac[0] >> 16;
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+ buf[2] = mac[0] >> 8;
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+ buf[3] = mac[0];
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+ buf[4] = mac[1] >> 24;
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+ buf[5] = mac[1] >> 16;
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+
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+ return 0;
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+
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+err:
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+ printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR);
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+ return 1;
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+}
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+
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+/* Platform dependent initialisation. */
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+int misc_init_r(void)
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+{
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+ int i;
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+ u_int8_t i2cbuf;
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+ u_int8_t env_enetaddr[6], eeprom_enetaddr[6];
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+ char *tmp = getenv("ethaddr");
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+ char *end;
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+ int clk;
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+
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+ /* EMIF-A CS3 configuration for FPGA. */
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+ REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
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+
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+ clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
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+
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+ printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2);
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+ printf("DDR Clock: %dMHz\n", (clk / 2));
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+
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+ /* Configure I2C switch (PCA9543) to enable channel 0. */
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+ i2cbuf = CFG_I2C_PCA9543_ENABLE_CH0;
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+ if (i2c_write(CFG_I2C_PCA9543_ADDR, 0,
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+ CFG_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
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+ printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR);
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+ return 1;
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+ }
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+
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+ /* Read Ethernet MAC address from the U-Boot environment. */
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+ for (i = 0; i < 6; i++) {
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+ env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
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+ if (tmp)
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+ tmp = (*end) ? end+1 : end;
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+ }
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+
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+ /* Read Ethernet MAC address from EEPROM. */
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+ if (read_mac_address(eeprom_enetaddr) == 0) {
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+ if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
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+ memcmp(env_enetaddr, eeprom_enetaddr, 6) != 0) {
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+ printf("\nWarning: MAC addresses don't match:\n");
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+ printf("\tHW MAC address: "
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+ "%02X:%02X:%02X:%02X:%02X:%02X\n",
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+ eeprom_enetaddr[0], eeprom_enetaddr[1],
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+ eeprom_enetaddr[2], eeprom_enetaddr[3],
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+ eeprom_enetaddr[4], eeprom_enetaddr[5]);
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+ printf("\t\"ethaddr\" value: "
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+ "%02X:%02X:%02X:%02X:%02X:%02X\n",
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+ env_enetaddr[0], env_enetaddr[1],
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+ env_enetaddr[2], env_enetaddr[3],
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+ env_enetaddr[4], env_enetaddr[5]) ;
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+ debug("### Set MAC addr from environment\n");
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+ memcpy(eeprom_enetaddr, env_enetaddr, 6);
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+ }
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+ if (!tmp) {
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+ char ethaddr[20];
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+
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+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
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+ eeprom_enetaddr[0], eeprom_enetaddr[1],
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+ eeprom_enetaddr[2], eeprom_enetaddr[3],
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+ eeprom_enetaddr[4], eeprom_enetaddr[5]) ;
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+ debug("### Set environment from HW MAC addr = \"%s\"\n",
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+ ethaddr);
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+ setenv("ethaddr", ethaddr);
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+ }
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+ }
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+
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+ if (!eth_hw_init()) {
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+ printf("Ethernet init failed\n");
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+ } else {
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+ printf("ETH PHY: %s\n", phy.name);
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+ }
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+
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+ /* On this platform, U-Boot is copied in RAM by the UBL,
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+ * so we are always in the relocated state. */
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+ gd->flags |= GD_FLG_RELOC;
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+
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+ return(0);
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+}
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+
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+int dram_init(void)
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+{
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+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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+
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+ return(0);
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+}
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Hugo Villeneuve