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@@ -1,5 +1,5 @@
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/*
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- * (C) Copyright 2000-2005
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+ * (C) Copyright 2000-2008
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@@ -65,10 +65,17 @@
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_8xx\0" \
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- "bootfile=/tftpboot/fps850L/uImage\0" \
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+ "hostname=FPS860L\0" \
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+ "bootfile=FPS860L/uImage\0" \
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"fdt_addr=40040000\0" \
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"kernel_addr=40060000\0" \
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"ramdisk_addr=40200000\0" \
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+ "u-boot=FPS860L/u-image.bin\0" \
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+ "load=tftp 200000 ${u-boot}\0" \
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+ "update=prot off 40000000 +${filesize};" \
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+ "era 40000000 +${filesize};" \
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+ "cp.b 200000 40000000 ${filesize};" \
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+ "sete filesize;save\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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@@ -106,10 +113,14 @@
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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+#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_SNTP
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+#define CONFIG_NETCONSOLE
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+
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+
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/*
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* Miscellaneous configurable options
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*/
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@@ -180,11 +191,15 @@
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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-#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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+/* use CFI flash driver */
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+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
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+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
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+#define CFG_FLASH_EMPTY_INFO
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+#define CFG_FLASH_USE_BUFFER_WRITE 1
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+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
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@@ -194,6 +209,20 @@
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
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+
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+/*-----------------------------------------------------------------------
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+ * Dynamic MTD partition support
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+ */
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+#define CONFIG_JFFS2_CMDLINE
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+#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
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+
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+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
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+ "128k(dtb)," \
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+ "1664k(kernel)," \
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+ "2m(rootfs)," \
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+ "4m(data)"
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+
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/*-----------------------------------------------------------------------
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* Hardware Information Block
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*/
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@@ -306,9 +335,11 @@
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
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-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
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-#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
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- OR_SCY_5_CLK | OR_EHTR)
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+/*
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+ * FLASH timing:
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+ */
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+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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+ OR_SCY_3_CLK | OR_EHTR | OR_BI)
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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@@ -337,12 +368,42 @@
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/*
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* Memory Periodic Timer Prescaler
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+ *
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+ * The Divider for PTA (refresh timer) configuration is based on an
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+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
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+ * the number of chip selects (NCS) and the actually needed refresh
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+ * rate is done by setting MPTPR.
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+ *
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+ * PTA is calculated from
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+ * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
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+ *
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+ * gclk CPU clock (not bus clock!)
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+ * Trefresh Refresh cycle * 4 (four word bursts used)
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+ *
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+ * 4096 Rows from SDRAM example configuration
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+ * 1000 factor s -> ms
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+ * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
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+ * 4 Number of refresh cycles per period
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+ * 64 Refresh cycle in ms per number of rows
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+ * --------------------------------------------
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+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
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+ *
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+ * 50 MHz => 50.000.000 / Divider = 98
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+ * 66 Mhz => 66.000.000 / Divider = 129
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+ * 80 Mhz => 80.000.000 / Divider = 156
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*/
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-/* periodic timer for refresh */
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-#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
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+#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
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+#define CFG_MAMR_PTA 98
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-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
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+/*
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+ * For 16 MBit, refresh rates could be 31.3 us
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+ * (= 64 ms / 2K = 125 / quad bursts).
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+ * For a simpler initialization, 15.6 us is used instead.
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+ *
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+ * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
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+ * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
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+ */
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
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@@ -372,4 +433,6 @@
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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+#define CONFIG_SCC1_ENET
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+
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#endif /* __CONFIG_H */
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