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+/*
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+ * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
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+ * (C) Copyright 2004-2008
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+ * Texas Instruments, <www.ti.com>
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+ *
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+ * Derived from Beagle Board code by
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+ * Sunil Kumar <sunilsaini05@gmail.com>
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+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
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+ *
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc.
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+ */
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+#include <common.h>
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+#include <usb.h>
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+#include <asm/io.h>
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+#include <asm/gpio.h>
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+#include <asm/arch/clocks.h>
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+#include <asm/arch/clocks_omap3.h>
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+#include <asm/arch/ehci_omap3.h>
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+#include <asm/arch/sys_proto.h>
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+#include "ehci-core.h"
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+
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+inline int __board_usb_init(void)
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+{
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+ return 0;
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+}
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+int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
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+
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+#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
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+ defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
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+/* controls PHY(s) reset signal(s) */
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+static inline void omap_ehci_phy_reset(int on, int delay)
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+{
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+ /*
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+ * Refer ISSUE1:
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+ * Hold the PHY in RESET for enough time till
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+ * PHY is settled and ready
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+ */
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+ if (delay && !on)
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+ udelay(delay);
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+#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
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+ gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
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+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
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+#endif
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+#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
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+ gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
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+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
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+#endif
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+
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+ /* Hold the PHY in RESET for enough time till DIR is high */
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+ /* Refer: ISSUE1 */
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+ if (delay && on)
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+ udelay(delay);
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+}
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+#else
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+#define omap_ehci_phy_reset(on, delay) do {} while (0)
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+#endif
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+
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+/* Reset is needed otherwise the kernel-driver will throw an error. */
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+int ehci_hcd_stop(void)
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+{
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+ debug("Resetting OMAP3 EHCI\n");
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+ omap_ehci_phy_reset(1, 0);
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+ writel(OMAP_UHH_SYSCONFIG_SOFTRESET,
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+ OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
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+ /* disable USB clocks */
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+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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+ sr32(&prcm_base->iclken_usbhost, 0, 1, 0);
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+ sr32(&prcm_base->fclken_usbhost, 0, 2, 0);
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+ sr32(&prcm_base->iclken3_core, 2, 1, 0);
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+ sr32(&prcm_base->fclken3_core, 2, 1, 0);
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+ return 0;
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+}
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+
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+/*
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+ * Initialize the OMAP3 EHCI controller and PHY.
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+ * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
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+ * See there for additional Copyrights.
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+ */
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+int ehci_hcd_init(void)
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+{
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+ int ret;
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+
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+ debug("Initializing OMAP3 EHCI\n");
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+
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+ ret = board_usb_init();
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+ if (ret < 0)
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+ return ret;
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+
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+ /* Put the PHY in RESET */
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+ omap_ehci_phy_reset(1, 10);
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+
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+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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+ /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
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+ sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
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+ /*
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+ * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
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+ * and USBHOST_120M_FCLK (USBHOST_FCLK2)
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+ */
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+ sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
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+ /* Enable USBTTL_ICLK */
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+ sr32(&prcm_base->iclken3_core, 2, 1, 1);
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+ /* Enable USBTTL_FCLK */
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+ sr32(&prcm_base->fclken3_core, 2, 1, 1);
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+ debug("USB clocks enabled\n");
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+
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+ /* perform TLL soft reset, and wait until reset is complete */
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+ writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
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+ OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
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+ /* Wait for TLL reset to complete */
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+ while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
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+ & OMAP_USBTLL_SYSSTATUS_RESETDONE))
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+ ;
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+ debug("TLL reset done\n");
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+
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+ writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
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+ OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
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+ OMAP_USBTLL_SYSCONFIG_CACTIVITY,
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+ OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
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+
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+ /* Put UHH in NoIdle/NoStandby mode */
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+ writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP
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+ | OMAP_UHH_SYSCONFIG_SIDLEMODE
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+ | OMAP_UHH_SYSCONFIG_CACTIVITY
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+ | OMAP_UHH_SYSCONFIG_MIDLEMODE,
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+ OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
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+
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+ /* setup burst configurations */
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+ writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
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+ | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
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+ | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,
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+ OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);
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+
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+ omap_ehci_phy_reset(0, 10);
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+
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+ hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
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+ hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
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+
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+ debug("OMAP3 EHCI init done\n");
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+ return 0;
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+}
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Ilya Yanok