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@@ -179,10 +179,47 @@ in_flash:
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#endif
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#endif /* CFG_RAMBOOT */
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- bl setup_stack_in_data_cache_on_r1
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+ /* setup the bats */
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+ bl setup_bats
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+ sync
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+
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+ /*
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+ * Cache must be enabled here for stack-in-cache trick.
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+ * This means we need to enable the BATS.
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+ * This means:
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+ * 1) for the EVB, original gt regs need to be mapped
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+ * 2) need to have an IBAT for the 0xf region,
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+ * we are running there!
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+ * Cache should be turned on after BATs, since by default
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+ * everything is write-through.
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+ * The init-mem BAT can be reused after reloc. The old
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+ * gt-regs BAT can be reused after board_init_f calls
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+ * board_early_init_f (EVB only).
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+ */
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+ /* enable address translation */
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+ bl enable_addr_trans
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+ sync
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+
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+ /* enable and invalidate the data cache */
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+ bl dcache_enable
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+ sync
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+#ifdef CFG_INIT_RAM_LOCK
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+ bl lock_ram_in_cache
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+ sync
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+#endif
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+
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+ /* set up the stack pointer in our newly created
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+ * cache-ram (r1) */
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+ lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
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+ ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
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+
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+ li r0, 0 /* Make room for stack frame header and */
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+ stwu r0, -4(r1) /* clear final stack frame so that */
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+ stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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+
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/* let the C-code set up the rest */
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- /* */
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+ /* */
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/* Be careful to keep code relocatable & stack humble */
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/*------------------------------------------------------*/
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@@ -509,6 +546,221 @@ init_e300_core: /* time t 10 */
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/*------------------------------*/
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blr
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+ .globl invalidate_bats
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+invalidate_bats:
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+ /* invalidate BATs */
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+ mtspr IBAT0U, r0
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+ mtspr IBAT1U, r0
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+ mtspr IBAT2U, r0
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+ mtspr IBAT3U, r0
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+#if (CFG_HID2 & HID2_HBE)
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+ mtspr IBAT4U, r0
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+ mtspr IBAT5U, r0
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+ mtspr IBAT6U, r0
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+ mtspr IBAT7U, r0
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+#endif
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+ isync
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+ mtspr DBAT0U, r0
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+ mtspr DBAT1U, r0
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+ mtspr DBAT2U, r0
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+ mtspr DBAT3U, r0
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+#if (CFG_HID2 & HID2_HBE)
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+ mtspr DBAT4U, r0
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+ mtspr DBAT5U, r0
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+ mtspr DBAT6U, r0
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+ mtspr DBAT7U, r0
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+#endif
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+ isync
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+ sync
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+ blr
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+
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+ /* setup_bats - set them up to some initial state */
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+ .globl setup_bats
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+setup_bats:
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+ addis r0, r0, 0x0000
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+
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+ /* IBAT 0 */
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+ addis r4, r0, CFG_IBAT0L@h
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+ ori r4, r4, CFG_IBAT0L@l
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+ addis r3, r0, CFG_IBAT0U@h
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+ ori r3, r3, CFG_IBAT0U@l
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+ mtspr IBAT0L, r4
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+ mtspr IBAT0U, r3
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+ isync
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+
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+ /* DBAT 0 */
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+ addis r4, r0, CFG_DBAT0L@h
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+ ori r4, r4, CFG_DBAT0L@l
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+ addis r3, r0, CFG_DBAT0U@h
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+ ori r3, r3, CFG_DBAT0U@l
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+ mtspr DBAT0L, r4
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+ mtspr DBAT0U, r3
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+ isync
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+
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+ /* IBAT 1 */
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+ addis r4, r0, CFG_IBAT1L@h
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+ ori r4, r4, CFG_IBAT1L@l
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+ addis r3, r0, CFG_IBAT1U@h
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+ ori r3, r3, CFG_IBAT1U@l
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+ mtspr IBAT1L, r4
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+ mtspr IBAT1U, r3
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+ isync
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+
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+ /* DBAT 1 */
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+ addis r4, r0, CFG_DBAT1L@h
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+ ori r4, r4, CFG_DBAT1L@l
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+ addis r3, r0, CFG_DBAT1U@h
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+ ori r3, r3, CFG_DBAT1U@l
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+ mtspr DBAT1L, r4
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+ mtspr DBAT1U, r3
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+ isync
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+
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+ /* IBAT 2 */
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+ addis r4, r0, CFG_IBAT2L@h
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+ ori r4, r4, CFG_IBAT2L@l
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+ addis r3, r0, CFG_IBAT2U@h
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+ ori r3, r3, CFG_IBAT2U@l
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+ mtspr IBAT2L, r4
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+ mtspr IBAT2U, r3
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+ isync
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+
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+ /* DBAT 2 */
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+ addis r4, r0, CFG_DBAT2L@h
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+ ori r4, r4, CFG_DBAT2L@l
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+ addis r3, r0, CFG_DBAT2U@h
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+ ori r3, r3, CFG_DBAT2U@l
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+ mtspr DBAT2L, r4
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+ mtspr DBAT2U, r3
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+ isync
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+
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+ /* IBAT 3 */
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+ addis r4, r0, CFG_IBAT3L@h
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+ ori r4, r4, CFG_IBAT3L@l
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+ addis r3, r0, CFG_IBAT3U@h
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+ ori r3, r3, CFG_IBAT3U@l
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+ mtspr IBAT3L, r4
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+ mtspr IBAT3U, r3
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+ isync
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+
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+ /* DBAT 3 */
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+ addis r4, r0, CFG_DBAT3L@h
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+ ori r4, r4, CFG_DBAT3L@l
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+ addis r3, r0, CFG_DBAT3U@h
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+ ori r3, r3, CFG_DBAT3U@l
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+ mtspr DBAT3L, r4
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+ mtspr DBAT3U, r3
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+ isync
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+
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+#if (CFG_HID2 & HID2_HBE)
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+ /* IBAT 4 */
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+ addis r4, r0, CFG_IBAT4L@h
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+ ori r4, r4, CFG_IBAT4L@l
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+ addis r3, r0, CFG_IBAT4U@h
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+ ori r3, r3, CFG_IBAT4U@l
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+ mtspr IBAT4L, r4
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+ mtspr IBAT4U, r3
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+ isync
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+
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+ /* DBAT 4 */
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+ addis r4, r0, CFG_DBAT4L@h
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+ ori r4, r4, CFG_DBAT4L@l
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+ addis r3, r0, CFG_DBAT4U@h
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+ ori r3, r3, CFG_DBAT4U@l
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+ mtspr DBAT4L, r4
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+ mtspr DBAT4U, r3
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+ isync
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+
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+ /* IBAT 5 */
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+ addis r4, r0, CFG_IBAT5L@h
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+ ori r4, r4, CFG_IBAT5L@l
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+ addis r3, r0, CFG_IBAT5U@h
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+ ori r3, r3, CFG_IBAT5U@l
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+ mtspr IBAT5L, r4
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+ mtspr IBAT5U, r3
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+ isync
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+
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+ /* DBAT 5 */
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+ addis r4, r0, CFG_DBAT5L@h
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+ ori r4, r4, CFG_DBAT5L@l
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+ addis r3, r0, CFG_DBAT5U@h
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+ ori r3, r3, CFG_DBAT5U@l
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+ mtspr DBAT5L, r4
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+ mtspr DBAT5U, r3
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+ isync
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+
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+ /* IBAT 6 */
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+ addis r4, r0, CFG_IBAT6L@h
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+ ori r4, r4, CFG_IBAT6L@l
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+ addis r3, r0, CFG_IBAT6U@h
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+ ori r3, r3, CFG_IBAT6U@l
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+ mtspr IBAT6L, r4
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+ mtspr IBAT6U, r3
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+ isync
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+
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+ /* DBAT 6 */
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+ addis r4, r0, CFG_DBAT6L@h
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+ ori r4, r4, CFG_DBAT6L@l
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+ addis r3, r0, CFG_DBAT6U@h
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+ ori r3, r3, CFG_DBAT6U@l
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+ mtspr DBAT6L, r4
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+ mtspr DBAT6U, r3
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+ isync
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+
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+ /* IBAT 7 */
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+ addis r4, r0, CFG_IBAT7L@h
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+ ori r4, r4, CFG_IBAT7L@l
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+ addis r3, r0, CFG_IBAT7U@h
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+ ori r3, r3, CFG_IBAT7U@l
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+ mtspr IBAT7L, r4
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+ mtspr IBAT7U, r3
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+ isync
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+
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+ /* DBAT 7 */
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+ addis r4, r0, CFG_DBAT7L@h
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+ ori r4, r4, CFG_DBAT7L@l
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+ addis r3, r0, CFG_DBAT7U@h
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+ ori r3, r3, CFG_DBAT7U@l
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+ mtspr DBAT7L, r4
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+ mtspr DBAT7U, r3
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+ isync
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+#endif
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+
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+ /* Invalidate TLBs.
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+ * -> for (val = 0; val < 0x20000; val+=0x1000)
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+ * -> tlbie(val);
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+ */
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+ lis r3, 0
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+ lis r5, 2
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+
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+1:
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+ tlbie r3
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+ addi r3, r3, 0x1000
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+ cmp 0, 0, r3, r5
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+ blt 1b
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+
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+ blr
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+
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+ .globl enable_addr_trans
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+enable_addr_trans:
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+ /* enable address translation */
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+ mfmsr r5
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+ ori r5, r5, (MSR_IR | MSR_DR)
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+ mtmsr r5
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+ isync
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+ blr
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+
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+ .globl disable_addr_trans
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+disable_addr_trans:
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+ /* disable address translation */
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+ mflr r4
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+ mfmsr r3
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+ andi. r0, r3, (MSR_IR | MSR_DR)
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+ beqlr
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+ andc r3, r3, r0
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+ mtspr SRR0, r4
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+ mtspr SRR1, r3
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+ rfi
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+
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/* Cache functions.
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*
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* Note: requires that all cache bits in
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@@ -550,26 +802,25 @@ icache_status:
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.globl dcache_enable
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dcache_enable:
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mfspr r3, HID0
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- ori r3, r3, HID0_ENABLE_DATA_CACHE
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- lis r4, 0
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- ori r4, r4, HID0_LOCK_DATA_CACHE
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- andc r3, r3, r4
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- ori r4, r3, HID0_LOCK_INSTRUCTION_CACHE
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- sync
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- mtspr HID0, r4 /* sets enable and invalidate, clears lock */
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+ li r5, HID0_DCFI|HID0_DLOCK
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+ andc r3, r3, r5
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+ mtspr HID0, r3 /* no invalidate, unlock */
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+ ori r3, r3, HID0_DCE
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+ ori r5, r3, HID0_DCFI
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+ mtspr HID0, r5 /* enable + invalidate */
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+ mtspr HID0, r3 /* enable */
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sync
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- mtspr HID0, r3 /* clears invalidate */
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blr
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.globl dcache_disable
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dcache_disable:
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mfspr r3, HID0
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lis r4, 0
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- ori r4, r4, HID0_ENABLE_DATA_CACHE|HID0_LOCK_DATA_CACHE
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+ ori r4, r4, HID0_DCE|HID0_DLOCK
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andc r3, r3, r4
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- ori r4, r3, HID0_INVALIDATE_DATA_CACHE
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+ ori r4, r3, HID0_DCI
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sync
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- mtspr HID0, r4 /* sets invalidate, clears enable and lock */
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+ mtspr HID0, r4 /* sets invalidate, clears enable and lock */
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sync
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mtspr HID0, r3 /* clears invalidate */
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blr
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@@ -674,46 +925,29 @@ relocate_code:
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* Now flush the cache: note that we must start from a cache aligned
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* address. Otherwise we might miss one cache line.
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*/
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-4:
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- bl un_setup_stack_in_data_cache
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- mr r7, r3
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- mr r8, r4
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- bl dcache_disable
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- mr r3, r7
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- mr r4, r8
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-
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- cmpwi r6,0
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+4: cmpwi r6,0
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add r5,r3,r5
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- beq 7f /* Always flush prefetch queue in any case */
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+ beq 7f /* Always flush prefetch queue in any case */
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subi r0,r6,1
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andc r3,r3,r0
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- mfspr r7,HID0 /* don't do dcbst if dcache is disabled*/
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- rlwinm r7,r7,HID0_DCE_SHIFT,31,31
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- cmpwi r7,0
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- beq 9f
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mr r4,r3
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5: dcbst 0,r4
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add r4,r4,r6
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cmplw r4,r5
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blt 5b
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- sync /* Wait for all dcbst to complete on bus */
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-9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
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- rlwinm r7,r7,HID0_DCE_SHIFT,31,31
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- cmpwi r7,0
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- beq 7f
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+ sync /* Wait for all dcbst to complete on bus */
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mr r4,r3
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6: icbi 0,r4
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add r4,r4,r6
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cmplw r4,r5
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blt 6b
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-7: sync /* Wait for all icbi to complete on bus */
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+7: sync /* Wait for all icbi to complete on bus */
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isync
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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-
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addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
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mtlr r0
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blr
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@@ -871,6 +1105,27 @@ trap_reloc:
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blr
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#ifdef CFG_INIT_RAM_LOCK
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+lock_ram_in_cache:
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+ /* Allocate Initial RAM in data cache.
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+ */
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+ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
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+ ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
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+ li r2, ((CFG_INIT_RAM_END & ~31) + \
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+ (CFG_INIT_RAM_ADDR & 31) + 31) / 32
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+ mtctr r2
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+1:
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+ dcbz r0, r3
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+ addi r3, r3, 32
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+ bdnz 1b
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+
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+ /* Lock the data cache */
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+ mfspr r0, HID0
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+ ori r0, r0, 0x1000
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+ sync
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+ mtspr HID0, r0
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+ sync
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+ blr
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+
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.globl unlock_ram_in_cache
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unlock_ram_in_cache:
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/* invalidate the INIT_RAM section */
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@@ -884,6 +1139,15 @@ unlock_ram_in_cache:
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bdnz 1b
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sync /* Wait for all icbi to complete on bus */
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isync
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+
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+ /* Unlock the data cache and invalidate it */
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+ mfspr r3, HID0
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+ li r5, HID0_DLOCK|HID0_DCFI
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+ andc r3, r3, r5 /* no invalidate, unlock */
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+ ori r5, r3, HID0_DCFI /* invalidate, unlock */
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+ mtspr HID0, r5 /* invalidate, unlock */
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+ mtspr HID0, r3 /* no invalidate, unlock */
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+ sync
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blr
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#endif
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@@ -952,148 +1216,3 @@ remap_flash_by_law0:
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stw r4, LBLAWBAR1(r3)
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stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
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blr
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-
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-setup_stack_in_data_cache_on_r1:
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- lis r3, (CFG_IMMRBAR)@h
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-
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- /* setup D-BAT for the D-Cache (with out real memory backup) */
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-
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- lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
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- mtspr DBAT0U, r4
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- ori r4, r4, 0x0002
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- mtspr DBAT0L, r4
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- isync
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-
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-#if 0
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- /* Enable MMU */
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- mfmsr r4
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- ori r4, r4, (MSR_DR | MSR_IR)@l
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- mtmsr r4
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-#endif
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-
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- /* Enable and invalidate data cache. */
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- mfspr r4, HID0
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- mr r5, r4
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- ori r4, r4, HID0_DCE | HID0_DCI
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- ori r5, r5, HID0_DCE
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- sync
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- mtspr HID0, r4
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- mtspr HID0, r5
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- sync
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-
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- /* Allocate Initial RAM in data cache.*/
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- li r0, 0
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- lis r4, (CFG_INIT_RAM_ADDR)@h
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- ori r4, r4, (CFG_INIT_RAM_ADDR)@l
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- li r5, 128*8 /* 128*8*32=32Kb */
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- mtctr r5
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-1:
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- dcbz r0, r4
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- addi r4, r4, 32
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- bdnz 1b
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- isync
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-
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- /* Lock all the D-cache, basically leaving the reset of the program without dcache */
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- mfspr r4, HID0
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- ori r4, r4, (HID0_DLOCK)@l
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- sync
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- mtspr HID0 , r4
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-
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- /* setup the stack pointer in r1 */
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- lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
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- ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
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- li r0, 0 /* Make room for stack frame header and */
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-
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- stwu r0, -4(r1) /* clear final stack frame so that */
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- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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-
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- blr
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-
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-un_setup_stack_in_data_cache:
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- blr
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- mr r14, r4
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- mr r15, r5
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-
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-
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- lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
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- mtspr DBAT0U, r4
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- ori r4, r4, 0x0002
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- mtspr DBAT0L, r4
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- isync
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-
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- /* un lock all the D-cache */
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- mfspr r4, HID0
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- lis r5, (~(HID0_DLOCK))@h
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- ori r5, r5, (~(HID0_DLOCK))@l
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- and r4, r4, r5
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- sync
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- mtspr HID0 , r4
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-
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- /* Re - Allocate Initial RAM in data cache.*/
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- li r0, 0
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- lis r4, (CFG_INIT_RAM_ADDR)@h
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- ori r4, r4, (CFG_INIT_RAM_ADDR)@l
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- li r5, 128*8 /* 128*8*32=32Kb */
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- mtctr r5
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-1:
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- dcbz r0, r4
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- addi r4, r4, 32
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- bdnz 1b
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- isync
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-
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- mflr r16
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- bl dcache_disable
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- mtlr r16
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-
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- blr
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-
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-#if 0
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-#define GREEN_LIGHT 0x2B0D4046
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-#define RED_LIGHT 0x250D4046
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-#define LIB_CNT 0x4FFF
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-
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-/*
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- * Lib Light
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- */
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-
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- .globl liblight
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-liblight:
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- lis r3, CFG_IMMRBAR@h
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- ori r3, r3, CFG_IMMRBAR@l
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- li r4, 0x3002
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- mtmsr r4
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- xor r4, r4, r4
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- mtspr HID0, r4
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- mtspr HID2, r4
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- lis r4, 0xF8000000@h
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- ori r4, r4, 0xF8000000@l
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- stw r4, LBLAWBAR1(r3)
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- lis r4, 0x8000000E@h
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- ori r4, r4, 0x8000000E@l
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- stw r4, LBLAWAR1(r3)
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- lis r4, 0xF8000801@h
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- ori r4, r4, 0xF8000801@l
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- stw r4, BR1(r3)
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- lis r4, 0xFFFFE8f0@h
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- ori r4, r4, 0xFFFFE8f0@l
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- stw r4, OR1(r3)
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-
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- lis r4, 0xF8000000@h
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- ori r4, r4, 0xF8000000@l
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- lis r5, GREEN_LIGHT@h
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- ori r5, r5, GREEN_LIGHT@l
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- lis r6, RED_LIGHT@h
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- ori r6, r6, RED_LIGHT@l
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- lis r7, LIB_CNT@h
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- ori r7, r7, LIB_CNT@l
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-
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-1:
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- stw r5, 0(r4)
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- mtctr r7
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-2: bdnz 2b
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- stw r6, 0(r4)
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- mtctr r7
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-3: bdnz 3b
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- b 1b
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-
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-#endif
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Kumar Gala