ARM: OMAP4+: Move external phy initialisations to arch specific place.

The external phy is present in the case OMAP5 soc is currently
configured in emif-common.c. This results in having dummy structures
for those Socs which do not have a external phy. So by having a weak
function in emif-common and overriding it in OMAP5, avoids the use
of dummy structures.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

arch/arm/cpu/armv7/omap-common/emif-common.c

@@ -31,6 +31,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
 #include <asm/utils.h>
+#include <linux/compiler.h>
 
 void set_lpmode_selfrefresh(u32 base)
 {
@@ -140,9 +141,6 @@ static void do_lpddr2_init(u32 base, u32 cs)
 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-	u32 *ext_phy_ctrl_base = 0;
-	u32 *emif_ext_phy_ctrl_base = 0;
-	u32 i = 0;
 
 	/* Not NVM */
 	clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
@@ -160,29 +158,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
 	writel(regs->sdram_config_init, &emif->emif_sdram_config);
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 
-	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
-	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
-	if (omap_revision() >= OMAP5430_ES1_0) {
-		/* Configure external phy control timing registers */
-		for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
-			writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
-			/* Update shadow registers */
-			writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
-		}
-
-		/*
-		 * external phy 6-24 registers do not change with
-		 * ddr frequency
-		 */
-		for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
-			writel(ext_phy_ctrl_const_base[i],
-						emif_ext_phy_ctrl_base++);
-			/* Update shadow registers */
-			writel(ext_phy_ctrl_const_base[i],
-						emif_ext_phy_ctrl_base++);
-		}
-	}
+	do_ext_phy_settings(base, regs);
 
 	do_lpddr2_init(base, CS0);
 	if (regs->sdram_config & EMIF_REG_EBANK_MASK)
@@ -194,6 +170,10 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
 	/* Enable refresh now */
 	clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 
+	}
+
+__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
 }
 
 void emif_update_timings(u32 base, const struct emif_regs *regs)

arch/arm/cpu/armv7/omap4/sdram_elpida.c

@@ -91,7 +91,6 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
 };
 
 /* Dummy registers for OMAP44xx */
-const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
 const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
 
 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {

arch/arm/cpu/armv7/omap5/sdram.c

@@ -204,6 +204,37 @@ void emif_get_device_details(u32 emif_nr,
 
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	u32 i = 0;
+
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+	/*
+	 * external phy 6-24 registers do not change with
+	 * ddr frequency
+	 */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+		writel(ext_phy_ctrl_const_base[i],
+					emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ext_phy_ctrl_const_base[i],
+					emif_ext_phy_ctrl_base++);
+	}
+}
+
 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 	.max_freq	= 532000000,

arch/arm/include/asm/emif.h

@@ -1141,6 +1141,8 @@ void emif_get_device_timings(u32 emif_nr,
 		const struct lpddr2_device_timings **cs1_device_timings);
 #endif
 
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
+
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 extern u32 *const T_num;
 extern u32 *const T_den;