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@@ -0,0 +1,442 @@
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+/*
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+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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+ *
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+ * Loosely based on the old code and Linux's PXA MMC driver
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+#include <config.h>
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+#include <common.h>
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+#include <malloc.h>
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+
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+#include <mmc.h>
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+#include <asm/errno.h>
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+#include <asm/arch/hardware.h>
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+#include <asm/arch/regs-mmc.h>
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+#include <asm/io.h>
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+
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+/* PXAMMC Generic default config for various CPUs */
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+#if defined(CONFIG_PXA250)
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+#define PXAMMC_FIFO_SIZE 1
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+#define PXAMMC_MIN_SPEED 312500
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+#define PXAMMC_MAX_SPEED 20000000
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+#define PXAMMC_HOST_CAPS (0)
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+#elif defined(CONFIG_PXA27X)
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+#define PXAMMC_CRC_SKIP
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+#define PXAMMC_FIFO_SIZE 32
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+#define PXAMMC_MIN_SPEED 304000
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+#define PXAMMC_MAX_SPEED 19500000
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+#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT)
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+#elif defined(CONFIG_CPU_MONAHANS)
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+#define PXAMMC_FIFO_SIZE 32
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+#define PXAMMC_MIN_SPEED 304000
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+#define PXAMMC_MAX_SPEED 26000000
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+#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT | MMC_MODE_HS)
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+#else
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+#error "This CPU isn't supported by PXA MMC!"
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+#endif
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+
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+#define MMC_STAT_ERRORS \
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+ (MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN | \
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+ MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE | \
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+ MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR)
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+
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+/* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
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+#define PXA_MMC_TIMEOUT 100
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+
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+struct pxa_mmc_priv {
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+ struct pxa_mmc_regs *regs;
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+};
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+
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+/* Wait for bit to be set */
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+static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
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+{
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+ struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
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+ struct pxa_mmc_regs *regs = priv->regs;
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+ unsigned int timeout = PXA_MMC_TIMEOUT;
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+
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+ /* Wait for bit to be set */
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+ while (--timeout) {
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+ if (readl(®s->stat) & mask)
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+ break;
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+ udelay(10);
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+ }
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+
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+ if (!timeout)
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+ return -ETIMEDOUT;
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+
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+ return 0;
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+}
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+
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+static int pxa_mmc_stop_clock(struct mmc *mmc)
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+{
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+ struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
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+ struct pxa_mmc_regs *regs = priv->regs;
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+ unsigned int timeout = PXA_MMC_TIMEOUT;
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+
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+ /* If the clock aren't running, exit */
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+ if (!(readl(®s->stat) & MMC_STAT_CLK_EN))
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+ return 0;
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+
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+ /* Tell the controller to turn off the clock */
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+ writel(MMC_STRPCL_STOP_CLK, ®s->strpcl);
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+
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+ /* Wait until the clock are off */
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+ while (--timeout) {
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+ if (!(readl(®s->stat) & MMC_STAT_CLK_EN))
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+ break;
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+ udelay(10);
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+ }
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+
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+ /* The clock refused to stop, scream and die a painful death */
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+ if (!timeout)
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+ return -ETIMEDOUT;
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+
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+ /* The clock stopped correctly */
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+ return 0;
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+}
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+
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+static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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+ uint32_t cmdat)
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+{
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+ struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
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+ struct pxa_mmc_regs *regs = priv->regs;
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+ int ret;
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+
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+ /* The card can send a "busy" response */
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+ if (cmd->flags & MMC_RSP_BUSY)
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+ cmdat |= MMC_CMDAT_BUSY;
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+
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+ /* Inform the controller about response type */
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+ switch (cmd->resp_type) {
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+ case MMC_RSP_R1:
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+ case MMC_RSP_R1b:
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+ cmdat |= MMC_CMDAT_R1;
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+ break;
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+ case MMC_RSP_R2:
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+ cmdat |= MMC_CMDAT_R2;
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+ break;
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+ case MMC_RSP_R3:
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+ cmdat |= MMC_CMDAT_R3;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ /* Load command and it's arguments into the controller */
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+ writel(cmd->cmdidx, ®s->cmd);
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+ writel(cmd->cmdarg >> 16, ®s->argh);
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+ writel(cmd->cmdarg & 0xffff, ®s->argl);
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+ writel(cmdat, ®s->cmdat);
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+
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+ /* Start the controller clock and wait until they are started */
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+ writel(MMC_STRPCL_START_CLK, ®s->strpcl);
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+
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+ ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
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+ if (ret)
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+ return ret;
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+
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+ /* Correct and happy end */
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+ return 0;
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+}
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+
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+static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
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+{
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+ struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
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+ struct pxa_mmc_regs *regs = priv->regs;
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+ uint32_t a, b, c;
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+ int i;
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+ int stat;
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+
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+ /* Read the controller status */
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+ stat = readl(®s->stat);
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+
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+ /*
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+ * Linux says:
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+ * Did I mention this is Sick. We always need to
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+ * discard the upper 8 bits of the first 16-bit word.
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+ */
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+ a = readl(®s->res) & 0xffff;
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+ for (i = 0; i < 4; i++) {
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+ b = readl(®s->res) & 0xffff;
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+ c = readl(®s->res) & 0xffff;
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+ cmd->response[i] = (a << 24) | (b << 8) | (c >> 8);
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+ a = c;
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+ }
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+
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+ /* The command response didn't arrive */
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+ if (stat & MMC_STAT_TIME_OUT_RESPONSE)
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+ return -ETIMEDOUT;
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+ else if (stat & MMC_STAT_RES_CRC_ERROR && cmd->flags & MMC_RSP_CRC) {
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+#ifdef PXAMMC_CRC_SKIP
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+ if (cmd->flags & MMC_RSP_136 && cmd->response[0] & (1 << 31))
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+ printf("Ignoring CRC, this may be dangerous!\n");
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+ else
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+#endif
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+ return -EILSEQ;
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+ }
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+
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+ /* The command response was successfully read */
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+ return 0;
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+}
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+
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+static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
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+{
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+ struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
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+ struct pxa_mmc_regs *regs = priv->regs;
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+ uint32_t len;
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+ uint32_t *buf = (uint32_t *)data->dest;
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+ int size;
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+ int ret;
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+
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+ len = data->blocks * data->blocksize;
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+
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+ while (len) {
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+ /* The controller has data ready */
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+ if (readl(®s->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
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+ size = min(len, PXAMMC_FIFO_SIZE);
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+ len -= size;
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+ size /= 4;
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+
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+ /* Read data into the buffer */
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+ while (size--)
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+ *buf++ = readl(®s->rxfifo);
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+
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+ }
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+
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+ if (readl(®s->stat) & MMC_STAT_ERRORS)
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+ return -EIO;
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+ }
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+
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+ /* Wait for the transmission-done interrupt */
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+ ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
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+{
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+ struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
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+ struct pxa_mmc_regs *regs = priv->regs;
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+ uint32_t len;
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+ uint32_t *buf = (uint32_t *)data->src;
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+ int size;
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+ int ret;
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+
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+ len = data->blocks * data->blocksize;
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+
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+ while (len) {
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+ /* The controller is ready to receive data */
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+ if (readl(®s->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
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+ size = min(len, PXAMMC_FIFO_SIZE);
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+ len -= size;
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+ size /= 4;
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+
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+ while (size--)
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+ writel(*buf++, ®s->txfifo);
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+
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+ if (min(len, PXAMMC_FIFO_SIZE) < 32)
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+ writel(MMC_PRTBUF_BUF_PART_FULL, ®s->prtbuf);
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+ }
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+
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+ if (readl(®s->stat) & MMC_STAT_ERRORS)
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+ return -EIO;
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+ }
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+
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+ /* Wait for the transmission-done interrupt */
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+ ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
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+ if (ret)
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+ return ret;
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+
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+ /* Wait until the data are really written to the card */
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+ ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
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+ struct mmc_data *data)
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+{
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+ struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
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+ struct pxa_mmc_regs *regs = priv->regs;
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+ uint32_t cmdat = 0;
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+ int ret;
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+
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+ /* Stop the controller */
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+ ret = pxa_mmc_stop_clock(mmc);
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+ if (ret)
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+ return ret;
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+
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+ /* If we're doing data transfer, configure the controller accordingly */
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+ if (data) {
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+ writel(data->blocks, ®s->nob);
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+ writel(data->blocksize, ®s->blklen);
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+ /* This delay can be optimized, but stick with max value */
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+ writel(0xffff, ®s->rdto);
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+ cmdat |= MMC_CMDAT_DATA_EN;
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+ if (data->flags & MMC_DATA_WRITE)
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+ cmdat |= MMC_CMDAT_WRITE;
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+ }
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+
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+ /* Run in 4bit mode if the card can do it */
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+ if (mmc->bus_width == 4)
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+ cmdat |= MMC_CMDAT_SD_4DAT;
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+
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+ /* Execute the command */
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+ ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
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+ if (ret)
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+ return ret;
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+
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+ /* Wait until the command completes */
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+ ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
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+ if (ret)
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+ return ret;
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+
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+ /* Read back the result */
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+ ret = pxa_mmc_cmd_done(mmc, cmd);
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+ if (ret)
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+ return ret;
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+
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+ /* In case there was a data transfer scheduled, do it */
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+ if (data) {
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+ if (data->flags & MMC_DATA_WRITE)
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+ pxa_mmc_do_write_xfer(mmc, data);
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+ else
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+ pxa_mmc_do_read_xfer(mmc, data);
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+ }
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+
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+ return 0;
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+}
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+
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+static void pxa_mmc_set_ios(struct mmc *mmc)
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+{
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+ struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
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+ struct pxa_mmc_regs *regs = priv->regs;
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+ uint32_t tmp;
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+ uint32_t pxa_mmc_clock;
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+
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+ if (!mmc->clock) {
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+ pxa_mmc_stop_clock(mmc);
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+ return;
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+ }
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+
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+ /* PXA3xx can do 26MHz with special settings. */
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+ if (mmc->clock == 26000000) {
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+ writel(0x7, ®s->clkrt);
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+ return;
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+ }
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+
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+ /* Set clock to the card the usual way. */
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+ pxa_mmc_clock = 0;
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+ tmp = mmc->f_max / mmc->clock;
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+ tmp += tmp % 2;
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+
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+ while (tmp > 1) {
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+ pxa_mmc_clock++;
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+ tmp >>= 1;
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+ }
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+
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+ writel(pxa_mmc_clock, ®s->clkrt);
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+}
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+
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+static int pxa_mmc_init(struct mmc *mmc)
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+{
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+ struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
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+ struct pxa_mmc_regs *regs = priv->regs;
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+
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+ /* Make sure the clock are stopped */
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+ pxa_mmc_stop_clock(mmc);
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+
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+ /* Turn off SPI mode */
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+ writel(0, ®s->spi);
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+
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+ /* Set up maximum timeout to wait for command response */
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+ writel(MMC_RES_TO_MAX_MASK, ®s->resto);
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+
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+ /* Mask all interrupts */
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+ writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
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+ ®s->i_mask);
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+ return 0;
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+}
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+
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+int pxa_mmc_register(int card_index)
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+{
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+ struct mmc *mmc;
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+ struct pxa_mmc_priv *priv;
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+ uint32_t reg;
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+ int ret = -ENOMEM;
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+
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+ mmc = malloc(sizeof(struct mmc));
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+ if (!mmc)
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+ goto err0;
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+
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+ priv = malloc(sizeof(struct pxa_mmc_priv));
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+ if (!priv)
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+ goto err1;
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+
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+ switch (card_index) {
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+ case 0:
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+ priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
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+ break;
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+ case 1:
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+ priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
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+ break;
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+ default:
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+ printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
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+ card_index);
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+ goto err2;
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+ }
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+
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+ mmc->priv = priv;
|
|
|
+
|
|
|
+ sprintf(mmc->name, "PXA MMC");
|
|
|
+ mmc->send_cmd = pxa_mmc_request;
|
|
|
+ mmc->set_ios = pxa_mmc_set_ios;
|
|
|
+ mmc->init = pxa_mmc_init;
|
|
|
+
|
|
|
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
+ mmc->f_max = PXAMMC_MAX_SPEED;
|
|
|
+ mmc->f_min = PXAMMC_MIN_SPEED;
|
|
|
+ mmc->host_caps = PXAMMC_HOST_CAPS;
|
|
|
+
|
|
|
+ mmc->b_max = 0;
|
|
|
+
|
|
|
+#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */
|
|
|
+ reg = readl(CKEN);
|
|
|
+ reg |= CKEN12_MMC;
|
|
|
+ writel(reg, CKEN);
|
|
|
+#else /* PXA3xx */
|
|
|
+ reg = readl(CKENA);
|
|
|
+ reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
|
|
|
+ writel(reg, CKENA);
|
|
|
+#endif
|
|
|
+
|
|
|
+ mmc_register(mmc);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+err2:
|
|
|
+ free(priv);
|
|
|
+err1:
|
|
|
+ free(mmc);
|
|
|
+err0:
|
|
|
+ return ret;
|
|
|
+}
|
Wolfgang Denk