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@@ -22,8 +22,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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volatile ccsr_ddr_t *ddr;
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volatile ccsr_ddr_t *ddr;
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u32 temp_sdram_cfg;
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u32 temp_sdram_cfg;
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u32 total_gb_size_per_controller;
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u32 total_gb_size_per_controller;
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- int timeout, timeout_save;
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+ int timeout;
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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+ int timeout_save;
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volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
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volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
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unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
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unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
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int csn = -1;
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int csn = -1;
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@@ -305,7 +306,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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>> SDRAM_CFG_DBW_SHIFT);
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>> SDRAM_CFG_DBW_SHIFT);
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timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
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timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
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(get_ddr_freq(0) >> 20)) << 1;
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(get_ddr_freq(0) >> 20)) << 1;
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+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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timeout_save = timeout;
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timeout_save = timeout;
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+#endif
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total_gb_size_per_controller >>= 4; /* shift down to gb size */
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total_gb_size_per_controller >>= 4; /* shift down to gb size */
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debug("total %d GB\n", total_gb_size_per_controller);
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debug("total %d GB\n", total_gb_size_per_controller);
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debug("Need to wait up to %d * 10ms\n", timeout);
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debug("Need to wait up to %d * 10ms\n", timeout);
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