Merge branch 'master' of /home/git/u-boot

.gitignore

@@ -10,6 +10,7 @@
 *.orig
 *.a
 *.o
+*~
 
 #
 # Top-level generic files
@@ -17,9 +18,13 @@
 
 /System.map
 /u-boot
+/u-boot.hex
 /u-boot.map
 /u-boot.bin
 /u-boot.srec
+/u-boot.ldr
+/u-boot.ldr.hex
+/u-boot.ldr.srec
 
 #
 # Generated files

CHANGELOG

@@ -1,3 +1,1262 @@
+commit b738654d3c84a30f2bfd9a8d7652ff20807c890c
+Author: Mike Nuss <mike@terascala.com>
+Date:	Wed Feb 6 11:10:11 2008 -0500
+
+    PPC440EPx: Optionally enable second I2C bus
+
+    The option CONFIG_I2C_MULTI_BUS does not have any effect on Sequoia, the
+    PPC440EPx reference platform, because IIC1 is never enabled. Add Sequoia board
+    code to turn on IIC1 if CONFIG_I2C_MULTI_BUS is selected.
+
+    Signed-off-by: Mike Nuss <mike@terascala.com>
+    Cc: Stefan Roese <sr@denx.de>
+
+commit ef5b4f221c22d05770878513951745f236b5b43f
+Author: Niklaus Giger <niklaus.giger@netstal.com>
+Date:	Tue Feb 5 10:26:44 2008 +0100
+
+    ppc4xx: HCU4/5. Cleanup configs
+
+    - hcu4.h: Removed define of CONFIG_PPC405GPr
+    - Corrected phy addresses
+    - Fix boot variables
+    - Respect line length of 80 chars
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 74973126d1be63ac75bdc192f46234dca3a7c421
+Author: Niklaus Giger <niklaus.giger@netstal.com>
+Date:	Tue Feb 5 11:31:28 2008 +0100
+
+    ppc4xx: HCU4/5. Cleanups
+
+    - Fix some coding style violations.
+    - Use in/out_u16/32 where appropriate.
+    - Use register names from ppc405.h.
+    - Fix trace useage for Lauterbach.
+    - Remove obsolete generation HCU2.
+    - Renamed fixed_hcu4_sdram to init_ppc405_sdram.
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 8cc10d06b833ed917a19ad358c8ebbed8bc19555
+Author: Niklaus Giger <niklaus.giger@netstal.com>
+Date:	Tue Feb 5 10:26:41 2008 +0100
+
+    ppc4xx: PPC405GPr fix missing register definitions
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 214398d9cb22268d9d4f7563359edca0f78297a2
+Author: Larry Johnson <lrj@acm.org>
+Date:	Fri Jan 18 21:49:05 2008 -0500
+
+    ppc4xx: Beautify configuration files for Sequoia and Korat boards
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 30c6a241e88499f536e86d325759e29ba00ff67f
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Fri Feb 15 20:09:01 2008 +0100
+
+    Wipe out assembler warnings while compiling x86 biosemu
+
+    This patch tries to get rid of some assembler warnings about
+    changed .got2 section type while compiling x86 bios emulator
+    code.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 67a4389e39ad853d65b72e2b7cad15c7e8291147
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Feb 15 00:57:09 2008 +0100
+
+    Prepare v1.3.2-rc1 release candidate
+
+commit f33e9653c9c09868995d788511d573771c209fe5
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Fri Feb 15 00:13:20 2008 +0100
+
+    Fix compile warning on lib_ppc/board.c
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit e5c6f9f8bec4dff9603419161e3a15cc8ad5d5f4
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Thu Feb 14 18:22:04 2008 +0100
+
+    Add Radeon Mobility 9200 pci device id to the radeon driver
+
+    This patch extends PCI device id table of the
+    radeon driver so that the driver will also support
+    Radeon Mobility 9200 (M9+) based boards.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 1b8607e1f7143548c6062c28371449ec69588c00
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Thu Feb 14 18:19:50 2008 +0100
+
+    Extend ATI Radeon driver to support more video modes
+
+    Adds ATI Radeon 9200 support for 1280x1024, 1024x768,
+    800x600, 640x480 at 24, 16 and 8 bpp.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 4124382de029d361162a4b8cecc773eb8f26e2a8
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Feb 10 17:05:20 2008 +0100
+
+    xsengine: fix typo and few coding style
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6f4abee789b6d9be3ec4b97ad48f509355559e9e
+Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Date:	Fri Feb 8 21:25:58 2008 +0100
+
+    Fix wrong memory limit calculation in memory-test
+
+    If the length of the memory address range passed to the "mtest" command is
+    not of the form 2^x - 1, not all address lines are tested. This bug is
+    inherited from the original software at
+    http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C. Fix
+    this.
+
+    Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+commit 7e30f5eac7f07082a7ca77b7d91b944a8d0af6db
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Feb 15 00:11:39 2008 +0100
+
+    Coding STyle cleanup.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f6921e3dc331293c873ec4d109fd5517a42a90b3
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Tue Feb 5 13:30:43 2008 +0900
+
+    sh: Fix register address of SH7722
+
+    The address of SH7722 is wrong by old document.
+    This patch fixes this problem.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 0ec7a061fb1c277f6afd73d61dd71bd21e7ef7b2
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 17:44:23 2008 -0500
+
+    only update version header as needed
+
+    Constantly rebuilding the version header will force useless relinking, so we
+    simply need to compare the new header with the existing one before updating
+    it.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 208447f8e953f347425eb92c8e28d59e6d911363
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Jan 28 05:56:19 2008 -0500
+
+    Do not specify a CROSS_COMPILE default when executing size
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 1f780aa6f17a5d79791d69ec1d2f66d76ac45d8e
+Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Date:	Wed Feb 13 11:19:19 2008 +0100
+
+    Fix return value of mtest when CFG_ALT_MEMTEST set
+
+    Fix a missing return statement from a non-void function.
+
+    Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+commit 943afa229cf5bf70ef917c7eb6bd0db59a1ba602
+Author: Timur Tabi <timur@freescale.com>
+Date:	Wed Jan 9 14:35:26 2008 -0600
+
+    85xx, 86xx: Determine I2C clock frequencies and store in global_data
+
+    Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx.
+
+    Update the get_clocks() function in 85xx and 86xx to determine the I2C
+    clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit b931b3a9c3bdfaaeaa71e57a6026eec726005b08
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu Feb 14 23:18:01 2008 +0100
+
+    TQM834x: clean up configuration
+
+    Get board name consistent with Linux and elsewhere;
+    get rid of local network definitions etc.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 38cc09c55b1d7f233789052c6fc462e5377669a9
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Thu Feb 14 08:02:12 2008 +0100
+
+    TFTP: fix search of ':' in BootFile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 0bc9efada170096c6b273f19165e32936d330d80
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu Feb 14 22:46:55 2008 +0100
+
+    Coding style cleanup; update CHANGELOG.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e7670f6c1e52ae6d2a43ff75a8bcfa7a5c86e47b
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu Feb 14 22:43:22 2008 +0100
+
+    PPC: Use r2 instead of r29 as global data pointer
+
+    R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc
+    will refuse to use load/store multiple insns; instead, it issues a
+    list of simple load/store instructions upon function entry and exit,
+    resulting in bigger code size, which in turn makes the build for a
+    few boards fail.
+
+    Use r2 instead.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3c234efa693bc59906c2be55c7918ecbb55392ea
+Author: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
+Date:	Wed Jan 30 09:08:49 2008 +0100
+
+    ARM: make the machid configurable via the environment
+
+    If the variable "machid" exists, let do_bootm_linux use that instead
+    of bd->bi_arch_number.
+
+    Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
+
+commit dd24058407c5add45cc60aec6c757ddc1a17e1b0
+Author: Vlad Lungu <vlad@comsys.ro>
+Date:	Wed Jan 23 16:34:46 2008 +0200
+
+    Use #ifdef CONFIG_FSLDMAFEC
+
+    MCD_tasks.c lacks [subject] so compilation of mips targets (and more, probably)
+    fails
+
+    Signed-off-by: Vlad Lungu <vlad@comsys.ro>
+
+commit 26c7bab81e08dc7bd696c48f753428a829629bd8
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date:	Sat Jan 19 10:25:59 2008 +0900
+
+    common/miiphyutil.c: Cleanup MII_DEBUG and debug()
+
+    Current MII_DEBUG is confusing in two ways. One is useless define-then-
+    undef at the top of the file. The other is there is only one debug() in
+    this file, and that doesn't seem worthwhile to bother having MII_DEBUG.
+    While there are many useful printf()/puts() debug codes, but they are for
+    DEBUG, not for MII_DEBUG.
+
+    This patch tries to put them all together into MII_DEBUG and debug().
+
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 751b9b5189f3274b03c809172631316d6b002c82
+Author: Kyungmin Park <kmpark@infradead.org>
+Date:	Thu Jan 17 16:43:25 2008 +0900
+
+    OneNAND Initial Program Loader (IPL) support
+
+    This patch enables the OneNAND boot within U-Boot.
+    Before this work, we used another OneNAND IPL called X-Loader based
+    on open source. With this work, we can build the oneboot.bin image
+    without other program.
+
+    The build sequence is simple.
+    First, it compiles the u-boot.bin
+    Second, it compiles OneNAND IPL
+    Finally, it becomes the oneboot.bin from OneNAND IPL and u-boot.bin
+    The mechanism is similar with NAND boot except it boots from itself.
+
+    Another thing is that you can only use the OneNAND IPL only to work
+    other bootloader such as RedBoot and so on.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 21f6f9636f0e978397548751347425fbf8d42bb3
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Wed Jan 16 13:06:59 2008 -0600
+
+    Fix CONFIG_MMC usage in fat code
+
+    A #if statement in fat.c depended on CONFIG_MMC, instead of
+    defined(CONFIG_MMC).  This meant CONFIG_MMC needed to be defined
+    as "1" rather than just defined.  Now it's better.
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit f57d7d364ce189e39b0a64338d2f8012c074a2bd
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date:	Tue Jan 15 12:52:31 2008 +0100
+
+    ppc: Refactor cache routines, so there is only one common set.
+
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 3f2ac8f928c76cbd2374437b2d079f8b4324aaba
+Author: Jon Loeliger <jdl@jdl.com>
+Date:	Wed Jan 23 15:55:02 2008 -0600
+
+    86xx: Fix compilation warning in sys_eprom.c
+
+    sys_eeprom.c:82:9: warning: unknown escape sequence '\/'
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 65230107025733e89e28fd5e5cfd916d4953c28a
+Author: Haavard Skinnemoen <hskinnemoen at>
+Date:	Fri Feb 22 11:40:50 2008 +0000
+
+    Move AT91RM9200DK board support under board/atmel
+
+    We already have a vendor subdir for Atmel, so we should use it.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen <at> atmel.com>
+
+commit 6d0943a6be99977d6d853d51749e9963d68eb192
+Author: Andreas Engel <andreas.engel@ericsson.com>
+Date:	Mon Jan 14 09:06:52 2008 +0000
+
+    ARM: cleanup duplicated exception handlingcode
+
+    Move duplicated exception handling code into lib_arm.
+
+    Signed-off-by: Andreas Engel <andreas.engel@ericsson.com>
+
+commit ea8d989f4ef8203e1c0291e62435a8c62e3cfb29
+Author: Timo Tuunainen <timo.tuunainen@sysart.fi>
+Date:	Fri Feb 1 10:09:03 2008 +0000
+
+    Support for Artila M-501 starter kit
+
+    Kimmo Leppala / Sysart and
+    Timo Tuunainen / Sysart
+
+commit 9604b6e53ddae4fe00a488cbcd6b0e6cb344bccc
+Author: Stelian Pop <stelian@popies.net>
+Date:	Mon Feb 11 10:50:19 2008 +0000
+
+    AT91CAP9 support
+
+    ---------------------------------
+
+    read_dataflash() takes a signed char pointer as a parameter. Silence a
+    few warnings dues to incorrect parameter types in env_dataflash.c.
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit 64e8a06af68cda174a8a06d0a61fce5e5bb189d7
+Author: Stelian Pop <stelian@popies.net>
+Date:	Thu Feb 7 09:42:57 2008 +0000
+
+    AT91CAP9 support : move board files to Atmel vendor directory.
+
+    AT91CAP9 support : move at91cap9adk board files to Atmel vendor directory.
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit 7263ef191b87da94768f762c7093bedeb70db98f
+Author: Stelian Pop <stelian at>
+Date:	Thu Jan 3 21:15:56 2008 +0000
+
+    AT91CAP9 support : MACB changes
+
+    Signed-off-by: Stelian Pop <stelian <at> popies.net>
+    Acked-by: Haavard Skinnemoen <hskinnemoen <at> atmel.com>
+
+commit 6afcabf11d7321850f4feaadfee841488ace54c5
+Author: Stelian Pop <stelian@popies.net>
+Date:	Thu Feb 7 16:37:54 2008 +0000
+
+    AT91CAP9 support : board/ files
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit fefb6c10928caa9e71335cad64dcb65c83fce8ab
+Author: Stelian Pop <stelian at>
+Date:	Wed Jan 30 21:15:54 2008 +0000
+
+    AT91CAP9 support : cpu/ files
+
+    Signed-off-by: Stelian Pop <stelian <at> popies.net>
+
+commit fa506a926cec348805143576c941f8e61b333cc0
+Author: Stelian Pop <stelian@popies.net>
+Date:	Thu Jan 31 21:15:53 2008 +0000
+
+    AT91CAP9 support : include/ files
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit 20b197c6f2799af399a68f96a1aff543a75621b8
+Author: Stelian Pop <stelian@popies.net>
+Date:	Sun Jan 20 19:49:21 2008 +0000
+
+    AT91CAP9 support : build integration
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit d49fe4bed5b69ec910909d1bd62da23ecd8801fd
+Author: Stelian Pop <stelian@popies.net>
+Date:	Sun Jan 20 21:07:00 2008 +0000
+
+    Improve DataFlash CS definition.
+
+    Use a structure instead of the error prone unnamed array to
+    define the possible dataflash banks.
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit a6cdd21b56014208706238712a853a9e9a0a2290
+Author: Stelian Pop <stelian@popies.net>
+Date:	Sat Jan 19 21:09:35 2008 +0000
+
+    Fix arm926ejs compile when SKIP_LOWLEVEL_INIT is on
+
+    Fix arm926ejs compile when SKIP_LOWLEVEL_INIT is on.
+
+    cpu/arm926ejs/start.o: In function `cpu_init_crit':
+    .../cpu/arm926ejs/start.S:227: undefined reference to `lowlevel_init'
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit ea686f52e45b3df2938866d3f5a98bb2556dfe2b
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Fri Feb 1 16:50:24 2008 +0000
+
+    Fix timer overflow in DaVinci
+    Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
+
+commit f4e7cbfcb0fcbc325a2bcfea7e00e3dd37f93846
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Fri Feb 1 16:49:08 2008 +0000
+
+    Update board NetStar
+    Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+
+commit b7f6193e76651e1fd606e46eb11915b53cb6618b
+Author: Niklaus Giger <niklaus.giger@netstal.com>
+Date:	Tue Feb 5 10:26:42 2008 +0100
+
+    ppc4xx: HCU4/5. Fix make O=../xx
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 29e3500cbc43c89eff6e720ca83e375deeecd9b3
+Author: Larry Johnson <lrj@acm.org>
+Date:	Tue Jan 22 08:51:59 2008 -0500
+
+    ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit fe891ecf4d187e9d11dde869ed4623af52b54451
+Author: Hiroshi Ito <ito@mlb.co.jp>
+Date:	Thu Jan 31 18:35:04 2008 +0900
+
+    NFS Timeout with large files.
+
+    Retry to send NFS packet before reaching timeout.
+
+    Signed-off-by: Hiroshi Ito <ito@mlb.co.jp>
+
+commit 88f72527f5b89c0905ad5c36cc2ef8d29dd6bbf0
+Author: Johannes Stezenbach <js@sig21.net>
+Date:	Tue Jan 29 00:11:25 2008 +0100
+
+    Add dependencies to avoid race conditions with parallel make.
+
+    Signed-off-by: Johannes Stezenbach <js@sig21.net>
+
+commit 6d1b6f9f89c815eaca44acff8e73ece7181f61b6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Jan 28 05:46:01 2008 -0500
+
+    Mark board_init_[fr] as noreturn
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 161b2af4d7b48fd602ce333c355a4df0337892bb
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Jan 28 05:28:50 2008 -0500
+
+    Only use TEXT_BASE if defined by the board
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 1b769881750030f10743808b9d6013e11f559350
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Jan 25 07:54:47 2008 +0100
+
+    Fix remaining CONFIG_COMMANDS
+
+    update comments
+    Fix coding style
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 0c9d42e6b0b83d507335a291e3ea99240038f4b9
+Author: Niklaus Giger <niklaus.giger@netstal.com>
+Date:	Mon Jan 21 16:46:00 2008 +0100
+
+    Add *~ to .gitignore
+
+    One should never add a backup file ending in with ~ to the git repository.
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 3cfb0c51b2bb5ede54eca85ace5b1ba12be314b0
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Jan 17 00:02:10 2008 -0600
+
+    Remove duplicate defines for ARRAY_SIZE
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit c77ce474b1c57b13e9d36d9830f147966c143694
+Author: Stelian Pop <stelian@popies.net>
+Date:	Mon Jan 14 22:08:14 2008 +0100
+
+    Fix incorrect address test in AT91F_DataflashSelect().
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit d9ad115bbf7bb0842de7dbd2502b7e430f83cc3d
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Feb 13 15:09:58 2008 -0600
+
+    Fix building of fdt_support.c if DEBUG set
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit ccd6e1464e5396bc1a9aebf7077ddf4342eafe03
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Feb 12 14:53:28 2008 -0600
+
+    Add CFG_MPC86xx_DDR_ADDR and CFG_MPC86xx_DDR2_ADDR symbols
+
+    These replace direct structure references for IMMR sections.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit c62776be8dca4097ca03d4f9415f08d4887b45d0
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Feb 12 00:45:06 2008 +0100
+
+    Get rid of "#undef DEBUG" from board config files.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 73bf1e2de7862bcdbd5a9f993b3e84b67c8ea9c8
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Jan 15 17:09:41 2008 -0600
+
+    Remove #undef DEBUG from MPC83xx board header files
+
+    Remove the "#undef DEBUG" line from all Freescale 83xx board header files.
+    The inclusion of this line makes it impossible to enable debug code in
+    other source files, because "#define DEBUG" typically needs to be defined
+    before any header files are included.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 69018ce2e086e9caf35b914d675b82bc4888f077
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Jan 17 08:25:45 2008 -0600
+
+    QE: Move FDT support into a common file
+
+    Move the flat device tree setup for QE related devices into
+    a common file shared between 83xx & 85xx platforms that have QE's.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 37e3c62fa07a823e7569c872e3a9395d227ed8e3
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Mon Jan 28 10:15:02 2008 +0100
+
+    ADS5121e: DDR2 init/timing update.
+
+    Signed-off-by: John Rigby <jrigby@freescale.com>
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit ac9152830d7fdebace8a260b7737ef2870c21ca0
+Author: John Rigby <jrigby@freescale.com>
+Date:	Wed Jan 30 13:36:57 2008 -0700
+
+    Device tree updates
+
+    Changes to match 5121 device tree going mainline in 2.6.25.
+
+    Change OF_SOC from "soc5121" to plain "soc".
+    Remove unneeded "ref-frequency" fixups.
+    Remove "address" enetaddr fixup.
+
+    Add bus-frequency fixup for old OF_SOC so old
+    kernels with old device trees will work with new
+    u-boot with 66MHz IPS clock
+
+    Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit de55d18df3ff2ea614624e74793de7c43520e0e7
+Author: John Rigby <jrigby@freescale.com>
+Date:	Wed Jan 30 13:36:56 2008 -0700
+
+    Change IPS freq to 66MHz
+
+    Recommended frequency is 66MHz
+    Change divider from 4 to 3.
+
+    Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit cd9cb62f9d8b78d6c3af5d1e9b5a3d68a3d73974
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Jan 14 22:38:55 2008 +0100
+
+    xsengine: rename board_post_init to board_late_init
+
+    missing migration from "Cleanup of some init functions"
+    in c837dcb1a316745092567bfe4fb266d0941884ff
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8dafa87476b0d7170e219c2f5e3842c833a91807
+Author: Larry Johnson <lrj@acm.org>
+Date:	Sat Jan 12 23:35:33 2008 -0500
+
+    Add attribute POST_PREREL to ECC memory POST
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit ed2cf548cac80cd3cf8154dcfe7b2685bef45938
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Jan 17 08:25:45 2008 -0600
+
+    QE: Move FDT support into a common file
+
+    Move the flat device tree setup for QE related devices into
+    a common file shared between 83xx & 85xx platforms that have QE's.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d38da537943cd36356b9d3d9d9b60533554b81d8
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Wed Jan 23 17:20:14 2008 +0100
+
+    AVR32: Make SDRAM refresh rate configurable
+
+    The existing code assumes the SDRAM row refresh period should always
+    be 15.6 us. This is not always true, and indeed on the ATNGW100, the
+    refresh rate should really be 7.81 us.
+
+    Add a refresh_period member to struct sdram_info and initialize it
+    properly for both ATSTK1000 and ATNGW100. Out-of-tree boards will
+    panic() until the refresh_period member is updated properly.
+
+    Big thanks to Gerhard Berghofer for pointing out this issue.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 61151cccb660cdb06a07fb283de6089913d7bde0
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Apr 19 10:10:11 2007 +0200
+
+    ATSTK1000: Fix potential flash programming bug
+
+    The (now obsolete) atngw100 flash programming code was having problems
+    programming the onboard at49bv642 chip. The atstk1000 flash
+    programming code may have the same bug, so import fix for this problem
+    from the AVR32 Linux BSP.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit b2e1d5b64469f10dfcce27f7b0afd935684a8e11
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Nov 22 17:04:13 2007 +0100
+
+    ATSTK1004: Fix comment about default load address
+
+    The default load address is SDRAM + 2MB, not SDRAM + 4MB. The latter
+    wouldn't have worked anyway since the board can only access 4MB of
+    SDRAM.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 8269ab53608d8db2aa06969c337ab0b0518211e5
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Nov 22 17:01:24 2007 +0100
+
+    ATSTK1002: Use SDRAM + 4MB as default load address
+
+    Many people run into problems when they compile a big kernel and load
+    the uImage at the default SDRAM + 2MB address as the kernel will
+    overwrite the uImage as it is being unpacked. Increase the default
+    load address so that we can load a 4MB kernel image without any
+    problems.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 2bcacc2d841b77f3d2d3910db722003742727e9f
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Nov 22 16:51:39 2007 +0100
+
+    ATNGW100: Fix default mtest range
+
+    Let mtest cover the whole SDRAM except the last megabyte, which is
+    where u-boot lives.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 9856a6b3104e0bc210b0868dfe691c52bf03c227
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Tue Jan 22 15:31:56 2008 +0900
+
+    sh: Fix register address of SH7722.
+
+    The address of SH7722 is wrong by old document.
+    This patch fixes this problem.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 30942b18b66f35f2ceedab39af10e9eccaa943cc
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:57 2008 -0500
+
+    new command for displaying strings at specified memory locations
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit b58d8b48e25b0c866d167cc577f118f528cd9e0a
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:57 2008 -0500
+
+    rewrite/cleanup Blackfin RTC driver
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 94a91e248b71c3ff951fc27cff6909e82ca37d15
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:57 2008 -0500
+
+    generate u-boot.ldr for Blackfin targets
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit b779f7a59530436040f157f7841db7ab796542df
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:57 2008 -0500
+
+    scrub unused symbols
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit cc2977acc3bbbb7850f16645dd1081f95335868d
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:57 2008 -0500
+
+    move Blackfin cpu object list to respective cpu directories
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit d0b01a246d0a351bc7dce1d0c9cf6aebdf6d7505
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:57 2008 -0500
+
+    interface to Blackfin on-chip One-Time-Programmable memory
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 4c727c77e43872d3a1d1f76a949fcb3f26a38788
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:56 2008 -0500
+
+    add support for memory commands with Blackfin L1 instruction memory
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 6b9097e5e7490aa7b828c6f1a1c7a0e875df8464
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:56 2008 -0500
+
+    use C code rather than inline assembly
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 97c26e006d2fa6d4e1560933ee6f385d8b8908b9
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:56 2008 -0500
+
+    add Blackfin-specific reginfo command
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 0858b835e7ea501ea084d34cef75932f098342bb
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:55 2008 -0500
+
+    add support for Blackfin symbol prefixes to examples
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 8dc48d71a4be753ea9f84956cd33600de35fad04
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:55 2008 -0500
+
+    add Blackfin-specific bdinfo command
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 0003613e3c7df3b84b2cb92e797d77f46f15a43a
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:55 2008 -0500
+
+    move -ffixed-P5 to blackfin_config.mk and drop unused -D__BLACKFIN__
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 60fa72d65610c7ef33e1d6db858979d05ff0df58
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:55 2008 -0500
+
+    unify the Blackfin board targets
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit d4d7730853e5d675f76ec666807da3028c91d592
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:55 2008 -0500
+
+    punt Blackfin VDSP headers and import sanitized/auto-generated ones
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 6cfcce67671a3425229d66203386fa3cbd0cc3bd
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:54 2008 -0500
+
+    always pull in asm/blackfin.h for Blackfin ports
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit bf53974c2ddae678d7660f2b5ccfeb0732b6f5dc
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:54 2008 -0500
+
+    add missing __raw versions of Blackfin read/write io functions
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 24e02d0fd3acc50e73e1a3cdd567f0a77946f15d
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:54 2008 -0500
+
+    add the default Blackfin logo used by Blackfin boards with splash screens
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 4c58eb5552220e425c8af6ac8d2839244a2f57b1
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:54 2008 -0500
+
+    add some more Blackfin docs
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 32a9f5f2160a034ea87ea651b233ef7c635e55cf
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:54 2008 -0500
+
+    make smc91111_eeprom managment simpler by depending on the board configuration file rather than a hardcoded list of boards
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 4087bc88cebec75c432a7fe9f6afb545b0919831
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:54 2008 -0500
+
+    fix building on Blackfin as the assembler supports the .set syntax, not the = syntax, for assigning symbols
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit b45264ee85cbd92020640a32e02fb434fd557108
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Feb 4 19:26:53 2008 -0500
+
+    add gitignores for Blackfin pieces
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit a93907c43f847f076dd0e34ee3b69b5e8e6d0d29
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Jan 18 01:14:03 2008 +0100
+
+    TFTP: add host ip addr support
+
+    allow to use a different server as set in serverip
+    add CONFIG_TFTP_FILE_NAME_MAX_LEN to configure the file name length
+    if not defined the max length will be at 128
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit e56b4b494cd92def577969f9678395aa22d34c9f
+Author: Timur Tabi <timur@freescale.com>
+Date:	Wed Jan 9 14:35:26 2008 -0600
+
+    85xx,86xx: Determine I2C clock frequencies and store in global_data
+
+    Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx.
+
+    Update the get_clocks() function in 85xx and 86xx to determine the I2C
+    clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 7ec8bb15ee368ea54d48d64867767a704d9ab4c2
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu Dec 27 10:56:54 2007 +0100
+
+    OMAP5912: fix FIFO handling in UART driver
+
+    According to the OMAP5912 Serial Interfaces Reference Guide (see
+    http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the
+    FIFO_EN enable bit in the FIFO Control Register (FCR) can only be
+    changed when the baud clock is not running, i. e. when both DLL and
+    DLH are set to 0.
+
+    Thus make sure that DLL and DLH are 0 when writing the FCR.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 16158778b5f52f201e95ded2d2d9084b0ed5670d
+Author: Harald Welte <laforge@openmoko.org>
+Date:	Wed Dec 19 15:10:52 2007 +0100
+
+    ARM: S3C24x0 SoC NAND controller support
+
+    This patch adds NAND support to the S3C24x0 SoC code in u-boot
+
+    Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit a7c185ed3d9f8ebd85cfc286e1ffee72e4803163
+Author: Harald Welte <laforge@openmoko.org>
+Date:	Wed Dec 19 14:24:40 2007 +0100
+
+    ARM: s3c24xx: Multiple serial port support
+
+    This patch adds support for CONFIG_SERIAL_MULTI on s3c24x0 CPU's
+
+    Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit a25f72f1f73a11de68251fb88c89991e202e68fa
+Author: Harald Welte <laforge@openmoko.org>
+Date:	Wed Dec 19 14:16:57 2007 +0100
+
+    ARM: arm920t: Allow use of 'gd' pointer from IRQ
+
+    This patch allows us to use the 'gd' pointer (and thus environment
+    and everything else associated with it) from interrupt context on
+    arm920t.
+
+    Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit be19bd5cd0f454b63298844a0b5377e029b2caad
+Author: Harald Welte <laforge@openmoko.org>
+Date:	Wed Dec 19 14:19:38 2007 +0100
+
+    ARM: arm920/s3c24xx: IRQ demulitplexer callback
+
+    This patch adds a IRQ demultiplexer callback to the arm920 cpu core code,
+    plus a stub implementation of it for the S3C2410.
+
+    The purpose is to allow arm920t implementations such as the s3c24x0 to
+    implement interrupt handlers in u-boot without having to touch core
+    arm920t code.
+
+    Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit a41dbbd98d201d8aea31b5d21df4742c20cd7eda
+Author: Hebbar <gururajakr@sanyo.co.in>
+Date:	Tue Dec 18 16:03:07 2007 -0800
+
+    ARM: Display Ethernet info in do_bdinfo only if CONFIG_CMD_NET is defined
+
+    Add ifdef to bdinfo command to display ethernet information
+    only if CONFIG_CMD_NET is defined for arm modules.
+
+    Signed-off-by: K R Gururaja Hebbar <gururajakr@sanyo.co.in>
+
+commit f7ad79b6f9f0f45437b62e19b45356cc2aaf4884
+Author: Hebbar <gururajakr@sanyo.co.in>
+Date:	Tue Dec 18 16:00:54 2007 -0800
+
+    ARM: add I2C init function call in lib_arm/board.c
+
+    Adds I2C init func call to init sequence for ARM boards. This is
+    present in ppc,blackfin and other processor init sequence.
+
+    Signed-off-by: K R Gururaja Hebbar <gururajakr@sanyo.co.in>
+
+commit ff02f139804f3cb61414f7bbcbfdaa0279e3efae
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Feb 1 09:38:29 2008 +0100
+
+    ppc4xx: Fix ndfc HW ECC byte order
+
+    The current ndfc HW ECC implementation swaps the first two ECC bytes.
+    But the 4xx NDFC already uses the SMC (Smart Media Card) ECC ordering,
+    so this swapping in the HW ECC driver is bogus. This patch fixes this
+    problem and now really uses the SMC ECC byte order.
+
+    Thanks to Sean MacLennan for pointing this out.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e1d1429b49b0ee58c80f8c7b29c1ebaf8be7f5f1
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 30 15:35:50 2008 +0100
+
+    ppc4xx: Fix GPIO configuration for pcs440ep
+
+    The SRD0_PFC0 register was not configured correctly to enable the GPIO's
+    49-63 for GPIO. They have been configured as trace signals. This patch
+    fixes this by clearing the corresponding bit.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 28d77d968bfe0316deb5bf15c17f57d5ff2c8821
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 30 14:48:28 2008 +0100
+
+    ppc4xx: Fix problem with init-ram bigger than 4k on 440 platforms
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4fedfddf97461b88668b9aec774dfb7a0c6dc368
+Author: Ladislav Michl <ladis@linux-mips.org>
+Date:	Fri Dec 7 00:42:32 2007 +0100
+
+    ARM: Board voiceblue update
+
+    Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+
+commit 2c5260f711168d5ee91c70ddbb7d897013eefc46
+Author: Ladislav Michl <ladis@linux-mips.org>
+Date:	Thu Dec 6 23:24:57 2007 +0100
+
+    ARM: AT91RM9200 based boards config cleanup
+
+    Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+
+    Remove nowhere used struct bd_info_ext, remove trailing whitespaces, fix
+    indentation.
+
+commit 481f28b1db5cd21deb55f69399ba240e107af4c7
+Author: Ladislav Michl <ladis@linux-mips.org>
+Date:	Thu Dec 6 22:59:16 2007 +0100
+
+    ARM: Fix at91rm9200dk base address
+
+    Somewhere during development of U-Boot-1.1.3 CONFIG_BOOTBINFUNC was
+    renamed into CONFIG_INIT_CRITICAL which was 04 Apr 2005 replaced
+    with CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT.
+    However CONFIG_SKIP_LOWLEVEL_INIT has oposite meaning to
+    CONFIG_BOOTBINFUNC, so fix configuration to reflect this fact.
+    I'm sending this patch 4th (!) time in hope it produces at least some
+    reaction.
+
+    Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+
+    Fix at91rm9200dk base and environment address.
+
+commit c95219fae2a7add7daa2f91aedca65b1698465c7
+Author: stefano babic <sbabic@denx.de>
+Date:	Tue Nov 20 10:40:24 2007 +0100
+
+    MMC for PXA 27X (resubmit)
+
+    MMC support for X_Scale PXA is broken and does not work.
+    Mainly, the mmc_init() function cannot recognize current SD/MMC cards.
+    There were already some patches around the world but none of them was
+    merged into the official u-boot tree.
+
+    This patch makes order fixing this issue. Resubmit after code cleanup.
+
+    Applied and tested on PXA 270 (TrizepsIV module).
+
+    Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit 96bbfa1e6625ce23a150936863b3ecf4c853eb33
+Author: stefano babic <sbabic@denx.de>
+Date:	Tue Nov 20 10:37:04 2007 +0100
+
+    Fix gcc issues in pxa-regs.h
+
+    Fix gcc4 issue. With some toolchain, a previous patch that fixes gcc4
+    issues generates wrong code.
+    (Problem was reported with gcc-4.0.2-glibc-2.3.6/arm-softfloat-linux-gnu).
+    This patch fixes the problem and solves the gcc-4 issues as the linux
+    kernel does.
+
+    Signed-off-by: Stefano Babic <sbabic@denx.de>
+    Signed-off-by: Dmitry Ivanov <ivadmitry@gmail.com>
+
+commit 7047b388876e7b905b2ec4edb8010543e3641b85
+Author: Jens Gehrlein <sew_s@tqs.de>
+Date:	Tue Jan 29 08:45:03 2008 +0100
+
+    TQM834x: enable DHCP
+
+    Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit a877004d44ca7dbc1e618add3eeb1da7c84e4bec
+Author: Jens Gehrlein <sew_s@tqs.de>
+Date:	Tue Jan 29 08:45:02 2008 +0100
+
+    TQM834x: support for Spansion N-type Flashes (sector size = 256 KiB at 2x16 Bit).
+
+    Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 8931ab176025b03cfc320b3fd1eca432a88ed560
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sat Jan 26 23:41:19 2008 -0500
+
+    Fix conditional compilation of mpx8xxx_spi driver
+
+    This driver should only compile if CONFIG_MPC8XXX_SPI is set
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 63f732d3d3880feb531f48af247c025bf01462b0
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date:	Tue Jan 29 17:00:34 2008 +0100
+
+    API: Provide dummy halt() in the glue layer.
+
+    This fixes a demo app link failure on platforms configured with CONFIG_PANIC_HANG.
+
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 0dc1fc22af86d16993388d9ed9630dbaa2d51826
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date:	Tue Jan 29 16:57:38 2008 +0100
+
+    API: Convert conditional building to the new scheme.
+
+    This fixes a build breakage with CONFIG_API enabled, which appeared after
+    the recent changes in the U-Boot build system.
+
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 98b742489c09780be6a832eeaa4e5eff824792bb
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Jan 25 09:56:17 2008 +0100
+
+    inka4x0: remove dead code
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4f93f8b1a4d35b6d302842132edba920ef8f62aa
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Jan 23 16:31:06 2008 -0600
+
+    86xx: Add reginfo command
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit ddcebcb638715a6278da93b553d5016f99823816
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Jan 23 16:31:05 2008 -0600
+
+    86xx: Add print_laws function to fsl_law.c
+
+    This can be used for debug, and will be used by board code
+    to help implement reginfo.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 9cd32426f26a0567bb61f339edd83c6a2ce9bfc3
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Jan 23 16:31:04 2008 -0600
+
+    86xx: Remove old-style law setup code
+
+    This includes mpc8610hpcd, mpc8641hpcn, and sbc8641d.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 713d8186649dae874613d495b0cecaa039a98b30
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Jan 23 16:31:03 2008 -0600
+
+    86xx: Convert sbc8641d to use new law setup code.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 031976f6364b93833e989f57e9f1e023e0be8c4c
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Jan 23 16:31:02 2008 -0600
+
+    86xx: Convert mpc8610hpcd to new law setup method.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 4933b91f8a49e436681f163df3173beb91cac44a
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Jan 23 16:31:01 2008 -0600
+
+    86xx: Support new law setup method and convert mpc8641
+
+    Adds the support code in cpu/mpc86xx for the new law setup code
+    recently created fsl_law.c, and changes the MPC8641HPCN config
+    to use this code.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 1a41f7ce9c086e208c0eabf52565a237af2a2bd1
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Jan 23 16:31:00 2008 -0600
+
+    86xx: Rearrange the sequence in start.S
+
+    * split the BAT initialization so that only 2 BATs (for the boot page
+    and stack) are programmed very early on.  The rest are initialized later.
+    * Move other BAT setup,  ccsrbar setup, and law setup later in the code
+    after translation has been enabled.
+
+    These changes will facilitate the moving of law and BAT initialization
+    to C code, and will aid with 36-bit physical addressing support.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 33dac03b1b5d61e4fed7bad445ba40b4c97feba0
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jan 23 14:41:37 2008 +0100
+
+    Coding Style Cleanup; update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 865f0f9754b95183cad395de7e8cb85df0c6ea1f
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Wed Jan 23 14:31:17 2008 +0100

CREDITS

@@ -391,6 +391,10 @@ E: dan.poirot@windriver.com
 D: Support for the Wind River sbc405, sbc8240 board
 W: http://www.windriver.com
 
+N: Stelian Pop
+E: stelian.pop@leadtechdesign.com
+D: Atmel AT91CAP9ADK support
+
 N: Stefan Roese
 E: sr@denx.de
 D: AMCC PPC4xx Support
@@ -509,3 +513,19 @@ N: Nobuhiro Iwamatsu
 E: iwamatsu@nigauri.org
 D: Support for SuperH, MS7750SE01 and  MS7722SE01 boards.
 W: http://www.nigauri.org/~iwamatsu/
+
+N: Alan Lu
+E: alnalu001@gmail.com
+D: Support for Artila M-501 starter kit
+W: http://www.artila.com/
+
+N: Kimmo Leppala
+E: kimmo.leppala@sysart.fi
+D: Support for Artila M-501 starter kit
+W: http://www.sysart.fi/
+
+N: Timo Tuunainen
+E: timo.tuunainen@sysart.fi
+D: Support for Artila M-501 starter kit
+W: http://www.sysart.fi/
+

MAKEALL

@@ -446,6 +446,7 @@ LIST_ARM7="		\
 #########################################################################
 
 LIST_ARM9="			\
+	at91cap9adk		\
 	at91rm9200dk		\
 	cmc_pu2			\
 	ap920t			\
@@ -459,6 +460,7 @@ LIST_ARM9="			\
 	cp946es			\
 	cp966			\
 	lpd7a400		\
+	m501sk			\
 	mp2usb			\
 	mx1ads			\
 	mx1fs2			\
@@ -721,7 +723,7 @@ build_target() {
 	${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
 				| tee ${LOG_DIR}/$target.ERR
 
-	${CROSS_COMPILE:-ppc_8xx-}size ${BUILD_DIR}/u-boot \
+	${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
 				| tee -a ${LOG_DIR}/$target.MAKELOG
 }
 

Makefile

@@ -23,8 +23,8 @@
 
 VERSION = 1
 PATCHLEVEL = 3
-SUBLEVEL = 1
-EXTRAVERSION =
+SUBLEVEL = 2
+EXTRAVERSION = -rc1
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
@@ -185,18 +185,6 @@ endif
 ifeq ($(CPU),mpc85xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
-ifeq ($(CPU),bf533)
-OBJS += cpu/$(CPU)/start1.o	cpu/$(CPU)/interrupt.o	cpu/$(CPU)/cache.o
-OBJS += cpu/$(CPU)/flush.o	cpu/$(CPU)/init_sdram.o
-endif
-ifeq ($(CPU),bf537)
-OBJS += cpu/$(CPU)/start1.o	cpu/$(CPU)/interrupt.o	cpu/$(CPU)/cache.o
-OBJS += cpu/$(CPU)/flush.o	cpu/$(CPU)/init_sdram.o
-endif
-ifeq ($(CPU),bf561)
-OBJS += cpu/$(CPU)/start1.o	cpu/$(CPU)/interrupt.o	cpu/$(CPU)/cache.o
-OBJS += cpu/$(CPU)/flush.o 	cpu/$(CPU)/init_sdram.o
-endif
 
 OBJS := $(addprefix $(obj),$(OBJS))
 
@@ -253,9 +241,7 @@ LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
 	"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
 LIBS += common/libcommon.a
 LIBS += libfdt/libfdt.a
-ifeq ($(CONFIG_API),y)
 LIBS += api/libapi.a
-endif
 
 LIBS := $(addprefix $(obj),$(LIBS))
 .PHONY : $(LIBS)
@@ -266,11 +252,8 @@ PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -
 # The "tools" are needed early, so put this first
 # Don't include stuff already done in $(LIBS)
 SUBDIRS	= tools \
-	  examples
-
-ifeq ($(CONFIG_API),y)
-SUBDIRS += api_examples
-endif
+	  examples \
+	  api_examples
 
 .PHONY : $(SUBDIRS)
 
@@ -279,13 +262,21 @@ NAND_SPL = nand_spl
 U_BOOT_NAND = $(obj)u-boot-nand.bin
 endif
 
+ifeq ($(CONFIG_ONENAND_U_BOOT),y)
+ONENAND_IPL = onenand_ipl
+U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
+endif
+
 __OBJS := $(subst $(obj),,$(OBJS))
 __LIBS := $(subst $(obj),,$(LIBS))
 
 #########################################################################
 #########################################################################
 
-ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
+ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND)
+ifeq ($(ARCH),blackfin)
+ALL += $(obj)u-boot.ldr
+endif
 
 all:		$(ALL)
 
@@ -298,6 +289,15 @@ $(obj)u-boot.srec:	$(obj)u-boot
 $(obj)u-boot.bin:	$(obj)u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
 
+$(obj)u-boot.ldr:	$(obj)u-boot
+		$(LDR) -T $(CONFIG_BFIN_CPU) -f -c $@ $< $(LDR_FLAGS)
+
+$(obj)u-boot.ldr.hex:	$(obj)u-boot.ldr
+		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary
+
+$(obj)u-boot.ldr.srec:	$(obj)u-boot.ldr
+		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary
+
 $(obj)u-boot.img:	$(obj)u-boot.bin
 		./tools/mkimage -A $(ARCH) -T firmware -C none \
 		-a $(TEXT_BASE) -e 0 \
@@ -312,18 +312,18 @@ $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
 $(obj)u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
-		UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
+		UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
 		cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
 			--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
 			-Map u-boot.map -o u-boot
 
-$(OBJS):	$(obj)include/autoconf.mk
+$(OBJS):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
 
-$(LIBS):	$(obj)include/autoconf.mk
+$(LIBS):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C $(dir $(subst $(obj),,$@))
 
-$(SUBDIRS):	$(obj)include/autoconf.mk
+$(SUBDIRS):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C $@ all
 
 $(NAND_SPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
@@ -332,12 +332,19 @@ $(NAND_SPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
 $(U_BOOT_NAND):	$(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
 		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
 
+$(ONENAND_IPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
+		$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
+
+$(U_BOOT_ONENAND):	$(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
+		cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
+
 $(VERSION_FILE):
 		@( echo -n "#define U_BOOT_VERSION \"U-Boot " ; \
 		echo -n "$(U_BOOT_VERSION)" ; \
 		echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \
 			 $(TOPDIR)) ; \
-		echo "\"" ) > $(VERSION_FILE)
+		echo "\"" ) > $@.tmp
+		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
 
 gdbtools:
 		$(MAKE) -C tools/gdb all || exit 1
@@ -1225,9 +1232,11 @@ G2000_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
 
 hcu4_config:	unconfig
+	@mkdir -p $(obj)board/netstal/common
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal
 
 hcu5_config:	unconfig
+	@mkdir -p $(obj)board/netstal/common
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal
 
 HH405_config:	unconfig
@@ -2301,8 +2310,11 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$
 
 xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
 
+at91cap9adk_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91cap9
+
 at91rm9200dk_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
+	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
 
 cmc_pu2_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
@@ -2313,6 +2325,8 @@ csb637_config	:	unconfig
 mp2usb_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200
 
+m501sk_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm920t m501sk NULL at91rm9200
 
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
@@ -2353,17 +2367,8 @@ mx1ads_config	:	unconfig
 mx1fs2_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx
 
-netstar_32_config	\
 netstar_config:		unconfig
-	@mkdir -p $(obj)include
-	@if [ "$(findstring _32_,$@)" ] ; then \
-		$(XECHO) "... 32MB SDRAM" ; \
-		echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>$(obj)include/config.h ; \
-	else \
-		$(XECHO) "... 64MB SDRAM" ; \
-		echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>$(obj)include/config.h ; \
-	fi
-	@$(MKCONFIG) -a netstar arm arm925t netstar
+	@$(MKCONFIG) $(@:_config=) arm arm925t netstar
 
 omap1510inn_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
@@ -2602,7 +2607,9 @@ omap2420h4_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
 
 apollon_config		: unconfig
+	@echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
 	@$(MKCONFIG) $(@:_config=) arm arm1136 apollon
+	@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
 
 #========================================================================
 # i386
@@ -2815,20 +2822,19 @@ xupv2p_config:	unconfig
 	@echo "#define CONFIG_XUPV2P 1" >> $(obj)include/config.h
 	@$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx
 
-#########################################################################
-## Blackfin
-#########################################################################
-bf533-ezkit_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-ezkit
+#========================================================================
+# Blackfin
+#========================================================================
 
-bf533-stamp_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-stamp
+# Analog Devices boards
+BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit
 
-bf537-stamp_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) blackfin bf537 bf537-stamp
+$(BFIN_BOARDS:%=%_config)	: unconfig
+	@$(MKCONFIG) $(@:_config=) blackfin $(firstword $(subst -, ,$@)) $(@:_config=)
 
-bf561-ezkit_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) blackfin bf561 bf561-ezkit
+$(BFIN_BOARDS):
+	$(MAKE) $@_config
+	$(MAKE)
 
 #========================================================================
 # AVR32
@@ -2903,6 +2909,8 @@ clean:
 	@rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
+	@rm -f $(obj)onenand_ipl/onenand-ipl $(obj)onenand_ipl/onenand-ipl.bin \
+		$(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)onenand_ipl/onenand-ipl.map
 	@rm -f $(obj)api_examples/demo $(VERSION_FILE)
 
 clobber:	clean
@@ -2918,6 +2926,7 @@ clobber:	clean
 	@rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
 	@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
+	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -lname "*" -print | xargs rm -f
 	@[ ! -d $(obj)api_examples ] || find $(obj)api_examples -lname "*" -print | xargs rm -f
 
 ifeq ($(OBJTREE),$(SRCTREE))

README

@@ -3499,7 +3499,7 @@ GCC's implementation.
 
 For PowerPC, the following registers have specific use:
 	R1:	stack pointer
-	R2:	TOC pointer
+	R2:	reserved for system use
 	R3-R4:	parameter passing and return values
 	R5-R10: parameter passing
 	R13:	small data area pointer
@@ -3508,7 +3508,7 @@ For PowerPC, the following registers have specific use:
 
 	(U-Boot also uses R14 as internal GOT pointer.)
 
-    ==> U-Boot will use R29 to hold a pointer to the global data
+    ==> U-Boot will use R2 to hold a pointer to the global data
 
     Note: on PPC, we could use a static initializer (since the
     address of the global data structure is known at compile time),
@@ -3517,6 +3517,11 @@ For PowerPC, the following registers have specific use:
     average for all boards 752 bytes for the whole U-Boot image,
     624 text + 127 data).
 
+On Blackfin, the normal C ABI (except for P5) is followed as documented here:
+	http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
+
+    ==> U-Boot will use P5 to hold a pointer to the global data
+
 On ARM, the following registers are used:
 
 	R0:	function argument word/integer result

api/Makefile

@@ -24,13 +24,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)libapi.a
 
-COBJS	= api.o api_net.o api_storage.o api_platform-$(ARCH).o
+COBJS-$(CONFIG_API) += api.o api_net.o api_storage.o api_platform-$(ARCH).o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
-all:	$(LIB)
-
 $(LIB):	$(obj).depend $(OBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
 

api/api_storage.c

@@ -61,21 +61,21 @@ static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
 
 void dev_stor_init(void)
 {
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(CONFIG_CMD_IDE)
 	specs[ENUM_IDE].max_dev = CFG_IDE_MAXDEVICE;
 	specs[ENUM_IDE].enum_started = 0;
 	specs[ENUM_IDE].enum_ended = 0;
 	specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE;
 	specs[ENUM_IDE].name = "ide";
 #endif
-#if (CONFIG_COMMANDS & CFG_CMD_USB)
+#if defined(CONFIG_CMD_USB)
 	specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
 	specs[ENUM_USB].enum_started = 0;
 	specs[ENUM_USB].enum_ended = 0;
 	specs[ENUM_USB].type = DEV_TYP_STOR | DT_STOR_USB;
 	specs[ENUM_USB].name = "usb";
 #endif
-#if (CONFIG_COMMANDS & CFG_CMD_SCSI)
+#if defined(CONFIG_CMD_SCSI)
 	specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE;
 	specs[ENUM_SCSI].enum_started = 0;
 	specs[ENUM_SCSI].enum_ended = 0;

api_examples/Makefile

@@ -30,19 +30,25 @@ endif
 
 include $(TOPDIR)/config.mk
 
-ELF	+= demo
-BIN	+= demo.bin
+ELF-$(CONFIG_API) += demo
+BIN-$(CONFIG_API) += demo.bin
+ELF	:= $(ELF-y)
+BIN	:= $(BIN-y)
 
 #CFLAGS += -v
 
-COBJS	:= $(ELF:=.o)
-SOBJS	:= crt0.o
+COBJS-$(CONFIG_API) += $(ELF:=.o)
+SOBJS-$(CONFIG_API) += crt0.o
 ifeq ($(ARCH),ppc)
-SOBJS	+= ppcstring.o
+SOBJS-$(CONFIG_API) += ppcstring.o
 endif
+COBJS	:= $(COBJS-y)
+SOBJS	:= $(SOBJS-y)
 
 LIB	= $(obj)libglue.a
-LIBCOBJS= glue.o crc32.o ctype.o string.o vsprintf.o libgenwrap.o
+LIBCOBJS-$(CONFIG_API) += glue.o crc32.o ctype.o string.o vsprintf.o \
+				libgenwrap.o
+LIBCOBJS := $(LIBCOBJS-y)
 
 LIBOBJS	= $(addprefix $(obj),$(SOBJS) $(LIBCOBJS))
 
@@ -55,7 +61,7 @@ gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
 
 CPPFLAGS += -I..
 
-all:	$(obj).depend $(OBJS) $(LIB) $(BIN) $(ELF)
+all:	$(obj).depend $(OBJS) $(LIB) $(ELF) $(BIN)
 
 #########################################################################
 $(LIB):	$(obj).depend $(LIBOBJS)

api_examples/libgenwrap.c

@@ -84,7 +84,12 @@ void do_reset (void)
 	ub_reset();
 }
 
-void *malloc(size_t len)
+void *malloc (size_t len)
 {
 	return NULL;
 }
+
+void hang (void)
+{
+	while (1) ;
+}

blackfin_config.mk

@@ -21,4 +21,12 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__BLACKFIN__
+PLATFORM_RELFLAGS += -ffixed-P5
+PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
+
+SYM_PREFIX = _
+
+LDR_FLAGS += --use-vmas
+ifeq (,$(findstring s,$(MAKEFLAGS)))
+LDR_FLAGS += --quiet
+endif

board/BuS/EB+MCF-EV123/mii.c

@@ -132,7 +132,7 @@ uint mii_send(uint mii_cmd)
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
 
 #if defined(CFG_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)

board/amcc/sequoia/sequoia.c

@@ -86,10 +86,13 @@ int board_early_init_f(void)
 	/* enable USB device */
 	out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
 
-	/* select Ethernet pins */
+	/* select Ethernet (and optionally IIC1) pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
 	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
 		SDR0_PFC1_SELECT_CONFIG_4;
+#ifdef CONFIG_I2C_MULTI_BUS
+	sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
+#endif
 	mfsdr(SDR0_PFC2, sdr0_pfc2);
 	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 		SDR0_PFC2_SELECT_CONFIG_4;

board/apollon/apollon.c

@@ -440,7 +440,8 @@ void muxSetupTouchScreen(void)
 void muxSetupGPMC(void)
 {
 	/* gpmc_io_dir, MCR */
-	writel(0x4800008C, 0x19000000);
+	volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
+	*MCR = 0x19000000;
 
 	/* NOR FLASH CS0 */
 	/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */

board/atmel/at91cap9adk/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= at91cap9adk.o led.o nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/atmel/at91cap9adk/at91cap9adk.c

@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91CAP9.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+
+#define MP_BLOCK_3_BASE	0xFDF00000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void at91cap9_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
+#endif
+
+#ifdef CONFIG_USART1
+	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
+#endif
+
+#ifdef CONFIG_USART2
+	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
+#endif
+
+
+}
+
+static void at91cap9_nor_hw_init(void)
+{
+	/* Ensure EBI supply is 3.3V */
+	AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
+
+	/* Configure SMC CS0 for parallel flash */
+	AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
+				     AT91C_FLASH_NCS_WR_SETUP |
+				     AT91C_FLASH_NRD_SETUP |
+				     AT91C_FLASH_NCS_RD_SETUP;
+
+	AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
+				     AT91C_FLASH_NCS_WR_PULSE |
+				     AT91C_FLASH_NRD_PULSE |
+				     AT91C_FLASH_NCS_RD_PULSE;
+
+	AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
+				     AT91C_FLASH_NRD_CYCLE;
+
+	AT91C_BASE_SMC->SMC_CTRL0 =  AT91C_SMC_READMODE |
+				     AT91C_SMC_WRITEMODE |
+				     AT91C_SMC_NWAITM_NWAIT_DISABLE |
+				     AT91C_SMC_BAT_BYTE_WRITE |
+				     AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
+				     (AT91C_SMC_TDF & (1 << 16));
+}
+
+#ifdef CONFIG_CMD_NAND
+static void at91cap9_nand_hw_init(void)
+{
+	/* Enable CS3 */
+	AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
+				     AT91C_SM_NCS_WR_SETUP |
+				     AT91C_SM_NRD_SETUP |
+				     AT91C_SM_NCS_RD_SETUP;
+
+	AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
+				     AT91C_SM_NCS_WR_PULSE |
+				     AT91C_SM_NRD_PULSE |
+				     AT91C_SM_NCS_RD_PULSE;
+
+	AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
+				     AT91C_SM_NRD_CYCLE;
+
+	AT91C_BASE_SMC->SMC_CTRL3 =  AT91C_SMC_READMODE |
+				     AT91C_SMC_WRITEMODE |
+				     AT91C_SMC_NWAITM_NWAIT_DISABLE |
+				     AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
+				     AT91C_SM_TDF;
+
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
+
+	/* RDY/BSY is not connected */
+
+	/* Enable NandFlash */
+	AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
+	AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
+}
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+static void at91cap9_spi_hw_init(void)
+{
+	AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
+				   AT91C_PD1_SPI0_NPCS3D;
+	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
+				   AT91C_PD1_SPI0_NPCS3D;
+
+	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
+	AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
+				   AT91C_PA1_SPI0_MOSI |
+				   AT91C_PA0_SPI0_MISO |
+				   AT91C_PA3_SPI0_NPCS1 |
+				   AT91C_PA5_SPI0_NPCS0 |
+				   AT91C_PA2_SPI0_SPCK;
+	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
+				   AT91C_PA4_SPI0_NPCS2A |
+				   AT91C_PA1_SPI0_MOSI |
+				   AT91C_PA0_SPI0_MISO |
+				   AT91C_PA3_SPI0_NPCS1 |
+				   AT91C_PA5_SPI0_NPCS0 |
+				   AT91C_PA2_SPI0_SPCK;
+
+	/* Enable Clock */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91cap9_macb_hw_init(void)
+{
+	unsigned int gpio;
+
+	/* Enable clock */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PB22) => PHY normal mode (not Test mode)
+	 *	ERX0 (PB25) => PHY ADDR0
+	 *	ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
+				     AT91C_PB25_E_RX0 |
+				     AT91C_PB26_E_RX1;
+
+	/* Need to reset PHY -> 500ms reset */
+	AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
+				    (AT91C_RSTC_ERSTL & (0x0D << 8)) |
+				    AT91C_RSTC_URSTEN;
+	AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
+				    AT91C_RSTC_EXTRST;
+
+	/* Wait for end hardware reset */
+	while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
+
+	/* Re-enable pull-up */
+	AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
+				     AT91C_PB25_E_RX0 |
+				     AT91C_PB26_E_RX1;
+
+#ifdef CONFIG_RMII
+	gpio =	AT91C_PB30_E_MDIO |
+		AT91C_PB29_E_MDC  |
+		AT91C_PB21_E_TXCK |
+		AT91C_PB27_E_RXER |
+		AT91C_PB25_E_RX0  |
+		AT91C_PB22_E_RXDV |
+		AT91C_PB26_E_RX1  |
+		AT91C_PB28_E_TXEN |
+		AT91C_PB23_E_TX0  |
+		AT91C_PB24_E_TX1;
+	AT91C_BASE_PIOB->PIO_ASR = gpio;
+	AT91C_BASE_PIOB->PIO_BSR = 0;
+	AT91C_BASE_PIOB->PIO_PDR = gpio;
+#else
+#error AT91CAP9A-DK works only in RMII mode
+#endif
+
+	/* Unlock EMAC, 3 0 2 1 sequence */
+#define MP_MAC_KEY0	0x5969cb2a
+#define MP_MAC_KEY1	0xb4a1872e
+#define MP_MAC_KEY2	0x05683fbc
+#define MP_MAC_KEY3	0x3634fba4
+#define UNLOCK_MAC	0x00000008
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_NEW
+static void at91cap9_uhp_hw_init(void)
+{
+	/* Unlock USB OHCI, 3 2 0 1 sequence */
+#define MP_OHCI_KEY0	0x896c11ca
+#define MP_OHCI_KEY1	0x68ebca21
+#define MP_OHCI_KEY2	0x4823efbc
+#define MP_OHCI_KEY3	0x8651aae4
+#define UNLOCK_OHCI	0x00000010
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
+	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
+}
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91CAP9ADK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91cap9_serial_hw_init();
+	at91cap9_nor_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91cap9_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91cap9_spi_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	at91cap9_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91cap9_uhp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif

board/atmel/at91cap9adk/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x73000000

board/atmel/at91cap9adk/led.c

@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91CAP9.h>
+
+#define	RED_LED		AT91C_PIO_PC29	/* this is the power led */
+#define	GREEN_LED	AT91C_PIO_PA10	/* this is the user1 led */
+#define	YELLOW_LED	AT91C_PIO_PA11	/* this is the user1 led */
+
+void red_LED_on(void)
+{
+	AT91C_BASE_PIOC->PIO_SODR = RED_LED;
+}
+
+void red_LED_off(void)
+{
+	AT91C_BASE_PIOC->PIO_CODR = RED_LED;
+}
+
+void green_LED_on(void)
+{
+	AT91C_BASE_PIOA->PIO_CODR = GREEN_LED;
+}
+
+void green_LED_off(void)
+{
+	AT91C_BASE_PIOA->PIO_SODR = GREEN_LED;
+}
+
+void yellow_LED_on(void)
+{
+	AT91C_BASE_PIOA->PIO_CODR = YELLOW_LED;
+}
+
+void yellow_LED_off(void)
+{
+	AT91C_BASE_PIOA->PIO_SODR = YELLOW_LED;
+}
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
+
+	/* Disable peripherals on LEDs */
+	AT91C_BASE_PIOA->PIO_PER = GREEN_LED | YELLOW_LED;
+	/* Enable pins as outputs */
+	AT91C_BASE_PIOA->PIO_OER = GREEN_LED | YELLOW_LED;
+	/* Turn all LEDs OFF */
+	AT91C_BASE_PIOA->PIO_SODR = GREEN_LED | YELLOW_LED;
+
+	/* Disable peripherals on LEDs */
+	AT91C_BASE_PIOC->PIO_PER = RED_LED;
+	/* Enable pins as outputs */
+	AT91C_BASE_PIOC->PIO_OER = RED_LED;
+	/* Turn all LEDs OFF */
+	AT91C_BASE_PIOC->PIO_CODR = RED_LED;
+}

board/atmel/at91cap9adk/nand.c

@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_CMD_NAND
+
+#include <nand.h>
+
+/*
+ *	hardware specific access to control-lines
+ */
+#define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
+#define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
+
+static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	struct nand_chip *this = mtd->priv;
+	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		IO_ADDR_W |= MASK_CLE;
+		break;
+	case NAND_CTL_SETALE:
+		IO_ADDR_W |= MASK_ALE;
+		break;
+	case NAND_CTL_CLRNCE:
+		AT91C_BASE_PIOD->PIO_SODR = AT91C_PIO_PD15;
+		break;
+	case NAND_CTL_SETNCE:
+		AT91C_BASE_PIOD->PIO_CODR = AT91C_PIO_PD15;
+		break;
+	}
+	this->IO_ADDR_W = (void *) IO_ADDR_W;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->hwcontrol = at91cap9adk_nand_hwcontrol;
+	nand->chip_delay = 20;
+
+	return 0;
+}
+#endif

board/atmel/at91cap9adk/u-boot.lds

@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj <at> denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/atmel/atngw100/atngw100.c

@@ -23,6 +23,7 @@
 
 #include <asm/io.h>
 #include <asm/sdram.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/hmatrix2.h>
 
@@ -40,6 +41,8 @@ static const struct sdram_info sdram = {
 	.trcd		= 2,
 	.tras		= 5,
 	.txsr		= 5,
+	/* 7.81 us */
+	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
 };
 
 int board_early_init_f(void)

board/atmel/atstk1000/atstk1000.c

@@ -23,6 +23,7 @@
 
 #include <asm/io.h>
 #include <asm/sdram.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/hmatrix2.h>
 
@@ -40,6 +41,8 @@ static const struct sdram_info sdram = {
 	.trcd		= 2,
 	.tras		= 5,
 	.txsr		= 5,
+	/* 15.6 us */
+	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
 };
 
 int board_early_init_f(void)

board/atmel/atstk1000/flash.c

@@ -159,7 +159,7 @@ int __flashprog write_buff(flash_info_t *info, uchar *src,
 {
 	unsigned long flags;
 	uint16_t *base, *p, *s, *end;
-	uint16_t word, status;
+	uint16_t word, status, status1;
 	int ret = ERR_OK;
 
 	if (addr < info->start[0]
@@ -194,20 +194,33 @@ int __flashprog write_buff(flash_info_t *info, uchar *src,
 		sync_write_buffer();
 
 		/* Wait for completion */
+		status1 = readw(p);
 		do {
 			/* TODO: Timeout */
-			status = readw(p);
-		} while ((status != word) && !(status & 0x28));
+			status = status1;
+			status1 = readw(p);
+		} while (((status ^ status1) & 0x40)	/* toggled */
+			 && !(status1 & 0x28));		/* error bits */
 
-		writew(0xf0, base);
-		readw(base);
-
-		if (status != word) {
-			printf("Flash write error at address 0x%p: 0x%02x\n",
-			       p, status);
+		/*
+		 * We'll need to check once again for toggle bit
+		 * because the toggle bit may stop toggling as I/O5
+		 * changes to "1" (ref at49bv642.pdf p9)
+		 */
+		status1 = readw(p);
+		status = readw(p);
+		if ((status ^ status1) & 0x40) {
+			printf("Flash write error at address 0x%p: "
+			       "0x%02x != 0x%02x\n",
+			       p, status,word);
 			ret = ERR_PROG_ERROR;
+			writew(0xf0, base);
+			readw(base);
 			break;
 		}
+
+		writew(0xf0, base);
+		readw(base);
 	}
 
 	if (flags)

board/bf533-ezkit/.gitignore

@@ -0,0 +1 @@
+/u-boot.lds

board/bf533-ezkit/flash.c

@@ -286,9 +286,9 @@ int write_flash(long nOffset, int nValue)
 	long addr;
 
 	addr = (CFG_FLASH_BASE + nOffset);
-	sync();
+	SSYNC();
 	*(unsigned volatile short *)addr = nValue;
-	sync();
+	SSYNC();
 	if (poll_toggle_bit(nOffset) < 0)
 		return FLASH_FAIL;
 	return FLASH_SUCCESS;
@@ -301,9 +301,9 @@ int read_flash(long nOffset, int *pnValue)
 
 	if (nOffset != 0x2)
 		reset_flash();
-	sync();
+	SSYNC();
 	nValue = *(volatile unsigned short *)addr;
-	sync();
+	SSYNC();
 	*pnValue = nValue;
 	return TRUE;
 }

board/bf533-stamp/.gitignore

@@ -0,0 +1 @@
+/u-boot.lds

board/bf533-stamp/bf533-stamp.c

@@ -76,9 +76,9 @@ void swap_to(int device_id)
 
 	if (device_id == ETHERNET) {
 		*pFIO_DIR = PF0;
-		sync();
+		SSYNC();
 		*pFIO_FLAG_S = PF0;
-		sync();
+		SSYNC();
 	} else if (device_id == FLASH) {
 		*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
 		*pFIO_FLAG_S = (PF4 | PF3 | PF2);
@@ -88,7 +88,7 @@ void swap_to(int device_id)
 		*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
 		*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
 		*pFIO_FLAG_D = (PF4 | PF3 | PF2);
-		sync();
+		SSYNC();
 	} else {
 		printf("Unknown bank to switch\n");
 	}
@@ -155,15 +155,15 @@ void cf_outb(unsigned char val, volatile unsigned char *addr)
 	 */
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	*(addr) = val;
-	sync();
+	SSYNC();
 
 	/* Setback PF1 PF0 to 0 0 to address external
 	 * memory banks  */
 	*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 }
 
 unsigned char cf_inb(volatile unsigned char *addr)
@@ -172,13 +172,13 @@ unsigned char cf_inb(volatile unsigned char *addr)
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	c = *(addr);
-	sync();
+	SSYNC();
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 
 	return c;
 }
@@ -189,15 +189,15 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	for (i = 0; i < words; i++) {
 		*(sect_buf + i) = *(addr);
-		sync();
+		SSYNC();
 	}
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 }
 
 void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
@@ -206,15 +206,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	for (i = 0; i < words; i++) {
 		*(addr) = *(sect_buf + i);
-		sync();
+		SSYNC();
 	}
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 }
 #endif
 
@@ -235,7 +235,7 @@ void stamp_led_set(int LED1, int LED2, int LED3)
 		*pFIO_FLAG_S = PF4;
 	else
 		*pFIO_FLAG_C = PF4;
-	sync();
+	SSYNC();
 }
 
 void show_boot_progress(int status)

board/bf533-stamp/spi.c

@@ -4,6 +4,7 @@
 #include <common.h>
 #include <linux/ctype.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/spi.h>
 
 #if defined(CONFIG_SPI)
 
@@ -153,7 +154,7 @@ void SendSingleCommand(const int iCommand)
 
 	/*sends the actual command to the SPI TX register */
 	*pSPI_TDBR = iCommand;
-	sync();
+	SSYNC();
 
 	/*The SPI status register will be polled to check the SPIF bit */
 	Wait_For_SPIF();
@@ -174,7 +175,7 @@ void SetupSPI(const int spi_setting)
 	*pSPI_FLG = 0xFB04;
 	*pSPI_BAUD = CONFIG_SPI_BAUD;
 	*pSPI_CTL = spi_setting;
-	sync();
+	SSYNC();
 }
 
 void SPI_OFF(void)
@@ -183,7 +184,7 @@ void SPI_OFF(void)
 	*pSPI_CTL = 0x0400;	/* disable SPI */
 	*pSPI_FLG = 0;
 	*pSPI_BAUD = 0;
-	sync();
+	SSYNC();
 	udelay(CONFIG_CCLK_HZ / 50000000);
 
 }
@@ -241,10 +242,10 @@ char ReadStatusRegister(void)
 	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turn on the SPI */
 
 	*pSPI_TDBR = SPI_RDSR;	/* send instruction to read status register */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	*pSPI_TDBR = 0;		/*send dummy to receive the status register */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the data has been sent */
 	status_register = *pSPI_RDBR;	/*read the status register */
 
@@ -305,18 +306,18 @@ ERROR_CODE EraseBlock(int nBlock)
 	/* Send the erase block command to the flash followed by the 24 address  */
 	/* to point to the start of a sector. */
 	*pSPI_TDBR = SPI_SE;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();
 	ShiftValue = (ulSectorOff >> 16);	/* Send the highest byte of the 24 bit address at first */
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	ShiftValue = (ulSectorOff >> 8);	/* Send the middle byte of the 24 bit address  at second */
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	*pSPI_TDBR = ulSectorOff;	/* Send the lowest byte of the 24 bit address finally */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 
 	/*Turns off the SPI */
@@ -351,25 +352,25 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
 	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
 
 	*pSPI_TDBR = SPI_READ;	/* Send the read command to SPI device */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	ShiftValue = (ulStart >> 16);	/* Send the highest byte of the 24 bit address at first */
 	*pSPI_TDBR = ShiftValue;	/* Send the byte to the SPI device */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	ShiftValue = (ulStart >> 8);	/* Send the middle byte of the 24 bit address  at second */
 	*pSPI_TDBR = ShiftValue;	/* Send the byte to the SPI device */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	*pSPI_TDBR = ulStart;	/* Send the lowest byte of the 24 bit address finally */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 
 	/* After the SPI device address has been placed on the MOSI pin the data can be */
 	/* received on the MISO pin. */
 	for (i = 0; i < lCount; i++) {
 		*pSPI_TDBR = 0;	/*send dummy */
-		sync();
+		SSYNC();
 		while (!(*pSPI_STAT & RXS)) ;
 		*cnData++ = *pSPI_RDBR;	/*read  */
 
@@ -406,26 +407,26 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
 		/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
 		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turns the SPI on */
 	*pSPI_TDBR = SPI_PP;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	ulWAddr = (ulStartAddr >> 16);
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	ulWAddr = (ulStartAddr >> 8);
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	ulWAddr = ulStartAddr;
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	/* Fourth, maximum number of 256 bytes will be taken from the Buffer */
 	/* and sent to the SPI device. */
 	for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
 		iData = *temp;
 		*pSPI_TDBR = iData;
-		sync();
+		SSYNC();
 		Wait_For_SPIF();	/*wait until the instruction has been sent */
 		temp++;
 	}

board/bf537-stamp/.gitignore

@@ -0,0 +1 @@
+/u-boot.lds

board/bf537-stamp/bf537-stamp.c

@@ -32,6 +32,7 @@
 #include <asm/io.h>
 #include <net.h>
 #include "ether_bf537.h"
+#include <asm/mach-common/bits/bootrom.h>
 
 /**
  * is_valid_ether_addr - Determine if the given Ethernet address is valid
@@ -117,7 +118,7 @@ int checkboard(void)
 void cf_outb(unsigned char val, volatile unsigned char *addr)
 {
 	*(addr) = val;
-	sync();
+	SSYNC();
 }
 
 unsigned char cf_inb(volatile unsigned char *addr)
@@ -125,7 +126,7 @@ unsigned char cf_inb(volatile unsigned char *addr)
 	volatile unsigned char c;
 
 	c = *(addr);
-	sync();
+	SSYNC();
 
 	return c;
 }
@@ -136,7 +137,7 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
 
 	for (i = 0; i < words; i++)
 		*(sect_buf + i) = *(addr);
-	sync();
+	SSYNC();
 }
 
 void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
@@ -145,7 +146,7 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
 
 	for (i = 0; i < words; i++)
 		*(addr) = *(sect_buf + i);
-	sync();
+	SSYNC();
 }
 #endif				/* CONFIG_BFIN_IDE */
 

board/bf537-stamp/ether_bf537.c

@@ -30,6 +30,10 @@
 #include <malloc.h>
 #include "ether_bf537.h"
 
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/emac.h>
+#include <asm/mach-common/bits/pll.h>
+
 #ifdef CONFIG_POST
 #include <post.h>
 #endif
@@ -364,7 +368,7 @@ int SetupSystemRegs(int *opmode)
 	u16 sysctl, phydat;
 	int count = 0;
 	/* Enable PHY output */
-	*pVR_CTL |= PHYCLKOE;
+	*pVR_CTL |= CLKBUFOE;
 	/* MDC  = 2.5 MHz */
 	sysctl = SET_MDCDIV(24);
 	/* Odd word alignment for Receive Frame DMA word */

board/bf537-stamp/flash.c

@@ -255,7 +255,7 @@ int write_flash(long nOffset, int nValue)
 
 	addr = (CFG_FLASH_BASE + nOffset);
 	*(unsigned volatile short *)addr = nValue;
-	sync();
+	SSYNC();
 #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
 	if (icache_status())
 		udelay(CONFIG_CCLK_HZ / 1000000);

board/bf537-stamp/nand.c

@@ -64,13 +64,13 @@ static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
 	this->IO_ADDR_R = this->IO_ADDR_W;
 
 	/* Drain the writebuffer */
-	sync();
+	SSYNC();
 }
 
 int bfin_device_ready(struct mtd_info *mtd)
 {
 	int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
-	sync();
+	SSYNC();
 	return ret;
 }
 

board/bf537-stamp/post-memory.c

@@ -104,15 +104,15 @@ void post_init_uart(int sclk)
 
 	*pUART_GCTL = 0x00;
 	*pUART_LCR = 0x83;
-	sync();
+	SSYNC();
 	*pUART_DLL = (divisor & 0xFF);
-	sync();
+	SSYNC();
 	*pUART_DLH = ((divisor >> 8) & 0xFF);
-	sync();
+	SSYNC();
 	*pUART_LCR = 0x03;
-	sync();
+	SSYNC();
 	*pUART_GCTL = 0x01;
-	sync();
+	SSYNC();
 }
 
 void post_out_buff(char *buff)
@@ -124,7 +124,7 @@ void post_out_buff(char *buff)
 	while ((buff[i] != '\0') && (i != 100)) {
 		while (!(*pUART_LSR & 0x20)) ;
 		*pUART_THR = buff[i];
-		sync();
+		SSYNC();
 		i++;
 	}
 	for (i = 0; i < 0x80000; i++) ;
@@ -141,7 +141,7 @@ int post_key_pressed(void)
 	*pPORTF_FER &= ~PF5;
 	*pPORTFIO_DIR &= ~PF5;
 	*pPORTFIO_INEN |= PF5;
-	sync();
+	SSYNC();
 
 	post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
 	for (i = 0; i < KEY_LOOP; i++) {
@@ -303,7 +303,7 @@ int post_init_sdram(int sclk)
 	    (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
 	     | PSS);
 
-	sync();
+	SSYNC();
 
 	*pEBIU_SDGCTL |= 0x1000000;
 	/* Set the SDRAM Refresh Rate control register based on SSCLK value */
@@ -314,7 +314,7 @@ int post_init_sdram(int sclk)
 
 	/* SDRAM Memory Global Control Register */
 	*pEBIU_SDGCTL = mem_SDGCTL;
-	sync();
+	SSYNC();
 	return mem_SDRRC;
 }
 

board/bf537-stamp/stm_m25p64.c

@@ -4,6 +4,7 @@
 #include <common.h>
 #include <linux/ctype.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/spi.h>
 
 #if defined(CONFIG_SPI)
 
@@ -142,7 +143,7 @@ void SendSingleCommand(const int iCommand)
 
 	/* sends the actual command to the SPI TX register */
 	*pSPI_TDBR = iCommand;
-	sync();
+	SSYNC();
 
 	/* The SPI status register will be polled to check the SPIF bit */
 	Wait_For_SPIF();
@@ -164,10 +165,10 @@ void SetupSPI(const int spi_setting)
 	*pSPI_FLG = 0xFF02;
 	*pSPI_BAUD = CONFIG_SPI_BAUD;
 	*pSPI_CTL = spi_setting;
-	sync();
+	SSYNC();
 
 	*pSPI_FLG = 0xFD02;
-	sync();
+	SSYNC();
 }
 
 void SPI_OFF(void)
@@ -176,7 +177,7 @@ void SPI_OFF(void)
 	*pSPI_CTL = 0x0400;	/* disable SPI */
 	*pSPI_FLG = 0;
 	*pSPI_BAUD = 0;
-	sync();
+	SSYNC();
 	udelay(CONFIG_CCLK_HZ / 50000000);
 
 }
@@ -234,10 +235,10 @@ char ReadStatusRegister(void)
 	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turn on the SPI */
 
 	*pSPI_TDBR = SPI_RDSR;	/* send instruction to read status register */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	*pSPI_TDBR = 0;		/*send dummy to receive the status register */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the data has been sent */
 	status_register = *pSPI_RDBR;	/*read the status register */
 
@@ -300,23 +301,23 @@ ERROR_CODE EraseBlock(int nBlock)
 	 * to point to the start of a sector
 	 */
 	*pSPI_TDBR = SPI_SE;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();
 	/* Send the highest byte of the 24 bit address at first */
 	ShiftValue = (ulSectorOff >> 16);
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/* Send the middle byte of the 24 bit address  at second */
 	ShiftValue = (ulSectorOff >> 8);
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/* Send the lowest byte of the 24 bit address finally */
 	*pSPI_TDBR = ulSectorOff;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 
@@ -357,33 +358,33 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
 	/* Send the read command to SPI device */
 	*pSPI_TDBR = SPI_READ;
 #endif
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/* Send the highest byte of the 24 bit address at first */
 	ShiftValue = (ulStart >> 16);
 	/* Send the byte to the SPI device */
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/* Send the middle byte of the 24 bit address  at second */
 	ShiftValue = (ulStart >> 8);
 	/* Send the byte to the SPI device */
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/* Send the lowest byte of the 24 bit address finally */
 	*pSPI_TDBR = ulStart;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 
 #ifdef CONFIG_SPI_FLASH_FAST_READ
 	/* Send dummy for FAST_READ */
 	*pSPI_TDBR = 0;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 #endif
@@ -392,7 +393,7 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
 	/* received on the MISO pin. */
 	for (i = 0; i < lCount; i++) {
 		*pSPI_TDBR = 0;
-		sync();
+		SSYNC();
 		while (!(*pSPI_STAT & RXS)) ;
 		*cnData++ = *pSPI_RDBR;
 
@@ -435,22 +436,22 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
 		 */
 		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
 	*pSPI_TDBR = SPI_PP;
-	sync();
+	SSYNC();
 	/*wait until the instruction has been sent */
 	Wait_For_SPIF();
 	ulWAddr = (ulStartAddr >> 16);
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	/*wait until the instruction has been sent */
 	Wait_For_SPIF();
 	ulWAddr = (ulStartAddr >> 8);
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	/*wait until the instruction has been sent */
 	Wait_For_SPIF();
 	ulWAddr = ulStartAddr;
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	/*wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/*
@@ -460,7 +461,7 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
 	for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
 		iData = *temp;
 		*pSPI_TDBR = iData;
-		sync();
+		SSYNC();
 		/*wait until the instruction has been sent */
 		Wait_For_SPIF();
 		temp++;

board/bf561-ezkit/.gitignore

@@ -0,0 +1 @@
+/u-boot.lds

board/bf561-ezkit/bf561-ezkit.c

@@ -65,9 +65,9 @@ int misc_init_r(void)
 	/* Keep PF12 low to be able to drive the USB-LAN Extender */
 	*pFIO0_DIR = 0x0000;
 	*pFIO0_FLAG_C = 0x1000;	/* Clear PF12 */
-	sync();
+	SSYNC();
 	*pFIO0_POLAR = 0x0000;
-	sync();
+	SSYNC();
 
 	return 0;
 }

board/cobra5272/mii.c

@@ -131,7 +131,7 @@ uint mii_send(uint mii_cmd)
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
 
 #if defined(CFG_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)

board/freescale/common/sys_eeprom.c

@@ -79,7 +79,7 @@ int mac_show(void)
 	/* Show Build Date,
 	 * BCD date values, as YYMMDDhhmmss.
 	 */
-	printf("Date 20%02x\/%02x\/%02x %02x:%02x:%02x\n",
+	printf("Date 20%02x/%02x/%02x %02x:%02x:%02x\n",
 	       mac_data.date[0],
 	       mac_data.date[1],
 	       mac_data.date[2],

board/freescale/mpc8610hpcd/Makefile

@@ -27,9 +27,7 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-SOBJS	:= init.o
-
-COBJS	:= $(BOARD).o
+COBJS	:= $(BOARD).o law.o
 
 COBJS-${CONFIG_FSL_DIU_FB}	+= mpc8610hpcd_diu.o
 

board/freescale/mpc8610hpcd/init.S

@@ -1,147 +0,0 @@
-/*
- * Copyright 2007 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <config.h>
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <mpc86xx.h>
-
-#define LAWAR_TRGT_PCI1		0x00000000
-#define LAWAR_TRGT_PCIE1	0x00200000
-#define LAWAR_TRGT_PCIE2	0x00100000
-#define LAWAR_TRGT_LBC		0x00400000
-#define LAWAR_TRGT_DDR		0x00f00000
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
-#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#else
-#define LAWBAR1 0
-#define LAWAR1	((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff)
-#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff)
-#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
-
-#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff)
-#define LAWAR5	(LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff)
-#define LAWAR6	(LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff)
-#define LAWAR7	(LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff)
-#define LAWAR8	(LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
-#define LAWAR9	(LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	lis	r7,CFG_CCSRBAR@h
-	ori	r7,r7,CFG_CCSRBAR@l
-
-	addi	r4,r7,0
-	addi	r5,r7,0
-
-	/* Skip LAWAR0, start at LAWAR1 */
-	lis	r6,LAWBAR1@h
-	ori	r6,r6,LAWBAR1@l
-	stwu	r6, 0xc28(r4)
-
-	lis	r6,LAWAR1@h
-	ori	r6,r6,LAWAR1@l
-	stwu	r6, 0xc30(r5)
-
-	/* LAWBAR2, LAWAR2 */
-	lis	r6,LAWBAR2@h
-	ori	r6,r6,LAWBAR2@l
-	stwu	r6, 0x20(r4)
-
-	lis	r6,LAWAR2@h
-	ori	r6,r6,LAWAR2@l
-	stwu	r6, 0x20(r5)
-
-	/* LAWBAR3, LAWAR3 */
-	lis	r6,LAWBAR3@h
-	ori	r6,r6,LAWBAR3@l
-	stwu	r6, 0x20(r4)
-
-	lis	r6,LAWAR3@h
-	ori	r6,r6,LAWAR3@l
-	stwu	r6, 0x20(r5)
-
-	/* LAWBAR4, LAWAR4 */
-	lis	r6,LAWBAR4@h
-	ori	r6,r6,LAWBAR4@l
-	stwu	r6, 0x20(r4)
-
-	lis	r6,LAWAR4@h
-	ori	r6,r6,LAWAR4@l
-	stwu	r6, 0x20(r5)
-	/* LAWBAR5, LAWAR5 */
-	lis	r6,LAWBAR5@h
-	ori	r6,r6,LAWBAR5@l
-	stwu	r6, 0x20(r4)
-
-	lis	r6,LAWAR5@h
-	ori	r6,r6,LAWAR5@l
-	stwu	r6, 0x20(r5)
-
-	/* LAWBAR6, LAWAR6 */
-	lis	r6,LAWBAR6@h
-	ori	r6,r6,LAWBAR6@l
-	stwu	r6, 0x20(r4)
-
-	lis	r6,LAWAR6@h
-	ori	r6,r6,LAWAR6@l
-	stwu	r6, 0x20(r5)
-
-	/* LAWBAR7, LAWAR7 */
-	lis	r6,LAWBAR7@h
-	ori	r6,r6,LAWBAR7@l
-	stwu	r6, 0x20(r4)
-
-	lis	r6,LAWAR7@h
-	ori	r6,r6,LAWAR7@l
-	stwu	r6, 0x20(r5)
-
-	/* LAWBAR8, LAWAR8 */
-	lis	r6,LAWBAR8@h
-	ori	r6,r6,LAWBAR8@l
-	stwu	r6, 0x20(r4)
-
-	lis	r6,LAWAR8@h
-	ori	r6,r6,LAWAR8@l
-	stwu	r6, 0x20(r5)
-
-	/* LAWBAR9, LAWAR9 */
-	lis	r6,LAWBAR9@h
-	ori	r6,r6,LAWBAR9@l
-	stwu	r6, 0x20(r4)
-
-	lis	r6,LAWAR9@h
-	ori	r6,r6,LAWAR9@l
-	stwu	r6, 0x20(r5)
-
-	blr

board/freescale/mpc8610hpcd/law.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#if !defined(CONFIG_SPD_EEPROM)
+	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
+#endif
+	SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(8, CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
+	SET_LAW_ENTRY(9, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/mpc8610hpcd/u-boot.lds

@@ -51,7 +51,6 @@ SECTIONS
   .text :
   {
     cpu/mpc86xx/start.o	(.text)
-    board/freescale/mpc8610hpcd/init.o (.bootpg)
     cpu/mpc86xx/traps.o (.text)
     cpu/mpc86xx/interrupts.o (.text)
     cpu/mpc86xx/cpu_init.o (.text)

board/freescale/mpc8641hpcn/Makefile

@@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o
-
-SOBJS	:= init.o
+COBJS	:= $(BOARD).o law.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/freescale/mpc8641hpcn/init.S

@@ -1,179 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc86xx.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
- * 0xf800_0000     0xf80f_ffff     CCSRBAR                 1M
- * 0xf810_0000     0xf81f_ffff     PIXIS                   1M
- * 0xfe00_0000     0xffff_ffff     FLASH (boot bank)       32M
- *
- * Notes:
- *    CCSRBAR don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
-#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-#else
-#define LAWBAR1 0
-#define LAWAR1  ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
-#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-/*
- * This is not so much the SDRAM map as it is the whole localbus map.
- */
-#define LAWBAR4 ((0xf8100000>>12) & 0xffffff)
-#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
-
-#define LAWBAR5 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
-#define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
-
-#define LAWBAR6 ((CFG_PCI2_IO_PHYS>>12) & 0xffffff)
-#define LAWAR6	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
-
-#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
-#define LAWAR7	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
-#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-#else
-#define LAWBAR8 0
-#define LAWAR8  ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR9 ((CFG_RIO_MEM_PHYS>>12) & 0xfffff)
-#define LAWAR9  (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	lis	r7,CFG_CCSRBAR@h
-	ori	r7,r7,CFG_CCSRBAR@l
-
-	addi    r4,r7,0
-	addi    r5,r7,0
-
-	/* Skip LAWAR0, start at LAWAR1 */
-	lis     r6,LAWBAR1@h
-	ori     r6,r6,LAWBAR1@l
-	stwu    r6, 0xc28(r4)
-
-	lis     r6,LAWAR1@h
-	ori     r6,r6,LAWAR1@l
-	stwu    r6, 0xc30(r5)
-
-	/* LAWBAR2, LAWAR2 */
-	lis     r6,LAWBAR2@h
-	ori     r6,r6,LAWBAR2@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR2@h
-	ori     r6,r6,LAWAR2@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR3, LAWAR3 */
-	lis     r6,LAWBAR3@h
-	ori     r6,r6,LAWBAR3@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR3@h
-	ori     r6,r6,LAWAR3@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR4, LAWAR4 */
-	lis     r6,LAWBAR4@h
-	ori     r6,r6,LAWBAR4@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR4@h
-	ori     r6,r6,LAWAR4@l
-	stwu    r6, 0x20(r5)
-	/* LAWBAR5, LAWAR5 */
-	lis     r6,LAWBAR5@h
-	ori     r6,r6,LAWBAR5@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR5@h
-	ori     r6,r6,LAWAR5@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR6, LAWAR6 */
-	lis     r6,LAWBAR6@h
-	ori     r6,r6,LAWBAR6@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR6@h
-	ori     r6,r6,LAWAR6@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR7, LAWAR7 */
-	lis     r6,LAWBAR7@h
-	ori     r6,r6,LAWBAR7@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR7@h
-	ori     r6,r6,LAWAR7@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR8, LAWAR8 */
-	lis     r6,LAWBAR8@h
-	ori     r6,r6,LAWBAR8@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR8@h
-	ori     r6,r6,LAWAR8@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR9, LAWAR9 */
-	lis     r6,LAWBAR9@h
-	ori     r6,r6,LAWBAR9@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR9@h
-	ori     r6,r6,LAWAR9@l
-	stwu    r6, 0x20(r5)
-
-	blr

board/freescale/mpc8641hpcn/law.c

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf800_0000     0xf80f_ffff     CCSRBAR                 1M
+ * 0xf810_0000     0xf81f_ffff     PIXIS                   1M
+ * 0xfe00_0000     0xffff_ffff     FLASH (boot bank)       32M
+ *
+ * Notes:
+ *    CCSRBAR don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#if !defined(CONFIG_SPD_EEPROM)
+	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+#endif
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(5, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+	SET_LAW_ENTRY(6, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	SET_LAW_ENTRY(7, (CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
+#if !defined(CONFIG_SPD_EEPROM)
+	SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
+#endif
+	SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/mpc8641hpcn/u-boot.lds

@@ -51,7 +51,6 @@ SECTIONS
   .text      :
   {
     cpu/mpc86xx/start.o	(.text)
-    board/freescale/mpc8641hpcn/init.o (.bootpg)
     cpu/mpc86xx/traps.o (.text)
     cpu/mpc86xx/interrupts.o (.text)
     cpu/mpc86xx/cpu_init.o (.text)

board/idmr/mii.c

@@ -131,7 +131,7 @@ uint mii_send(uint mii_cmd)
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
 
 #if defined(CFG_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)

board/m501sk/Makefile

@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := m501sk.o eeprom.o
+
+SOBJS  := memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/m501sk/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000

board/m501sk/eeprom.c

@@ -0,0 +1,102 @@
+/*
+ * Add by Alan Lu, 07-29-2005
+ * For ATMEL AT24C16 EEPROM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#ifdef CFG_EEPROM_AT24C16
+#undef DEBUG
+
+void eeprom_init(void)
+{
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+#endif
+}
+
+int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer,
+			unsigned cnt)
+{
+	int page, count = 0, i = 0;
+	page = offset / 0x100;
+	i = offset % 0x100;
+
+	while (count < cnt) {
+		if (i2c_read(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
+			return 1;
+		if (i > 0xff) {
+			page++;
+			i = 0;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
+ *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
+ *
+ * for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
+ *   0x00000nxx for EEPROM address selectors and page number at n.
+ */
+int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer,
+			unsigned cnt)
+{
+	int page, i = 0, count = 0;
+
+	page = offset / 0x100;
+	i = offset % 0x100;
+
+	while (count < cnt) {
+		if (i2c_write(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
+			return 1;
+		if (i > 0xff) {
+			page++;
+			i = 0;
+		}
+	}
+
+#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
+	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SPI
+int eeprom_probe(unsigned dev_addr, unsigned offset)
+{
+	unsigned char chip;
+
+	/* Probe the chip address */
+#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
+	chip = offset >> 8; /* block number */
+#else
+	chip = offset >> 16; /* block number */
+#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
+
+	chip |= dev_addr; /* insert device address */
+	return (i2c_probe(chip));
+}
+#endif
+#endif

board/m501sk/m501sk.c

@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2008
+ * Based on modifications by Alan Lu / Artila
+ * Author : Timo Tuunainen / Sysart
+			Kimmo Leppala / Sysart
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+#include "m501sk.h"
+#include "net.h"
+
+#ifdef CONFIG_M501SK
+
+void m501sk_gpio_init(void)
+{
+	AT91C_BASE_PIOD->PIO_PER = 1 << (M501SK_DEBUG_LED1 - 96) |
+		1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
+		1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
+
+	AT91C_BASE_PIOD->PIO_OER = 1 << (M501SK_DEBUG_LED1 - 96) |
+		1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
+		1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
+
+	AT91C_BASE_PIOD->PIO_SODR = 1 << (M501SK_READY_LED - 96);
+	AT91C_BASE_PIOD->PIO_CODR = 1 << (M501SK_DEBUG_LED3 - 96);
+	AT91C_BASE_PIOB->PIO_PER = 1 << (M501SK_BUZZER - 32);
+	AT91C_BASE_PIOB->PIO_OER = 1 << (M501SK_BUZZER - 32);
+	AT91C_BASE_PIOC->PIO_PDR = (1 << 7) | (1 << 8);
+
+	/* Power OFF all USART's LEDs */
+	AT91C_BASE_PIOA->PIO_PER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
+		AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
+		AT91C_PA23_TXD2;
+
+	AT91C_BASE_PIOA->PIO_OER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
+		AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
+		AT91C_PA23_TXD2;
+
+	AT91C_BASE_PIOA->PIO_SODR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
+		AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
+		AT91C_PA23_TXD2;
+
+	AT91C_BASE_PIOB->PIO_PER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
+	AT91C_BASE_PIOB->PIO_OER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
+	AT91C_BASE_PIOB->PIO_SODR = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
+}
+
+uchar m501sk_gpio_set(M501SK_PIO io)
+{
+	uchar status = 0xff;
+	switch (io) {
+	case M501SK_DEBUG_LED1:
+	case M501SK_DEBUG_LED2:
+	case M501SK_DEBUG_LED3:
+	case M501SK_DEBUG_LED4:
+	case M501SK_READY_LED:
+		AT91C_BASE_PIOD->PIO_SODR = 1 << (io - 96);
+		status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
+		break;
+	case M501SK_BUZZER:
+		AT91C_BASE_PIOB->PIO_SODR = 1 << (io - 32);
+		status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
+		break;
+	}
+	return status;
+}
+
+uchar m501sk_gpio_clear(M501SK_PIO io)
+{
+	uchar status = 0xff;
+	switch (io) {
+	case M501SK_DEBUG_LED1:
+	case M501SK_DEBUG_LED2:
+	case M501SK_DEBUG_LED3:
+	case M501SK_DEBUG_LED4:
+	case M501SK_READY_LED:
+		AT91C_BASE_PIOD->PIO_CODR = 1 << (io - 96);
+		status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
+		break;
+	case M501SK_BUZZER:
+		AT91C_BASE_PIOB->PIO_CODR = 1 << (io - 32);
+		status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
+		break;
+	}
+	return status;
+}
+
+void load_sernum_ethaddr(void)
+{
+	return;
+}
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* Correct IRDA resistor problem */
+	/* Set PA23_TXD in Output */
+	((AT91PS_PIO)AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+	gd->bd->bi_arch_number = MACH_TYPE_M501;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	m501sk_gpio_init();
+
+	/* Do interrupt init here, because flash needs timers */
+	interrupt_init();
+	flash_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	int i = 0;
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	for (i = 0; i < 500; i++) {
+		m501sk_gpio_clear(M501SK_DEBUG_LED3);
+		m501sk_gpio_clear(M501SK_BUZZER);
+		udelay(250);
+		m501sk_gpio_set(M501SK_DEBUG_LED3);
+		m501sk_gpio_set(M501SK_BUZZER);
+		udelay(80);
+	}
+	m501sk_gpio_clear(M501SK_BUZZER);
+	m501sk_gpio_clear(M501SK_DEBUG_LED3);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_CMD_NET)
+	eth_init(gd->bd);
+	eth_halt();
+#endif
+
+	/* Protect U-Boot, kernel & ramdisk memory addresses */
+	run_command("protect on 10000000 1041ffff", 0);
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if defined(CONFIG_CMD_NET)
+/*
+ * Name:
+ *     at91rm9200_GetPhyInterface
+ * Description:
+ *     Initialise the interface functions to the PHY
+ * Arguments:
+ *     None
+ * Return value:
+ *     None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
+#endif /* CONFIG_M501SK */

board/m501sk/m501sk.h

@@ -0,0 +1,167 @@
+/*
+ * linux/include/asm-arm/arch-at91/hardware.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __M501SK_H
+#define __M501SK_H
+
+#ifndef __ASSEMBLY__
+#include <asm-arm/arch-at91rm9200/AT91RM9200.h>
+#else
+#include <asm-arm/arch-at91rm9200/AT91RM9200_inc.h>
+#endif
+
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */
+#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) /* USART 2 RxD */
+#define AT91C_PA5_TXD3 ((unsigned int) 1 <<  5) /* USART 3 TxD */
+#define AT91C_PA6_RXD3 ((unsigned int) 1 << 6) /* USART 3 RxD */
+
+/* ========== Register definition for PIOD peripheral ========== */
+#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) /* Pin Data stat Reg */
+#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) /* Clear Output Data Reg */
+#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) /* Output Write Enable Reg */
+#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) /* Multi-driver Enable Reg */
+#define AT91C_PIOD_IMR  ((AT91_REG *) 0xFFFFFA48) /* Interrupt Mask Reg */
+#define AT91C_PIOD_IER  ((AT91_REG *) 0xFFFFFA40) /* Interrupt Enable Reg */
+#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) /* Output Data stat Reg */
+#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) /* Set Output Data Reg */
+#define AT91C_PIOD_PER  ((AT91_REG *) 0xFFFFFA00) /* PIO Enable Reg */
+#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) /* Output Write Disable Reg */
+#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) /* Pull-up Enable Reg */
+#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) /* Multi-driver Disable Reg */
+#define AT91C_PIOD_ISR  ((AT91_REG *) 0xFFFFFA4C) /* Interrupt stat Reg */
+#define AT91C_PIOD_IDR  ((AT91_REG *) 0xFFFFFA44) /* Interrupt Disable Reg */
+#define AT91C_PIOD_PDR  ((AT91_REG *) 0xFFFFFA04) /* PIO Disable Reg */
+#define AT91C_PIOD_ODR  ((AT91_REG *) 0xFFFFFA14) /* Output Disable Regr */
+#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) /* Output Write stat Reg */
+#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) /* AB Select stat Reg */
+#define AT91C_PIOD_ASR  ((AT91_REG *) 0xFFFFFA70) /* Select A Reg */
+#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) /* Pad Pull-up stat Reg */
+#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) /* Pull-up Disable Reg */
+#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) /* Multi-driver stat Reg */
+#define AT91C_PIOD_PSR  ((AT91_REG *) 0xFFFFFA08) /* PIO stat Reg */
+#define AT91C_PIOD_OER  ((AT91_REG *) 0xFFFFFA10) /* Output Enable Reg */
+#define AT91C_PIOD_OSR  ((AT91_REG *) 0xFFFFFA18) /* Output stat Reg */
+#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) /* Input Filter Enable Reg */
+#define AT91C_PIOD_BSR  ((AT91_REG *) 0xFFFFFA74) /* Select B Reg */
+#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) /* Input Filter Disable Reg */
+#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) /* Input Filter stat Reg */
+
+#define AT91C_PIO_PD0   ((unsigned int) 1 <<  0) /* Pin Controlled by PD0 */
+#define AT91C_PD0_ETX0  ((unsigned int) AT91C_PIO_PD0) /*  Enet MAC Tx Data 0*/
+#define AT91C_PIO_PD1   ((unsigned int) 1 <<  1) /* Pin Controlled by PD1 */
+#define AT91C_PD1_ETX1  ((unsigned int) AT91C_PIO_PD1) /*  Enet MAC Tx Data 1*/
+#define AT91C_PIO_PD10  ((unsigned int) 1 << 10) /* Pin Controlled by PD10 */
+#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) /* PMC Prog Clk Oput 3*/
+#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) /* ETMARM9 pl stat1 */
+#define AT91C_PIO_PD11  ((unsigned int) 1 << 11) /* Pin Controlled by PD11 */
+#define AT91C_PD11_     ((unsigned int) AT91C_PIO_PD11) /*   */
+#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) /* ETMARM9 pl stat2 */
+#define AT91C_PIO_PD12  ((unsigned int) 1 << 12) /* Pin Controlled by PD12 */
+#define AT91C_PD12_     ((unsigned int) AT91C_PIO_PD12) /*   */
+#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) /* ETM Trace Pkt 0 */
+#define AT91C_PIO_PD13  ((unsigned int) 1 << 13) /* Pin Controlled by PD13 */
+#define AT91C_PD13_     ((unsigned int) AT91C_PIO_PD13) /*   */
+#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) /* ETM Trace Pkt 1 */
+#define AT91C_PIO_PD14  ((unsigned int) 1 << 14) /* Pin Controlled by PD14 */
+#define AT91C_PD14_     ((unsigned int) AT91C_PIO_PD14) /*   */
+#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) /* ETM Trace Pkt 2 */
+#define AT91C_PIO_PD15  ((unsigned int) 1 << 15) /* Pin Controlled by PD15 */
+#define AT91C_PD15_TD0  ((unsigned int) AT91C_PIO_PD15) /* SSC TxD */
+#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) /* ETM Trace Pkt 3 */
+#define AT91C_PIO_PD16  ((unsigned int) 1 << 16) /* Pin Controlled by PD16 */
+#define AT91C_PD16_TD1  ((unsigned int) AT91C_PIO_PD16) /* SSC TxD 1 */
+#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) /* ETM Trace Pkt 4 */
+#define AT91C_PIO_PD17  ((unsigned int) 1 << 17) /* Pin Controlled by PD17 */
+#define AT91C_PD17_TD2  ((unsigned int) AT91C_PIO_PD17) /* SSC TxD 2 */
+#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) /* ETM Trace Pkt 5 */
+#define AT91C_PIO_PD18  ((unsigned int) 1 << 18) /* Pin Controlled by PD18 */
+#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) /*  SPI Perip CS 1 */
+#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) /* ETM Trace Pkt 6 */
+#define AT91C_PIO_PD19  ((unsigned int) 1 << 19) /* Pin Controlled by PD19 */
+#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) /*  SPI Perip CS 2 */
+#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) /* ETM Trace Pkt 7 */
+#define AT91C_PIO_PD2   ((unsigned int) 1 <<  2) /* Pin Controlled by PD2 */
+#define AT91C_PD2_ETX2  ((unsigned int) AT91C_PIO_PD2) /*  Ethernet MAC TxD 2 */
+#define AT91C_PIO_PD20  ((unsigned int) 1 << 20) /* Pin Controlled by PD20 */
+#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) /* SPI Perip CS 3 */
+#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) /* ETM Trace Pkt 8 */
+#define AT91C_PIO_PD21  ((unsigned int) 1 << 21) /* Pin Controlled by PD21 */
+#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) /* Usart 0 RTS */
+#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) /* ETM Trace Pkt 9 */
+#define AT91C_PIO_PD22  ((unsigned int) 1 << 22) /* Pin Controlled by PD22 */
+#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) /*  Usart 0 RTS */
+#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) /* ETM Trace Pkt 10 */
+#define AT91C_PIO_PD23  ((unsigned int) 1 << 23) /* Pin Controlled by PD23 */
+#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) /* USART 2 RTS */
+#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) /* ETM Trace Pkt 11 */
+#define AT91C_PIO_PD24  ((unsigned int) 1 << 24) /* Pin Controlled by PD24 */
+#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) /*  USART 3 RTS */
+#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) /* ETM Trace Pkt 12 */
+#define AT91C_PIO_PD25  ((unsigned int) 1 << 25) /* Pin Controlled by PD25 */
+#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) /* USART 1 DTR */
+#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) /* ETM Trace Pkt 13 */
+#define AT91C_PIO_PD26  ((unsigned int) 1 << 26) /* Pin Controlled by PD26 */
+#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) /* ETM Trace Pkt 14 */
+#define AT91C_PIO_PD27  ((unsigned int) 1 << 27) /* Pin Controlled by PD27 */
+#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) /* ETM Trace Pkt 15 */
+#define AT91C_PIO_PD3   ((unsigned int) 1 <<  3) /* Pin Controlled by PD3 */
+#define AT91C_PD3_ETX3  ((unsigned int) AT91C_PIO_PD3) /*  Enet MAC TxD 3 */
+#define AT91C_PIO_PD4   ((unsigned int) 1 <<  4) /* Pin Controlled by PD4 */
+#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) /* Enet MAC TxEn */
+#define AT91C_PIO_PD5   ((unsigned int) 1 <<  5) /* Pin Controlled by PD5 */
+#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) /*  Enet MAC TxCE */
+#define AT91C_PIO_PD6   ((unsigned int) 1 <<  6) /* Pin Controlled by PD6 */
+#define AT91C_PD6_DTXD  ((unsigned int) AT91C_PIO_PD6) /* DBGU Debug TxD */
+#define AT91C_PIO_PD7   ((unsigned int) 1 <<  7) /* Pin Controlled by PD7 */
+#define AT91C_PD7_PCK0  ((unsigned int) AT91C_PIO_PD7) /* PMC Prog Clk Oput 0*/
+#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) /* ETM Sync signal */
+#define AT91C_PIO_PD8   ((unsigned int) 1 <<  8) /* Pin Controlled by PD8 */
+#define AT91C_PD8_PCK1  ((unsigned int) AT91C_PIO_PD8) /* PMC Prog Clk Oput 1*/
+#define AT91C_PD8_TCLK  ((unsigned int) AT91C_PIO_PD8) /* ETM Trace Clk sig */
+#define AT91C_PIO_PD9   ((unsigned int) 1 <<  9) /* Pin Controlled by PD9 */
+#define AT91C_PD9_PCK2  ((unsigned int) AT91C_PIO_PD9) /* PMC Prog Clk 2 */
+#define AT91C_PD9_TPS0  ((unsigned int) AT91C_PIO_PD9) /* ETM ARM9 pl stat0 */
+#define AT91C_PIO_PB6   ((unsigned int) 1 <<  6) /* Pin Controlled by PB6 */
+#define AT91C_PIO_PC5   ((unsigned int) 1 <<  5)
+#define AT91C_PIO_PC14  ((unsigned int) 1 <<  14) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PC15  ((unsigned int) 1 <<  15) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PA19  ((unsigned int) 1 <<  19) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PB2   ((unsigned int) 1 <<  2) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PB8   ((unsigned int) 1 <<  8)
+#define AT91C_PIO_PB9   ((unsigned int) 1 <<  9)
+#define AT91C_PIO_PB10  ((unsigned int) 1 <<  10)
+#define AT91C_PIO_PB11  ((unsigned int) 1 <<  11)
+#define AT91C_PIO_PB17  ((unsigned int) 1 <<  17)
+#define AT91C_PIO_PB28  ((unsigned int) 1 <<  28)
+#define AT91C_PIO_PB29  ((unsigned int) 1 <<  29)
+
+typedef enum {
+	M501SK_BUZZER = 38,
+	M501SK_DEBUG_LED1 = 96,
+	M501SK_DEBUG_LED2,
+	M501SK_DEBUG_LED3,
+	M501SK_DEBUG_LED4,
+	M501SK_READY_LED = 102,
+} M501SK_PIO;
+
+void m501sk_gpio_init(void);
+uchar m501sk_gpio_set(M501SK_PIO io);
+uchar m501sk_gpio_clear(M501SK_PIO io);
+
+#endif

board/m501sk/memsetup.S

@@ -0,0 +1,200 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *	          Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifdef CONFIG_BOOTBINFUNC
+/*
+ * some parameters for the board
+ *
+ * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
+ * turn is based on the boot.bin code from ATMEL
+ *
+ */
+
+/* flash */
+#define MC_PUIA 0xFFFFFF10
+#define MC_PUIA_VAL 0x00000000
+#define MC_PUP 0xFFFFFF50
+#define MC_PUP_VAL 0x00000000
+#define MC_PUER 0xFFFFFF54
+#define MC_PUER_VAL 0x00000000
+#define MC_ASR 0xFFFFFF04
+#define MC_ASR_VAL 0x00000000
+#define MC_AASR 0xFFFFFF08
+#define MC_AASR_VAL 0x00000000
+#define EBI_CFGR 0xFFFFFF64
+#define EBI_CFGR_VAL 0x00000000
+#define SMC2_CSR 0xFFFFFF70
+#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR 0xFFFFFC28
+#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
+#define PLLBR 0xFFFFFC2C
+#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR 0xFFFFFC30
+/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define MCKR_VAL	0x00000202
+
+/* sdram */
+#define PIOC_ASR 0xFFFFF870
+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
+#define PIOC_BSR 0xFFFFF874
+#define PIOC_BSR_VAL 0x00000000
+#define PIOC_PDR 0xFFFFF804
+#define PIOC_PDR_VAL 0xFFFF0000
+#define EBI_CSA 0xFFFFFF60
+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define SDRC_CR 0xFFFFFF98
+#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
+#define SDRAM 0x20000000 /* address of the SDRAM */
+#define SDRAM1 0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define SDRC_MR 0xFFFFFF90
+#define SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1 0x00000004 /* refresh */
+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define SDRC_TR 0xFFFFFF94
+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+
+_TEXT_BASE:
+	.word   TEXT_BASE
+
+.globl lowlevelinit
+lowlevelinit:
+	/* memory control configuration */
+	/* this isn't very elegant, but  what the heck */
+	ldr     r0, =SMRDATA
+	ldr     r1, _TEXT_BASE
+	sub     r0, r0, r1
+	add     r2, r0, #80
+0:
+	/* the address */
+	ldr     r1, [r0], #4
+	/* the value */
+	ldr     r3, [r0], #4
+	str     r3, [r1]
+	cmp     r2, r0
+	bne     0b
+	/* delay - this is all done by guess */
+	ldr     r0, =0x00010000
+1:
+	subs    r0, r0, #1
+	bhi     1b
+	ldr     r0, =SMRDATA1
+	ldr     r1, _TEXT_BASE
+	sub     r0, r0, r1
+	add     r2, r0, #176
+2:
+	/* the address */
+	ldr     r1, [r0], #4
+	/* the value */
+	ldr     r3, [r0], #4
+	str     r3, [r1]
+	cmp     r2, r0
+	bne     2b
+
+	/* everything is fine now */
+	mov     pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word MC_PUIA
+	.word MC_PUIA_VAL
+	.word MC_PUP
+	.word MC_PUP_VAL
+	.word MC_PUER
+	.word MC_PUER_VAL
+	.word MC_ASR
+	.word MC_ASR_VAL
+	.word MC_AASR
+	.word MC_AASR_VAL
+	.word EBI_CFGR
+	.word EBI_CFGR_VAL
+	.word SMC2_CSR
+	.word SMC2_CSR_VAL
+	.word PLLAR
+	.word PLLAR_VAL
+	.word PLLBR
+	.word PLLBR_VAL
+	.word MCKR
+	.word MCKR_VAL
+	/* SMRDATA is 80 bytes long */
+	/* here there's a delay of 100 */
+SMRDATA1:
+	.word PIOC_ASR
+	.word PIOC_ASR_VAL
+	.word PIOC_BSR
+	.word PIOC_BSR_VAL
+	.word PIOC_PDR
+	.word PIOC_PDR_VAL
+	.word EBI_CSA
+	.word EBI_CSA_VAL
+	.word SDRC_CR
+	.word SDRC_CR_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL1
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL2
+	.word SDRAM1
+	.word SDRAM_VAL
+	.word SDRC_TR
+	.word SDRC_TR_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL3
+	.word SDRAM
+	.word SDRAM_VAL
+	/* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_BOOTBINFUNC */

include/asm-blackfin/segment.h → board/m501sk/u-boot.lds

@@ -1,7 +1,6 @@
 /*
- * U-boot - segment.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -18,29 +17,39 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
  */
 
-#ifndef _BLACKFIN_SEGMENT_H
-#define _BLACKFIN_SEGMENT_H
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	 cpu/arm920t/start.o   (.text)
+	 *(.text)
+	}
 
-/* define constants */
-typedef unsigned long mm_segment_t;	/* domain register */
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
 
-#define KERNEL_CS		0x0
-#define KERNEL_DS		0x0
-#define __KERNEL_CS		0x0
-#define __KERNEL_DS		0x0
+	. = ALIGN(4);
+	.data : { *(.data) }
 
-#define USER_CS			0x1
-#define USER_DS			0x1
-#define __USER_CS		0x1
-#define __USER_DS		0x1
+	. = ALIGN(4);
+	.got : { *(.got) }
 
-#define get_ds()		(KERNEL_DS)
-#define get_fs()		(__USER_DS)
-#define segment_eq(a,b)		((a) == (b))
-#define set_fs(val)
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
-#endif
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/m5271evb/mii.c

@@ -131,7 +131,7 @@ uint mii_send(uint mii_cmd)
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
 
 #if defined(CFG_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)

board/m5272c3/mii.c

@@ -131,7 +131,7 @@ uint mii_send(uint mii_cmd)
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
 
 #if defined(CFG_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)

board/m5282evb/mii.c

@@ -132,7 +132,7 @@ uint mii_send(uint mii_cmd)
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
 
 #if defined(CFG_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)

board/netstal/common/fixed_sdram.c

@@ -44,7 +44,7 @@ void show_sdram_registers(void)
 }
 #endif
 
-long int fixed_hcu4_sdram (unsigned int dram_size)
+long int init_ppc405_sdram(unsigned int dram_size)
 {
 #ifdef DEBUG
 	printf(__FUNCTION__);

board/netstal/common/hcu_flash.c

@@ -21,18 +21,6 @@
  * MA 02111-1307 USA
  */
 
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- *
- * Modified 6/6/2007
- * Added isync
- * Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com
- *
- */
-
 #include <common.h>
 #include <ppc4xx.h>
 #include <asm/processor.h>
@@ -387,7 +375,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	/* wait at least 80us - let's wait 1 ms */
 	udelay (1000);
 
-#if 0
 	/*
 	 * We wait for the last triggered sector
 	 */
@@ -396,7 +383,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	wait_for_DQ7 (info, l_sect);
 
 DONE:
-#endif
 	/* reset to read mode */
 	addr = (FLASH_WORD_SIZE *) info->start[0];
 	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */

board/netstal/common/nm.h

@@ -27,8 +27,7 @@ extern void set_params_for_sw_install(int install_requested, char *board_name );
 extern void common_misc_init_r(void);
 
 enum {
-	/* HW_GENERATION_HCU1 is no longer supported */
-	HW_GENERATION_HCU2  = 0x10,
+	/* HW_GENERATION_HCU1/2 is no longer supported */
 	HW_GENERATION_HCU3  = 0x10,
 	HW_GENERATION_HCU4  = 0x20,
 	HW_GENERATION_HCU5  = 0x30,
@@ -36,3 +35,11 @@ enum {
 	HW_GENERATION_MCU20 = 0x0a,
 	HW_GENERATION_MCU25 = 0x09,
 };
+
+#ifdef CONFIG_405GP
+#if defined(DEBUG)
+void show_sdram_registers(void);
+#endif
+long int init_ppc405_sdram(unsigned int dram_size);
+#endif
+

board/netstal/common/nm_bsp.c

@@ -29,8 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 typedef struct {u8	id;	char *name;} generation_info;
 
-generation_info generations[7] = {
-	{HW_GENERATION_HCU2,	"HCU2"},
+generation_info generations[6] = {
 	{HW_GENERATION_HCU3,	"HCU3"},
 	{HW_GENERATION_HCU4,	"HCU4"},
 	{HW_GENERATION_HCU5,	"HCU5"},
@@ -134,3 +133,4 @@ void common_misc_init_r(void)
 		saveenv();
 	}
 }
+

board/netstal/hcu4/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2007 Netstal Maschinen AG
+# (C) Copyright 2007-2008 Netstal Maschinen AG
 # Niklaus Giger (ng@netstal.com)
 #
 # This program is free software; you can redistribute it and/or
@@ -22,18 +22,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-vpath fixed_sdram.c ../common
-vpath hcu_flash.c ../common
-vpath nm_bsp.c ../common
-
 # NOBJS : Netstal common objects
-NOBJS	= ../common/fixed_sdram.o ../common/hcu_flash.o ../common/nm_bsp.o
+NOBJS	= fixed_sdram.o hcu_flash.o nm_bsp.o
 COBJS	= $(BOARD).o
 SOBJS	=
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(NOBJS:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(COBJS))
-NOBJS	:= $(addprefix $(obj),$(NOBJS))
+NOBJS	:= $(addprefix $(obj)../common/,$(NOBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(OBJS) $(SOBJS) $(NOBJS)

board/netstal/hcu4/hcu4.c

@@ -1,5 +1,5 @@
 /*
- *(C) Copyright 2005-2007 Netstal Maschinen AG
+ *(C) Copyright 2005-2008 Netstal Maschinen AG
  *    Niklaus Giger (Niklaus.Giger@netstal.com)
  *
  *    This source code is free software; you can redistribute it
@@ -28,17 +28,10 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define HCU_MACH_VERSIONS_REGISTER	(0x7C000000 + 0xF00000)
-#define SYS_SLOT_ADDRESS		(0x7C000000 + 0x400000)
-#define HCU3_DIGITAL_IO_REGISTER	(0x7C000000 + 0x500000)
+#define HCU_SLOT_ADDRESS		(0x7C000000 + 0x400000)
+#define HCU_DIGITAL_IO_REGISTER		(0x7C000000 + 0x500000)
 #define HCU_SW_INSTALL_REQUESTED	0x10
 
-#undef DEBUG
-
-#if defined(DEBUG)
-void show_sdram_registers(void);
-#endif
-long int fixed_hcu4_sdram (unsigned int dram_size);
-
 /*
  * This function is run very early, out of flash, and before devices are
  * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
@@ -49,17 +42,12 @@ long int fixed_hcu4_sdram (unsigned int dram_size);
  * anything, not even stack. So be careful.
  */
 
-#define CPC0_CR0	0xb1	/* Chip control register 0 */
-#define CPC0_CR1        0xb2	/* Chip control register 1 */
 /* Attention: If you want 1 microsecs times from the external oscillator
- * use  0x00804051. But this causes problems with u-boot and linux!
+ * 0x00004051 is okay for u-boot/linux, but different from old vxworks values
+ * 0x00804051 causes problems with u-boot and linux!
  */
 #define CPC0_CR0_VALUE	0x0030103c
 #define CPC0_CR1_VALUE	0x00004051
-#define CPC0_ECR	0xaa	/* Edge condition register */
-#define EBC0_CFG	0x23	/* External Peripheral Control Register */
-#define CPC0_EIRR	0xb6	/* External Interrupt Register */
-
 
 int board_early_init_f (void)
 {
@@ -70,16 +58,16 @@ int board_early_init_f (void)
 	 *      IRQ 17-24 RESERVED/UNUSED
 	 *      IRQ 31 (EXT IRQ 6) (unused)
 	 */
-	mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
-	mtdcr (uicer, 0x00000000); /* disable all ints */
-	mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFE000); /* set int polarities */
-	mtdcr (uictr, 0x00000000); /* set int trigger levels */
-	mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(uicer, 0x00000000); /* disable all ints */
+	mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
+	mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
+	mtdcr(uictr, 0x00000000); /* set int trigger levels */
+	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
 
-	mtdcr(CPC0_CR1,  CPC0_CR1_VALUE);
-	mtdcr(CPC0_ECR,  0x60606000);
-	mtdcr(CPC0_EIRR, 0x7c000000);
+	mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
+	mtdcr(CPC0_ECR, 0x60606000);
+	mtdcr(CPC0_EIRR, 0x7C000000);
 
 	return 0;
 }
@@ -93,18 +81,19 @@ int board_pre_init (void)
 
 int sys_install_requested(void)
 {
-	u16 *ioValuePtr = (u16 *)HCU3_DIGITAL_IO_REGISTER;
-	return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
+	u16 ioValue = in_be16((u16 *)HCU_DIGITAL_IO_REGISTER);
+	return (ioValue & HCU_SW_INSTALL_REQUESTED) != 0;
 }
 
 int checkboard (void)
 {
-	u16 *boardVersReg = (u16 *)HCU_MACH_VERSIONS_REGISTER;
-	u16 generation = in_be16(boardVersReg) & 0xf0;
-	u16 index      = in_be16(boardVersReg) & 0x0f;
+	u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
+	u16 generation = boardVersReg & 0xf0;
+	u16 index      = boardVersReg & 0x0f;
+
+	/* Cannot be done in board_early_init */
+	mtdcr(cntrl0,  CPC0_CR0_VALUE);
 
-	/* Cannot be done, in board_early_init */
-	mtdcr(CPC0_CR0,  CPC0_CR0_VALUE);
 	/* Force /RTS to active. The board it not wired quite
 	 *  correctly to use cts/rtc flow control, so just force the
 	 *  /RST active and forget about it.
@@ -145,8 +134,8 @@ void sdram_init(void)
  */
 u32 hcu_get_slot(void)
 {
-	u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
-	return in_be16(slot) & 0x7f;
+	u16 slot = in_be16((u16 *)HCU_SLOT_ADDRESS);
+	return slot & 0x7f;
 }
 
 /*
@@ -154,12 +143,12 @@ u32 hcu_get_slot(void)
  */
 u32 get_serial_number(void)
 {
-	u32 *serial = (u32 *)CFG_FLASH_BASE;
+	u32 serial = in_be32((u32 *)CFG_FLASH_BASE);
 
-	if (in_be32(serial) == 0xffffffff)
+	if (serial == 0xffffffff)
 		return 0;
 
-	return in_be32(serial);
+	return serial;
 }
 
 
@@ -177,12 +166,15 @@ int misc_init_r(void)
 long int initdram(int board_type)
 {
 	long dram_size = 0;
-	u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER;
-	u16 generation = in_be16(boardVersReg) & 0xf0;
-	if (generation == HW_GENERATION_HCU3)
-		dram_size = 32*1024*1024;
-	else dram_size = 64*1024*1024;
-	fixed_hcu4_sdram(dram_size);
+	u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
+	u16 generation = boardVersReg & 0xf0;
+	u16 index      = boardVersReg & 0x0f;
+
+	if (generation == HW_GENERATION_HCU3 && index < 0xf)
+		dram_size = 32 << 20;	/* 32 MB - RAM */
+	else
+		dram_size = 64 << 20;	/* 64 MB - RAM */
+	init_ppc405_sdram(dram_size);
 
 #ifdef DEBUG
 	show_sdram_registers();

board/netstal/hcu5/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2007 Netstal Maschinen AG
+# (C) Copyright 2007-2008 Netstal Maschinen AG
 # Niklaus Giger (ng@netstal.com)
 #
 # This program is free software; you can redistribute it and/or
@@ -22,17 +22,15 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-vpath hcu_flash.c ../common
-vpath nm_bsp.c ../common
 
 # NOBJS : Netstal common objects
-NOBJS	= ../common/hcu_flash.o ../common/nm_bsp.o
+NOBJS	= hcu_flash.o nm_bsp.o
 COBJS	= $(BOARD).o sdram.o
 SOBJS	= init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(NOBJS:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(COBJS))
-NOBJS	:= $(addprefix $(obj),$(NOBJS))
+NOBJS	:= $(addprefix $(obj)../common/,$(NOBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(OBJS) $(SOBJS) $(NOBJS)

board/netstal/hcu5/hcu5.c

@@ -309,15 +309,13 @@ int misc_init_r(void)
 	 */
 	if (mfspr(dbcr0) & 0x80000000) {
 		/* External debugger alive
-		 * enable trace facilty for Lauterback
-		 * CCR0[DAPUIB]=0 	Enable broadcast of instruction data
-		 *			to auxiliary processor interface
+		 * enable trace facilty for Lauterbach
 		 * CCR0[DTB]=0 		Enable broadcast of trace information
 		 * SDR0_PFC0[TRE] 	Trace signals are enabled instead of
 		 *			GPIO49-63
 		 */
-		mtspr(ccr0, mfspr(ccr0)  &~ 0x00108000);
-		mtsdr(SDR0_PFC0, sdr0_pfc1 | 0x00000100);
+	        mtspr(ccr0, mfspr(ccr0)  &~ (CCR0_DTB));
+		mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
 	}
 	return 0;
 }

board/netstal/hcu5/sdram.c

@@ -165,19 +165,25 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
 	u32 val;
 	char str[] = "ECC generation -";
 #if defined(CONFIG_PRAM)
-	u32 *magic;
-
-	/* Check whether vxWorks is using EDR logging, if yes zero */
-	/* also PostMortem and user reserved memory */
-	magic = (u32 *)in_be32((u32 *)(start_address + num_bytes -
-				       (CONFIG_PRAM*1024) + sizeof(u32)));
-
-	debug("\n%s:  CONFIG_PRAM %d kB magic 0x%x 0x%p -> 0x%x\n", __FUNCTION__,
-	       CONFIG_PRAM,
-	       start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32),
-	       magic, in_be32(magic));
-	if (in_be32(magic) == 0xbeefbabe)
-		num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
+	u32 *magicPtr;
+	u32 magic;
+
+	if ((mfspr(dbcr0) & 0x80000000) == 0) {
+		/* only if no external debugger is alive!
+		 * Check whether vxWorks is using EDR logging, if yes zero
+		 * also PostMortem and user reserved memory
+		 */
+		magicPtr = (u32 *)(start_address + num_bytes -
+				(CONFIG_PRAM*1024) + sizeof(u32));
+		magic = in_be32(magicPtr);
+		debug("%s:  CONFIG_PRAM %d kB magic 0x%x 0x%p\n",
+		      __FUNCTION__, CONFIG_PRAM,
+		      magicPtr, magic);
+		if (magic == 0xbeefbabe) {
+			printf("%s: preserving at %p\n", __FUNCTION__, magicPtr);
+			num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
+		}
+	}
 #endif
 
 	sync();

board/netstar/nand.c

@@ -45,23 +45,12 @@ static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd)
 	this->IO_ADDR_W = (void *) IO_ADDR_W;
 }
 
-/*
- *	chip R/B detection
- */
-/***
-static int netstar_nand_ready(struct mtd_info *mtd)
-{
-	return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02;
-}
-***/
-
 int board_nand_init(struct nand_chip *nand)
 {
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	nand->eccmode = NAND_ECC_SOFT;
 	nand->hwcontrol = netstar_nand_hwcontrol;
-/*	nand->dev_ready = netstar_nand_ready; */
-	nand->chip_delay = 18;
+	nand->chip_delay = 400;
 	return 0;
 }
 #endif

board/pcs440ep/pcs440ep.c

@@ -175,7 +175,7 @@ int board_early_init_f(void)
 	 *-------------------------------------------------------------------*/
 	mfsdr(sdr_pci0, reg);
 	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
-	mtsdr(sdr_pfc0, 0x00000100);	/* Pin function: enable GPIO49-63 */
+	mtsdr(sdr_pfc0, 0x00000000);	/* Pin function: enable GPIO49-63 */
 	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins, select IRQ5 */
 
 	return 0;

board/sbc8641d/Makefile

@@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o
-SOBJS	:= init.o
+COBJS	:= $(BOARD).o law.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/sbc8641d/init.S

@@ -1,192 +0,0 @@
-/*
- * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
- * Copyright 2007 Embedded Specialties, Inc.
- * Joe Hamman joe.hamman@embeddedspecialties.com
- *
- * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc86xx.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000	0x0fff_ffff	DDR1	256M
- * 0x1000_0000	0x1fff_ffff	DDR2	256M
- * 0xe000_0000	0xffff_ffff	LBC	512M
- *
- * Notes:
- *   CCSRBAR doesn't need a configured Local Access Window.
- *   If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-# DDR Bank 1
-# #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
-# #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-# DDR Bank 2
-# #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
-# #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-# LBC
-# #define LAWBAR3 ((0xe0000000>>12) & 0xffffff)
-# #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)))
-
-/*
- * LAW (Local Access Window) configuration:
- *
- * 0x0000_0000	DDR			256M
- * 0x1000_0000	DDR2			256M
- * 0x8000_0000	PCI1 MEM		512M
- * 0xa000_0000	PCI2 MEM		512M
- * 0xc000_0000	RapidIO			512M
- * 0xe200_0000	PCI1 IO			16M
- * 0xe300_0000	PCI2 IO			16M
- * 0xf800_0000	CCSRBAR			2M
- * 0xfe00_0000	FLASH (boot bank)	32M
- *
- */
-
-#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
-#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
-#define LAWAR3	(~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
-
-#define LAWBAR4 ((0xf8000000>>12) & 0xffffff)
-#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
-
-#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
-#define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
-
-#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
-#define LAWAR6	(~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
-
-#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
-#define LAWAR7	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
-
-#define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
-#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR9  (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	lis	r7,CFG_CCSRBAR@h
-	ori	r7,r7,CFG_CCSRBAR@l
-
-	addi    r4,r7,0
-	addi    r5,r7,0
-
-	/* Skip LAWAR0, start at LAWAR1 */
-	lis     r6,LAWBAR1@h
-	ori     r6,r6,LAWBAR1@l
-	stwu    r6, 0xc28(r4)
-
-	lis     r6,LAWAR1@h
-	ori     r6,r6,LAWAR1@l
-	stwu    r6, 0xc30(r5)
-
-	/* LAWBAR2, LAWAR2 */
-	lis     r6,LAWBAR2@h
-	ori     r6,r6,LAWBAR2@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR2@h
-	ori     r6,r6,LAWAR2@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR3, LAWAR3 */
-	lis     r6,LAWBAR3@h
-	ori     r6,r6,LAWBAR3@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR3@h
-	ori     r6,r6,LAWAR3@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR4, LAWAR4 */
-	lis     r6,LAWBAR4@h
-	ori     r6,r6,LAWBAR4@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR4@h
-	ori     r6,r6,LAWAR4@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR5, LAWAR5 */
-	lis     r6,LAWBAR5@h
-	ori     r6,r6,LAWBAR5@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR5@h
-	ori     r6,r6,LAWAR5@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR6, LAWAR6 */
-	lis     r6,LAWBAR6@h
-	ori     r6,r6,LAWBAR6@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR6@h
-	ori     r6,r6,LAWAR6@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR7, LAWAR7 */
-	lis     r6,LAWBAR7@h
-	ori     r6,r6,LAWBAR7@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR7@h
-	ori     r6,r6,LAWAR7@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR8, LAWAR8 */
-	lis     r6,LAWBAR8@h
-	ori     r6,r6,LAWBAR8@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR8@h
-	ori     r6,r6,LAWAR8@l
-	stwu    r6, 0x20(r5)
-
-	/* LAWBAR9, LAWAR9 */
-	lis     r6,LAWBAR9@h
-	ori     r6,r6,LAWBAR9@l
-	stwu    r6, 0x20(r4)
-
-	lis     r6,LAWAR9@h
-	ori     r6,r6,LAWAR9@l
-	stwu    r6, 0x20(r5)
-
-	blr

board/sbc8641d/law.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW (Local Access Window) configuration:
+ *
+ * 0x0000_0000	DDR			256M
+ * 0x1000_0000	DDR2			256M
+ * 0x8000_0000	PCI1 MEM		512M
+ * 0xa000_0000	PCI2 MEM		512M
+ * 0xc000_0000	RapidIO			512M
+ * 0xe200_0000	PCI1 IO			16M
+ * 0xe300_0000	PCI2 IO			16M
+ * 0xf800_0000	CCSRBAR			2M
+ * 0xfe00_0000	FLASH (boot bank)	32M
+ *
+ */
+
+
+struct law_entry law_table[] = {
+	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW_ENTRY(4, 0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(5, CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+	SET_LAW_ENTRY(6, CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	SET_LAW_ENTRY(7, 0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
+	SET_LAW_ENTRY(9, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

board/sbc8641d/u-boot.lds

@@ -51,7 +51,6 @@ SECTIONS
   .text      :
   {
     cpu/mpc86xx/start.o	(.text)
-    board/sbc8641d/init.o (.bootpg)
     cpu/mpc86xx/traps.o (.text)
     cpu/mpc86xx/interrupts.o (.text)
     cpu/mpc86xx/cpu_init.o (.text)

common/Makefile

@@ -78,6 +78,7 @@ COBJS-y += cmd_nand.o
 COBJS-$(CONFIG_CMD_NET) += cmd_net.o
 COBJS-y += cmd_nvedit.o
 COBJS-y += cmd_onenand.o
+COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o
 ifdef CONFIG_PCI
 COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o
 endif
@@ -88,6 +89,7 @@ COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
 COBJS-y += cmd_sata.o
 COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
 COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o
+COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o
 COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
 COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
 COBJS-$(CONFIG_CMD_USB) += cmd_usb.o

common/cmd_bdinfo.c

@@ -273,6 +273,37 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_BLACKFIN)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	printf("U-Boot      = %s\n", bd->bi_r_version);
+	printf("CPU         = %s\n", bd->bi_cpu);
+	printf("Board       = %s\n", bd->bi_board_name);
+	printf("VCO         = %lu MHz\n", bd->bi_vco / 1000000);
+	printf("CCLK        = %lu MHz\n", bd->bi_cclk / 1000000);
+	printf("SCLK        = %lu MHz\n", bd->bi_sclk / 1000000);
+
+	print_num("boot_params", (ulong)bd->bi_boot_params);
+	print_num("memstart",    (ulong)bd->bi_memstart);
+	print_num("memsize",     (ulong)bd->bi_memsize);
+	print_num("flashstart",  (ulong)bd->bi_flashstart);
+	print_num("flashsize",   (ulong)bd->bi_flashsize);
+	print_num("flashoffset", (ulong)bd->bi_flashoffset);
+
+	puts("ethaddr     =");
+	for (i = 0; i < 6; ++i)
+		printf("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+	puts("\nip_addr     = ");
+	print_IPaddr(bd->bi_ip_addr);
+	printf("\nbaudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else /* ! PPC, which leaves MIPS */
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

common/cmd_mem.c

@@ -154,9 +154,32 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		}
 	} while (nbytes > 0);
 #else
-	/* Print the lines. */
-	print_buffer(addr, (void*)addr, size, length, DISP_LINE_LEN/size);
-	addr += size*length;
+
+# if defined(CONFIG_BLACKFIN)
+	/* See if we're trying to display L1 inst */
+	if (addr_bfin_on_chip_mem(addr)) {
+		char linebuf[DISP_LINE_LEN];
+		ulong linebytes, nbytes = length * size;
+		do {
+			linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
+			memcpy(linebuf, (void *)addr, linebytes);
+			print_buffer(addr, linebuf, size, linebytes/size, DISP_LINE_LEN/size);
+
+			nbytes -= linebytes;
+			addr += linebytes;
+			if (ctrlc()) {
+				rc = 1;
+				break;
+			}
+		} while (nbytes > 0);
+	} else
+# endif
+
+	{
+		/* Print the lines. */
+		print_buffer(addr, (void*)addr, size, length, DISP_LINE_LEN/size);
+		addr += size*length;
+	}
 #endif
 
 	dp_last_addr = addr;
@@ -308,6 +331,13 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 #endif
 
+#ifdef CONFIG_BLACKFIN
+	if (addr_bfin_on_chip_mem(addr1) || addr_bfin_on_chip_mem(addr2)) {
+		puts ("Comparison with L1 instruction memory not supported.\n\r");
+		return 0;
+	}
+#endif
+
 	ngood = 0;
 
 	while (count-- > 0) {
@@ -478,6 +508,14 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 #endif
 
+#ifdef CONFIG_BLACKFIN
+	/* See if we're copying to/from L1 inst */
+	if (addr_bfin_on_chip_mem(dest) || addr_bfin_on_chip_mem(addr)) {
+		memcpy((void *)dest, (void *)addr, count * size);
+		return 0;
+	}
+#endif
+
 	while (count-- > 0) {
 		if (size == 4)
 			*((ulong  *)dest) = *((ulong  *)addr);
@@ -659,9 +697,10 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	vu_long	*addr, *start, *end;
 	ulong	val;
 	ulong	readback;
+	int     rcode = 0;
 
 #if defined(CFG_ALT_MEMTEST)
-	vu_long	addr_mask;
+	vu_long	len;
 	vu_long	offset;
 	vu_long	test_offset;
 	vu_long	pattern;
@@ -689,7 +728,6 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #else
 	ulong	incr;
 	ulong	pattern;
-	int     rcode = 0;
 #endif
 
 	if (argc > 1) {
@@ -798,26 +836,19 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		 *              all possible.
 		 *
 		 * Returns:     0 if the test succeeds, 1 if the test fails.
-		 *
-		 * ## NOTE ##	Be sure to specify start and end
-		 *              addresses such that addr_mask has
-		 *              lots of bits set. For example an
-		 *              address range of 01000000 02000000 is
-		 *              bad while a range of 01000000
-		 *              01ffffff is perfect.
 		 */
-		addr_mask = ((ulong)end - (ulong)start)/sizeof(vu_long);
+		len = ((ulong)end - (ulong)start)/sizeof(vu_long);
 		pattern = (vu_long) 0xaaaaaaaa;
 		anti_pattern = (vu_long) 0x55555555;
 
-		PRINTF("%s:%d: addr mask = 0x%.8lx\n",
+		PRINTF("%s:%d: length = 0x%.8lx\n",
 			__FUNCTION__, __LINE__,
-			addr_mask);
+			len);
 		/*
 		 * Write the default pattern at each of the
 		 * power-of-two offsets.
 		 */
-		for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) {
+		for (offset = 1; offset < len; offset <<= 1) {
 			start[offset] = pattern;
 		}
 
@@ -827,7 +858,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		test_offset = 0;
 		start[test_offset] = anti_pattern;
 
-		for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) {
+		for (offset = 1; offset < len; offset <<= 1) {
 		    temp = start[offset];
 		    if (temp != pattern) {
 			printf ("\nFAILURE: Address bit stuck high @ 0x%.8lx:"
@@ -841,10 +872,10 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		/*
 		 * Check for addr bits stuck low or shorted.
 		 */
-		for (test_offset = 1; (test_offset & addr_mask) != 0; test_offset <<= 1) {
+		for (test_offset = 1; test_offset < len; test_offset <<= 1) {
 		    start[test_offset] = anti_pattern;
 
-		    for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) {
+		    for (offset = 1; offset < len; offset <<= 1) {
 			temp = start[offset];
 			if ((temp != pattern) && (offset != test_offset)) {
 			    printf ("\nFAILURE: Address bit stuck low or shorted @"
@@ -954,8 +985,8 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		}
 		incr = -incr;
 	}
-	return rcode;
 #endif
+	return rcode;
 }
 
 
@@ -1006,6 +1037,13 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 	}
 #endif
 
+#ifdef CONFIG_BLACKFIN
+	if (addr_bfin_on_chip_mem(addr)) {
+		puts ("Can't modify L1 instruction in place. Use cp instead.\n\r");
+		return 0;
+	}
+#endif
+
 	/* Print the address, followed by value.  Then accept input for
 	 * the next value.  A non-converted value exits.
 	 */

common/cmd_otp.c

@@ -0,0 +1,163 @@
+/*
+ * cmd_otp.c - interface to Blackfin on-chip One-Time-Programmable memory
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+/* There are 512 128-bit "pages" (0x000 to 0x1FF).
+ * The pages are accessable as 64-bit "halfpages" (an upper and lower half).
+ * The pages are not part of the memory map.  There is an OTP controller which
+ * handles scanning in/out of bits.  While access is done through OTP MMRs,
+ * the bootrom provides C-callable helper functions to handle the interaction.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_OTP
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/otp.h>
+
+static const char *otp_strerror(uint32_t err)
+{
+	switch (err) {
+	case 0:                   return "no error";
+	case OTP_WRITE_ERROR:     return "OTP fuse write error";
+	case OTP_READ_ERROR:      return "OTP fuse read error";
+	case OTP_ACC_VIO_ERROR:   return "invalid OTP address";
+	case OTP_DATA_MULT_ERROR: return "multiple bad bits detected";
+	case OTP_ECC_MULT_ERROR:  return "error in ECC bits";
+	case OTP_PREV_WR_ERROR:   return "space already written";
+	case OTP_DATA_SB_WARN:    return "single bad bit in half page";
+	case OTP_ECC_SB_WARN:     return "single bad bit in ECC";
+	default:                  return "unknown error";
+	}
+}
+
+#define lowup(x) ((x) % 2 ? "upper" : "lower")
+
+int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	bool force = false;
+	if (!strcmp(argv[1], "--force")) {
+		force = true;
+		argv[1] = argv[0];
+		argv++;
+		--argc;
+	}
+
+	uint32_t (*otp_func)(uint32_t page, uint32_t flags, uint64_t *page_content);
+	if (!strcmp(argv[1], "read"))
+		otp_func = otp_read;
+	else if (!strcmp(argv[1], "write"))
+		otp_func = otp_write;
+	else {
+ usage:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	uint64_t *addr = (uint64_t *)simple_strtoul(argv[2], NULL, 16);
+	uint32_t page = simple_strtoul(argv[3], NULL, 16);
+	uint32_t flags, ret;
+	size_t i, count;
+	ulong half;
+
+	if (argc > 4)
+		count = simple_strtoul(argv[4], NULL, 16);
+	else
+		count = 2;
+
+	if (argc > 5) {
+		half = simple_strtoul(argv[5], NULL, 16);
+		if (half != 0 && half != 1) {
+			puts("Error: 'half' can only be '0' or '1'\n");
+			goto usage;
+		}
+	} else
+		half = 0;
+
+	/* do to the nature of OTP, make sure users are sure */
+	if (!force && otp_func == otp_write) {
+		printf(
+			"Writing one time programmable memory\n"
+			"Make sure your operating voltages and temperature are within spec\n"
+			"   source address:  0x%p\n"
+			"   OTP destination: %s page 0x%03X - %s page 0x%03X\n"
+			"   number to write: %ld halfpages\n"
+			" type \"YES\" (no quotes) to confirm: ",
+			addr,
+			lowup(half), page,
+			lowup(half + count - 1), page + (half + count - 1) / 2,
+			half + count
+		);
+
+		i = 0;
+		while (1) {
+			if (tstc()) {
+				const char exp_ans[] = "YES\r";
+				char c;
+				putc(c = getc());
+				if (exp_ans[i++] != c) {
+					printf(" Aborting\n");
+					return 1;
+				} else if (!exp_ans[i]) {
+					puts("\n");
+					break;
+				}
+			}
+		}
+
+		/* Only supported in newer silicon ... enable writing */
+#if (0)
+		otp_command(OTP_INIT, ...);
+#else
+		*pOTP_TIMING = 0x32149485;
+#endif
+	}
+
+	printf("OTP memory %s: addr 0x%08lx  page 0x%03X  count %ld ... ",
+		argv[1], addr, page, count);
+
+	ret = 0;
+	for (i = half; i < count + half; ++i) {
+		flags = (i % 2) ? OTP_UPPER_HALF : OTP_LOWER_HALF;
+		ret = otp_func(page, flags, addr);
+		if (ret & 0x1)
+			break;
+		else if (ret)
+			puts("W");
+		else
+			puts(".");
+		++addr;
+		if (i % 2)
+			++page;
+	}
+	if (ret & 0x1)
+		printf("\nERROR at page 0x%03X (%s-halfpage): 0x%03X: %s\n",
+			page, lowup(i), ret, otp_strerror(ret));
+	else
+		puts(" done\n");
+
+	if (otp_func == otp_write)
+		/* Only supported in newer silicon ... disable writing */
+#if (0)
+		otp_command(OTP_INIT, ...);
+#else
+		*pOTP_TIMING = 0x1485;
+#endif
+
+	return ret;
+}
+
+U_BOOT_CMD(otp, 6, 0, do_otp,
+	"otp - One-Time-Programmable sub-system\n",
+	"read <addr> <page> [count] [half]\n"
+	"otp write [--force] <addr> <page> [count] [half]\n"
+	"    - read/write 'count' half-pages starting at page 'page' (offset 'half')\n");
+
+#endif

common/cmd_reginfo.c

@@ -31,6 +31,8 @@
 #include <mpc5xx.h>
 #elif defined (CONFIG_MPC5200)
 #include <mpc5xxx.h>
+#elif defined (CONFIG_MPC86xx)
+extern void mpc86xx_reginfo(void);
 #endif
 
 int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -329,16 +331,56 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
 	printf ("\tSDRAMCS1: %08X\n",
 		*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
-#endif /* CONFIG_MPC5200 */
+#elif defined(CONFIG_MPC86xx)
+	mpc86xx_reginfo();
+
+#elif defined(CONFIG_BLACKFIN)
+	puts("\nSystem Configuration registers\n");
+
+	puts("\nPLL Registers\n");
+	printf("\tPLL_DIV:   0x%04x   PLL_CTL:      0x%04x\n",
+		bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
+	printf("\tPLL_STAT:  0x%04x   PLL_LOCKCNT:  0x%04x\n",
+		bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
+	printf("\tVR_CTL:    0x%04x\n", bfin_read_VR_CTL());
+
+	puts("\nEBIU AMC Registers\n");
+	printf("\tEBIU_AMGCTL:   0x%04x\n", bfin_read_EBIU_AMGCTL());
+	printf("\tEBIU_AMBCTL0:  0x%08x   EBIU_AMBCTL1:  0x%08x\n",
+		bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
+# ifdef EBIU_MODE
+	printf("\tEBIU_MBSCTL:   0x%08x   EBIU_ARBSTAT:  0x%08x\n",
+		bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
+	printf("\tEBIU_MODE:     0x%08x   EBIU_FCTL:     0x%08x\n",
+		bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
+# endif
+
+# ifdef EBIU_RSTCTL
+	puts("\nEBIU DDR Registers\n");
+	printf("\tEBIU_DDRCTL0:  0x%08x   EBIU_DDRCTL1:  0x%08x\n",
+		bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
+	printf("\tEBIU_DDRCTL2:  0x%08x   EBIU_DDRCTL3:  0x%08x\n",
+		bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
+	printf("\tEBIU_DDRQUE:   0x%08x   EBIU_RSTCTL    0x%04x\n",
+		bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
+	printf("\tEBIU_ERRADD:   0x%08x   EBIU_ERRMST:   0x%04x\n",
+		bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
+# else
+	puts("\nEBIU SDC Registers\n");
+	printf("\tEBIU_SDRRC:   0x%04x   EBIU_SDBCTL:  0x%04x\n",
+		bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
+	printf("\tEBIU_SDSTAT:  0x%04x   EBIU_SDGCTL:  0x%08x\n",
+		bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
+# endif
+
+#endif /* CONFIG_BLACKFIN */
+
 	return 0;
 }
 
  /**************************************************/
 
-#if ( defined(CONFIG_8xx)   || defined(CONFIG_405GP) || \
-      defined(CONFIG_405EP) || defined(CONFIG_MPC5200)  ) && \
-    defined(CONFIG_CMD_REGINFO)
-
+#if defined(CONFIG_CMD_REGINFO)
 U_BOOT_CMD(
  	reginfo,	2,	1,	do_reginfo,
 	"reginfo - print register information\n",

common/cmd_strings.c

@@ -0,0 +1,49 @@
+/*
+ * cmd_strings.c - just like `strings` command
+ *
+ * Copyright (c) 2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CFG_STRINGS
+
+static char *start_addr, *last_addr;
+
+int do_strings(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc == 1) {
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if ((flag & CMD_FLAG_REPEAT) == 0) {
+		start_addr = (char *)simple_strtoul(argv[1], NULL, 16);
+		if (argc > 2)
+			last_addr = (char *)simple_strtoul(argv[2], NULL, 16);
+		else
+			last_addr = (char *)-1;
+	}
+
+	char *addr = start_addr;
+	do {
+		printf("%s\n", addr);
+		addr += strlen(addr) + 1;
+	} while (addr[0] && addr < last_addr);
+
+	last_addr = addr + (last_addr - start_addr);
+	start_addr = addr;
+
+	return 0;
+}
+
+U_BOOT_CMD(strings, 3, 1, do_strings,
+	"strings - display strings\n",
+	"<addr> [byte count]\n"
+	"    - display strings at <addr> for at least [byte count] or first double NUL\n");
+
+#endif

common/env_dataflash.c

@@ -44,22 +44,22 @@ extern uchar default_environment[];
 uchar env_get_char_spec (int index)
 {
 	uchar c;
-	read_dataflash (CFG_ENV_ADDR+index+offsetof(env_t,data),1,&c);
+	read_dataflash(CFG_ENV_ADDR + index + offsetof(env_t,data),
+	1, (char *)&c);
 	return (c);
 }
 
 void env_relocate_spec (void)
 {
-	read_dataflash (CFG_ENV_ADDR,CFG_ENV_SIZE,(uchar *)env_ptr);
+	read_dataflash(CFG_ENV_ADDR, CFG_ENV_SIZE, (char *)env_ptr);
 }
 
 int saveenv(void)
 {
-/* env must be copied to do not alter env structure in memory*/
-unsigned char temp[CFG_ENV_SIZE];
-int i;
+	/* env must be copied to do not alter env structure in memory*/
+	unsigned char temp[CFG_ENV_SIZE];
 	memcpy(temp, env_ptr, CFG_ENV_SIZE);
-	return write_dataflash (CFG_ENV_ADDR, (unsigned long)temp, CFG_ENV_SIZE);
+	return write_dataflash(CFG_ENV_ADDR, (unsigned long)temp, CFG_ENV_SIZE);
 }
 
 /************************************************************************
@@ -77,13 +77,14 @@ int env_init(void)
 		AT91F_DataflashInit();	/* prepare for DATAFLASH read/write */
 
 		/* read old CRC */
-		read_dataflash (CFG_ENV_ADDR+offsetof(env_t,crc),sizeof(ulong),&crc);
+		read_dataflash(CFG_ENV_ADDR + offsetof(env_t, crc),
+			sizeof(ulong), (char *)&crc);
 		new = 0;
 		len = ENV_SIZE;
 		off = offsetof(env_t,data);
 		while (len > 0) {
 			int n = (len > sizeof(buf)) ? sizeof(buf) : len;
-			read_dataflash (CFG_ENV_ADDR+off,n , buf);
+			read_dataflash(CFG_ENV_ADDR + off, n, (char *)buf);
 			new = crc32 (new, buf, n);
 			len -= n;
 			off += n;

common/environment.c

@@ -70,11 +70,16 @@
 /*
  * Macros to generate global absolutes.
  */
+#if defined(__bfin__)
+# define GEN_SET_VALUE(name, value) asm (".set " GEN_SYMNAME(name) ", " GEN_VALUE(value))
+#else
+# define GEN_SET_VALUE(name, value) asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+#endif
 #define GEN_SYMNAME(str) SYM_CHAR #str
 #define GEN_VALUE(str) #str
 #define GEN_ABS(name, value) \
 		asm (".globl " GEN_SYMNAME(name)); \
-		asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+		GEN_SET_VALUE(name, value)
 
 /*
  * Macros to transform values

common/fdt_support.c

@@ -30,9 +30,6 @@
 #include <fdt_support.h>
 #include <exports.h>
 
-#ifdef CONFIG_QE
-#include "../drivers/qe/qe.h"
-#endif
 /*
  * Global data (for the gd->bd)
  */
@@ -418,7 +415,7 @@ void do_fixup_by_path(void *fdt, const char *path, const char *prop,
 {
 #if defined(DEBUG)
 	int i;
-	debug("Updating property '%s/%s' = ", node, prop);
+	debug("Updating property '%s/%s' = ", path, prop);
 	for (i = 0; i < len; i++)
 		debug(" %.2x", *(u8*)(val+i));
 	debug("\n");
@@ -444,7 +441,7 @@ void do_fixup_by_prop(void *fdt,
 	int off;
 #if defined(DEBUG)
 	int i;
-	debug("Updating property '%s/%s' = ", node, prop);
+	debug("Updating property '%s' = ", prop);
 	for (i = 0; i < len; i++)
 		debug(" %.2x", *(u8*)(val+i));
 	debug("\n");
@@ -471,7 +468,7 @@ void do_fixup_by_compat(void *fdt, const char *compat,
 	int off = -1;
 #if defined(DEBUG)
 	int i;
-	debug("Updating property '%s/%s' = ", node, prop);
+	debug("Updating property '%s' = ", prop);
 	for (i = 0; i < len; i++)
 		debug(" %.2x", *(u8*)(val+i));
 	debug("\n");
@@ -617,49 +614,4 @@ void fdt_fixup_ethernet(void *fdt, bd_t *bd)
 #endif
 	}
 }
-
-#ifdef CONFIG_QE
-/*
- * If a QE firmware has been uploaded, then add the 'firmware' node under
- * the 'qe' node.
- */
-void fdt_fixup_qe_firmware(void *fdt)
-{
-	struct qe_firmware_info *qe_fw_info;
-	int node, ret;
-
-	qe_fw_info = qe_get_firmware_info();
-	if (!qe_fw_info)
-		return;
-
-	node = fdt_path_offset(fdt, "/qe");
-	if (node < 0)
-		return;
-
-	/* We assume the node doesn't exist yet */
-	node = fdt_add_subnode(fdt, node, "firmware");
-	if (node < 0)
-		return;
-
-	ret = fdt_setprop(fdt, node, "extended-modes",
-		&qe_fw_info->extended_modes, sizeof(u64));
-	if (ret < 0)
-		goto error;
-
-	ret = fdt_setprop_string(fdt, node, "id", qe_fw_info->id);
-	if (ret < 0)
-		goto error;
-
-	ret = fdt_setprop(fdt, node, "virtual-traps", qe_fw_info->vtraps,
-		sizeof(qe_fw_info->vtraps));
-	if (ret < 0)
-		goto error;
-
-	return;
-
-error:
-	fdt_del_node(fdt, node);
-}
-#endif
-
 #endif

common/miiphyutil.c

@@ -36,7 +36,6 @@
 #include <net.h>
 
 /* local debug macro */
-#define MII_DEBUG
 #undef MII_DEBUG
 
 #undef debug
@@ -261,31 +260,25 @@ int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
 	unsigned short tmp;
 
 	if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
-#ifdef DEBUG
-		puts ("PHY ID register 2 read failed\n");
-#endif
+		debug ("PHY ID register 2 read failed\n");
 		return (-1);
 	}
 	reg = tmp;
 
-#ifdef DEBUG
-	printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
-#endif
+	debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
+
 	if (reg == 0xFFFF) {
 		/* No physical device present at this address */
 		return (-1);
 	}
 
 	if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
-#ifdef DEBUG
-		puts ("PHY ID register 1 read failed\n");
-#endif
+		debug ("PHY ID register 1 read failed\n");
 		return (-1);
 	}
 	reg |= tmp << 16;
-#ifdef DEBUG
-	printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
-#endif
+	debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
+
 	*oui = (reg >> 10);
 	*model = (unsigned char)((reg >> 4) & 0x0000003F);
 	*rev = (unsigned char)(reg & 0x0000000F);
@@ -304,15 +297,11 @@ int miiphy_reset (char *devname, unsigned char addr)
 	int loop_cnt;
 
 	if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
-#ifdef DEBUG
-		printf ("PHY status read failed\n");
-#endif
+		debug ("PHY status read failed\n");
 		return (-1);
 	}
 	if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) {
-#ifdef DEBUG
-		puts ("PHY reset failed\n");
-#endif
+		debug ("PHY reset failed\n");
 		return (-1);
 	}
 #ifdef CONFIG_PHY_RESET_DELAY
@@ -327,9 +316,7 @@ int miiphy_reset (char *devname, unsigned char addr)
 	reg = 0x8000;
 	while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
 		if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
-#     ifdef DEBUG
-			puts ("PHY status read failed\n");
-#     endif
+			debug ("PHY status read failed\n");
 			return (-1);
 		}
 	}

config.mk

@@ -121,6 +121,7 @@ CC	= $(CROSS_COMPILE)gcc
 CPP	= $(CC) -E
 AR	= $(CROSS_COMPILE)ar
 NM	= $(CROSS_COMPILE)nm
+LDR	= $(CROSS_COMPILE)ldr
 STRIP	= $(CROSS_COMPILE)strip
 OBJCOPY = $(CROSS_COMPILE)objcopy
 OBJDUMP = $(CROSS_COMPILE)objdump
@@ -147,7 +148,10 @@ OBJCFLAGS += --gap-fill=0xff
 gccincdir := $(shell $(CC) -print-file-name=include)
 
 CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS)		\
-	-D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE)		\
+	-D__KERNEL__
+ifneq ($(TEXT_BASE),)
+CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+endif
 
 ifneq ($(OBJTREE),$(SRCTREE))
 CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include
@@ -185,7 +189,10 @@ endif
 
 AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
 
-LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS += -Bstatic -T $(LDSCRIPT) $(PLATFORM_LDFLAGS)
+ifneq ($(TEXT_BASE),)
+LDFLAGS += -Ttext $(TEXT_BASE)
+endif
 
 # Location of a usable BFD library, where we define "usable" as
 # "built for ${HOST}, supports ${TARGET}".  Sensible values are

cpu/74xx_7xx/config.mk

@@ -23,4 +23,4 @@
 
 PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
 
-PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -ffixed-r29 -mstring
+PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring

cpu/arm1136/interrupts.c

@@ -37,145 +37,11 @@
 # include <asm/arch/omap2420.h>
 #endif
 
-#include <asm/proc-armv/ptrace.h>
-
 #define TIMER_LOAD_VAL 0
 
 /* macro to read the 32 bit timer */
 #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR))
 
-#ifdef CONFIG_USE_IRQ
-/* enable IRQ interrupts */
-void enable_interrupts (void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-						 "bic %0, %0, #0x80\n"
-						 "msr cpsr_c, %0"
-						 : "=r" (temp)
-						 :
-						 : "memory");
-}
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
-	unsigned long old,temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-						 "orr %1, %0, #0xc0\n"
-						 "msr cpsr_c, %1"
-						 : "=r" (old), "=r" (temp)
-						 :
-						 : "memory");
-	return(old & 0x80) == 0;
-}
-#else
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-		"USER_26",  "FIQ_26",   "IRQ_26",   "SVC_26",
-		"UK4_26",   "UK5_26",   "UK6_26",   "UK7_26",
-		"UK8_26",   "UK9_26",   "UK10_26",  "UK11_26",
-		"UK12_26",  "UK13_26",  "UK14_26",  "UK15_26",
-		"USER_32",  "FIQ_32",   "IRQ_32",   "SVC_32",
-		"UK4_32",   "UK5_32",   "UK6_32",   "ABT_32",
-		"UK8_32",   "UK9_32",   "UK10_32",  "UND_32",
-		"UK12_32",  "UK13_32",  "UK14_32",  "SYS_32",
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
-			"sp : %08lx  ip : %08lx  fp : %08lx\n",
-			instruction_pointer (regs),
-			regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
-			regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
-			regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
-			regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-			flags & CC_N_BIT ? 'N' : 'n',
-			flags & CC_Z_BIT ? 'Z' : 'z',
-			flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-			interrupts_enabled (regs) ? "on" : "off",
-			fast_interrupts_enabled (regs) ? "on" : "off",
-			processor_modes[processor_mode (regs)],
-			thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
 #if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
 /* Use the IntegratorCP function from board/integratorcp.c */
 #else

cpu/arm1136/start.S

@@ -35,6 +35,25 @@
 #endif
 .globl _start
 _start: b	reset
+#ifdef CONFIG_ONENAND_IPL
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+
+_hang:
+	.word	do_hang
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678	/* now 16*4=64 */
+#else
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -51,6 +70,7 @@ _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_ONENAND_IPL */
 .global _end_vect
 _end_vect:
 
@@ -139,7 +159,9 @@ relocate:				/* relocate U-Boot to RAM	    */
 	adr	r0, _start		/* r0 <- current position of code   */
 	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
 	cmp	r0, r1			/* don't reloc during debug	    */
+#ifndef CONFIG_ONENAND_IPL
 	beq	stack_setup
+#endif	/* CONFIG_ONENAND_IPL */
 
 	ldr	r2, _armboot_start
 	ldr	r3, _bss_start
@@ -156,26 +178,36 @@ copy_loop:
 	/* Set up the stack						    */
 stack_setup:
 	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
+#ifdef CONFIG_ONENAND_IPL
+	sub	sp, r0, #128		/* leave 32 words for abort-stack   */
+#else
 	sub	r0, r0, #CFG_MALLOC_LEN /* malloc area			    */
 	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo			    */
 #ifdef CONFIG_USE_IRQ
 	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+#endif	/* CONFIG_ONENAND_IPL */
 
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment	    */
 	ldr	r1, _bss_end		/* stop here			    */
 	mov	r2, #0x00000000		/* clear			    */
 
+#ifndef CONFIG_ONENAND_IPL
 clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
+#endif
 
 	ldr	pc, _start_armboot
 
+#ifdef CONFIG_ONENAND_IPL
+_start_armboot: .word start_oneboot
+#else
 _start_armboot: .word start_armboot
+#endif
 
 
 /*
@@ -214,6 +246,8 @@ cpu_init_crit:
 	bl	lowlevel_init	/* go setup pll,mux,memory */
 	mov	lr, ip		/* restore link */
 	mov	pc, lr		/* back to my caller */
+
+#ifndef CONFIG_ONENAND_IPL
 /*
  *************************************************************************
  *
@@ -326,10 +360,17 @@ cpu_init_crit:
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
+#endif	/* CONFIG_ONENAND_IPL */
 
 /*
  * exception handlers
  */
+#ifdef CONFIG_ONENAND_IPL
+	.align	5
+do_hang:
+	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
+	bl	hang				/* hang and never return */
+#else	/* !CONFIG_ONENAND IPL */
 	.align	5
 undefined_instruction:
 	get_bad_stack
@@ -415,3 +456,4 @@ rstctl:
 	.word	PM_RSTCTRL_WKUP
 
 #endif
+#endif	/* CONFIG_ONENAND_IPL */

cpu/arm720t/interrupts.c

@@ -60,137 +60,9 @@ static struct _irq_handler IRQ_HANDLER[N_IRQS];
 #endif	/* CONFIG_S3C4510B */
 
 #ifdef CONFIG_USE_IRQ
-/* enable IRQ/FIQ interrupts */
-void enable_interrupts (void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "bic %0, %0, #0x80\n"
-			     "msr cpsr_c, %0"
-			     : "=r" (temp)
-			     :
-			     : "memory");
-}
-
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
-	unsigned long old,temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "orr %1, %0, #0x80\n"
-			     "msr cpsr_c, %1"
-			     : "=r" (old), "=r" (temp)
-			     :
-			     : "memory");
-	return (old & 0x80) == 0;
-}
-#else /* CONFIG_USE_IRQ */
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] =
-		{ "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
-"UK6_26", "UK7_26",
-		"UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
-				"UK14_26", "UK15_26",
-		"USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
-				"UK6_32", "ABT_32",
-		"UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
-				"UK14_32", "SYS_32"
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]	   lr : [<%08lx>]\n"
-			"sp : %08lx  ip : %08lx	 fp : %08lx\n",
-			instruction_pointer (regs),
-			regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx	 r8 : %08lx\n",
-			regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx	 r5 : %08lx  r4 : %08lx\n",
-			regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx	 r1 : %08lx  r0 : %08lx\n",
-			regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-			flags & CC_N_BIT ? 'N' : 'n',
-			flags & CC_Z_BIT ? 'Z' : 'z',
-			flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-			interrupts_enabled (regs) ? "on" : "off",
-			fast_interrupts_enabled (regs) ? "on" : "off",
-			processor_modes[processor_mode (regs)],
-			thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
 void do_irq (struct pt_regs *pt_regs)
 {
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-#elif defined(CONFIG_S3C4510B)
+#if defined(CONFIG_S3C4510B)
 	unsigned int pending;
 
 	while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
@@ -212,7 +84,7 @@ void do_irq (struct pt_regs *pt_regs)
 #error do_irq() not defined for this CPU type
 #endif
 }
-
+#endif
 
 #ifdef CONFIG_S3C4510B
 static void default_isr( void *data) {

cpu/arm920t/interrupts.c

@@ -31,149 +31,20 @@
 
 #include <common.h>
 #include <arm920t.h>
-#include <asm/proc-armv/ptrace.h>
 
 #ifdef CONFIG_USE_IRQ
-/* enable IRQ interrupts */
-void enable_interrupts (void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "bic %0, %0, #0x80\n"
-			     "msr cpsr_c, %0"
-			     : "=r" (temp)
-			     :
-			     : "memory");
-}
-
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
-	unsigned long old,temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "orr %1, %0, #0xc0\n"
-			     "msr cpsr_c, %1"
-			     : "=r" (old), "=r" (temp)
-			     :
-			     : "memory");
-	return (old & 0x80) == 0;
-}
-#else
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
-	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
-	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
-	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
-	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
-	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
-	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
-	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
-		"sp : %08lx  ip : %08lx  fp : %08lx\n",
-		instruction_pointer (regs),
-		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
-		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
-		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
-		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-		flags & CC_N_BIT ? 'N' : 'n',
-		flags & CC_Z_BIT ? 'Z' : 'z',
-		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-		interrupts_enabled (regs) ? "on" : "off",
-		fast_interrupts_enabled (regs) ? "on" : "off",
-		processor_modes[processor_mode (regs)],
-		thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
+#include <asm/proc-armv/ptrace.h>
 void do_irq (struct pt_regs *pt_regs)
 {
-#if defined (CONFIG_USE_IRQ)
 #if defined (ARM920_IRQ_CALLBACK)
 	ARM920_IRQ_CALLBACK();
-	return;
 #elif defined (CONFIG_ARCH_INTEGRATOR)
 	/* ASSUMED to be a timer interrupt  */
 	/* Just clear it - count handled in */
 	/* integratorap.c                   */
 	*(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0;
-#endif /* ARCH_INTEGRATOR */
 #else
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
+#error do_irq() not defined for this cpu type
 #endif
 }
+#endif

cpu/arm920t/s3c24x0/serial.c

@@ -110,7 +110,6 @@ void serial_setbrg(void)
 static int serial_init_dev(const int dev_index)
 {
 	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
-	int i;
 
 	/* FIFO enable, Tx/Rx FIFO clear */
 	uart->UFCON = 0x07;

cpu/arm925t/interrupts.c

@@ -36,146 +36,11 @@
 #include <arm925t.h>
 #include <configs/omap1510.h>
 
-#include <asm/proc-armv/ptrace.h>
-
 #define TIMER_LOAD_VAL 0xffffffff
 
 /* macro to read the 32 bit timer */
 #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
 
-#ifdef CONFIG_USE_IRQ
-/* enable IRQ interrupts */
-void enable_interrupts (void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "bic %0, %0, #0x80\n"
-			     "msr cpsr_c, %0"
-			     : "=r" (temp)
-			     :
-			     : "memory");
-}
-
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
-	unsigned long old,temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "orr %1, %0, #0xc0\n"
-			     "msr cpsr_c, %1"
-			     : "=r" (old), "=r" (temp)
-			     :
-			     : "memory");
-	return (old & 0x80) == 0;
-}
-#else
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
-	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
-	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
-	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
-	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
-	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
-	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
-	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]	   lr : [<%08lx>]\n"
-		"sp : %08lx  ip : %08lx	 fp : %08lx\n",
-		instruction_pointer (regs),
-		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx	 r8 : %08lx\n",
-		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx	 r5 : %08lx  r4 : %08lx\n",
-		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx	 r1 : %08lx  r0 : %08lx\n",
-		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-		flags & CC_N_BIT ? 'N' : 'n',
-		flags & CC_Z_BIT ? 'Z' : 'z',
-		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-		interrupts_enabled (regs) ? "on" : "off",
-		fast_interrupts_enabled (regs) ? "on" : "off",
-		processor_modes[processor_mode (regs)],
-		thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
 static ulong timestamp;
 static ulong lastdec;
 

cpu/arm926ejs/at91cap9/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	= ether.o timer.o spi.o usb.o
+SOBJS	= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

cpu/arm926ejs/at91cap9/config.mk

@@ -0,0 +1,2 @@
+PLATFORM_CPPFLAGS += -march=armv5te
+PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)