Merge branch 'master' of git://git.denx.de/u-boot-sh

board/espt/lowlevel_init.S

@@ -206,26 +206,31 @@ PKDR_A:	.long	0xFFEF0034
 
 /* GPIO Set data */
 PADR_D:	.long	0x00000000
-PACR_D:	.long 	0x00001400
+PACR_D:	.word 	0x1400
+.align 2
 PBDR_D:	.long	0x00000000
-PBCR_D:	.long	0x0000555A
+PBCR_D:	.word	0x555A
+.align 2
 PCDR_D:	.long	0x00000000
-PCCR_D:	.long	0x00005555
+PCCR_D:	.word	0x5555
+.align 2
 PDDR_D:	.long	0x00000000
-PDCR_D:	.long	0x00000155
-PECR_D:	.long	0x00000000
-PFCR_D:	.long	0x00000000
-PGCR_D:	.long	0x00000000
-PHCR_D:	.long	0x00000000
-PICR_D:	.long	0x00000800
+PDCR_D:	.word	0x0155
+PECR_D:	.word	0x0000
+PFCR_D:	.word	0x0000
+PGCR_D:	.word	0x0000
+PHCR_D:	.word	0x0000
+PICR_D:	.word	0x0800
 PJDR_D:	.long	0x00000006
-PJCR_D:	.long	0x00005A57
+PJCR_D:	.word	0x5A57
+.align 2
 PKDR_D:	.long	0x00000000
-PKCR_D:	.long	0x0000FFF9
-PLCR_D:	.long 	0x0000C330
-PMCR_D:	.long	0x0000FFFF
-PNCR_D:	.long	0x00000242
-POCR_D:	.long	0x00000000
+PKCR_D:	.word	0xFFF9
+.align 2
+PLCR_D:	.word 	0xC330
+PMCR_D:	.word	0xFFFF
+PNCR_D:	.word	0x0242
+POCR_D:	.word	0x0000
 
 /* Pin Select */
 PSEL0_A:	.long	0xFFEF0070
@@ -233,11 +238,12 @@ PSEL1_A:	.long	0xFFEF0072
 PSEL2_A:	.long	0xFFEF0074
 PSEL3_A:	.long	0xFFEF0076
 PSEL4_A:	.long	0xFFEF0078
-PSEL0_D:	.long	0x0001
-PSEL1_D:	.long	0x2400
-PSEL2_D:	.long	0x0000
-PSEL3_D:	.long	0x2421
-PSEL4_D:	.long	0x0000
+PSEL0_D:	.word	0x0001
+PSEL1_D:	.word	0x2400
+PSEL2_D:	.word	0x0000
+PSEL3_D:	.word	0x2421
+PSEL4_D:	.word	0x0000
+.align 2
 
 MMSEL_A:	.long	0xFE600020
 BCR_A:		.long	0xFF801000

board/mpr2/lowlevel_init.S

@@ -82,10 +82,10 @@ lowlevel_init:
 /*
  * PLL Settings
  */
-FRQCR_D:	.long	0x1103		/* I:B:P=8:4:2 */
-WTCNT_D:	.long	0x5A00		/* start counting at zero */
-WTCSR_D:	.long	0xA507		/* divide by 4096 */
-
+FRQCR_D:	.word	0x1103		/* I:B:P=8:4:2 */
+WTCNT_D:	.word	0x5A00		/* start counting at zero */
+WTCSR_D:	.word	0xA507		/* divide by 4096 */
+.align 2
 /*
  * Spansion S29GL256N11 @ 48 MHz
  */

board/ms7720se/lowlevel_init.S

@@ -114,10 +114,10 @@ FRQCR_A:	.long	0xA415FF80	/* FRQCR Address */
 WTCNT_A:	.long	0xA415FF84
 WTCSR_A:	.long	0xA415FF86
 UCLKCR_A:	.long	0xA40A0008
-FRQCR_D:	.long	0x1103		/* I:B:P=8:4:2 */
-WTCNT_D:	.long	0x5A00
-WTCSR_D:	.long	0xA506
-UCLKCR_D:	.long	0xA5C0
+FRQCR_D:	.word	0x1103		/* I:B:P=8:4:2 */
+WTCNT_D:	.word	0x5A00
+WTCSR_D:	.word	0xA506
+UCLKCR_D:	.word	0xA5C0
 
 #define BSC_BASE	0xA4FD0000
 CMNCR_A:	.long	BSC_BASE
@@ -164,7 +164,8 @@ SDCR_D1:	.long	0x00000011
 RTCSR_D:	.long	0xA55A0010
 RTCNT_D:	.long	0xA55A001F
 RTCOR_D:	.long	0xA55A001F
-SDMR3_D:	.long	0x0000
+SDMR3_D:	.word	0x0000
+.align 2
 SDCR_D2:	.long	0x00000811
 
 #define PFC_BASE	0xA4050100
@@ -178,15 +179,16 @@ PTCR_A:		.long	PFC_BASE + 0x1E
 PVCR_A:		.long	PFC_BASE + 0x22
 PSELA_A:	.long	PFC_BASE + 0x24
 
-PCCR_D:		.long	0x0000
-PDCR_D:		.long	0x0000
-PECR_D:		.long	0x0000
-PGCR_D:		.long	0x0000
-PHCR_D:		.long	0x0000
-PPCR_D:		.long	0x00AA
-PTCR_D:		.long	0x0280
-PVCR_D:		.long	0x0000
-PSELA_D:	.long	0x0000
+PCCR_D:		.word	0x0000
+PDCR_D:		.word	0x0000
+PECR_D:		.word	0x0000
+PGCR_D:		.word	0x0000
+PHCR_D:		.word	0x0000
+PPCR_D:		.word	0x00AA
+PTCR_D:		.word	0x0280
+PVCR_D:		.word	0x0000
+PSELA_D:	.word	0x0000
+.align 2
 
 CCR_A:		.long	0xFFFFFFEC
 !CCR_D:		.long	0x0000000D

board/ms7750se/lowlevel_init.S

@@ -120,13 +120,14 @@ CCR_D_DISABLE:	.long	0x0808
 FRQCR_A:	.long	FRQCR
 FRQCR_D:
 #ifdef CONFIG_CPU_TYPE_R
-		.long	0x00000e1a	/* 12:3:3 */
+		.word	0x0e1a	/* 12:3:3 */
 #else	/* CONFIG_CPU_TYPE_R */
 #ifdef CONFIG_GOOD_SESH4
-		.long	0x00000e13	/* 6:2:1 */
+		.word	0x00e13	/* 6:2:1 */
 #else
-		.long	0x00000e23	/* 6:1:1 */
+		.word	0x00e23	/* 6:1:1 */
 #endif
+.align 2
 #endif	/* CONFIG_CPU_TYPE_R */
 
 BCR1_A:		.long	BCR1
@@ -140,15 +141,19 @@ WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
 WCR3_A:		.long	WCR3
 WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
 RTCSR_A:	.long	RTCSR
-RTCSR_D:	.long	0xA518		/* RTCSR Write Code A5h Data 18h */
+RTCSR_D:	.word	0xA518		/* RTCSR Write Code A5h Data 18h */
+.align 2
 RTCNT_A:	.long	RTCNT
-RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
+RTCNT_D:	.word	0xA500		/* RTCNT Write Code A5h Data 00h */
+.align 2
 RTCOR_A:	.long	RTCOR
-RTCOR_D:	.long	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
+RTCOR_D:	.word	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
+.align 2
 SDMR3_A:	.long	SDMR3_ADDRESS
 SDMR3_D:	.long	0x00
 MCR_A:		.long	MCR
 MCR_D1:		.long	MCR_D1_VALUE
 MCR_D2:		.long	MCR_D2_VALUE
 RFCR_A:		.long	RFCR
-RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
+RFCR_D:		.word	0xA400		/* RFCR Write Code A4h Data 00h */
+.align 2

board/renesas/ap325rxa/lowlevel_init.S

@@ -119,15 +119,16 @@ lowlevel_init:
 
 DRVCRA_A:	.long	DRVCRA
 DRVCRB_A:	.long	DRVCRB
-DRVCRA_D:	.long	0x4555
-DRVCRB_D:	.long	0x0005
+DRVCRA_D:	.word	0x4555
+DRVCRB_D:	.word	0x0005
 
 RWTCSR_A:	.long	RWTCSR
 RWTCNT_A:	.long	RWTCNT
 FRQCR_A:	.long	FRQCR
-RWTCSR_D1:	.long	0xa507
-RWTCSR_D2:	.long	0xa504
-RWTCNT_D:	.long	0x5a00
+RWTCSR_D1:	.word	0xa507
+RWTCSR_D2:	.word	0xa504
+RWTCNT_D:	.word	0x5a00
+.align 2
 FRQCR_D:	.long	0x0b04474a
 
 SBSC_SDCR_A:	.long	SBSC_SDCR

board/renesas/r2dplus/lowlevel_init.S

@@ -94,11 +94,14 @@ WCR3_D:		.long	0x07777707
 LED_A:		.long	0x04000036	/* LED Address */
 LED_D:		.long	0xFF		/* LED Data */
 RTCNT_A:	.long	RTCNT		/* RTCNT Address */
-RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
+RTCNT_D:	.word	0xA500		/* RTCNT Write Code A5h Data 00h */
+.align 2
 RTCOR_A:	.long	RTCOR		/* RTCOR Address */
-RTCOR_D:	.long	0xA534		/* RTCOR Write Code */
+RTCOR_D:	.word	0xA534		/* RTCOR Write Code */
+.align 2
 RTCSR_A:	.long	RTCSR		/* RTCSR Address */
-RTCSR_D:	.long	0xA510		/* RTCSR Write Code */
+RTCSR_D:	.word	0xA510		/* RTCSR Write Code */
+.align 2
 SDMR3_A:	.long	0xFF9400CC	/* SDMR3 Address */
 SDMR3_D0:	.long	0x55
 SDMR3_D1:	.long	0x00

board/renesas/rsk7203/lowlevel_init.S

@@ -73,7 +73,7 @@ init_bsc_cs0:
 
 	write32	CMNCR_A, CMNCR_D
 
-	write32	SC0BCR_A, SC0BCR_D
+	write32	CS0BCR_A, CS0BCR_D
 
 	write32	CS0WCR_A, CS0WCR_D
 
@@ -122,63 +122,82 @@ repeat0:
 CCR1_A:		.long CCR1
 CCR1_D:		.long 0x0000090B
 PCCRL4_A:	.long 0xFFFE3910
-PCCRL4_D0:	.long 0x00000000
+PCCRL4_D0:	.word 0x0000
+.align 2
 PECRL4_A:	.long 0xFFFE3A10
-PECRL4_D0:	.long 0x00000000
+PECRL4_D0:	.word 0x0000
+.align 2
 PECRL3_A:	.long 0xFFFE3A12
-PECRL3_D:	.long 0x00000000
+PECRL3_D:	.word 0x0000
+.align 2
 PEIORL_A:	.long 0xFFFE3A06
-PEIORL_D0:	.long 0x00001C00
-PEIORL_D1:	.long 0x00001C02
+PEIORL_D0:	.word 0x1C00
+PEIORL_D1:	.word 0x1C02
 PCIORL_A:	.long 0xFFFE3906
-PCIORL_D:	.long 0x00004000
+PCIORL_D:	.word 0x4000
+.align 2
 PFCRH2_A:	.long 0xFFFE3A8C
-PFCRH2_D:	.long 0x00000000
+PFCRH2_D:	.word 0x0000
+.align 2
 PFCRH3_A:	.long 0xFFFE3A8A
-PFCRH3_D:	.long 0x00000000
+PFCRH3_D:	.word 0x0000
+.align 2
 PFCRH1_A:	.long 0xFFFE3A8E
-PFCRH1_D:	.long 0x00000000
+PFCRH1_D:	.word 0x0000
+.align 2
 PFIORH_A:	.long 0xFFFE3A84
-PFIORH_D:	.long 0x00000729
+PFIORH_D:	.word 0x0729
+.align 2
 PECRL1_A:	.long 0xFFFE3A16
-PECRL1_D0:	.long 0x00000033
+PECRL1_D0:	.word 0x0033
+.align 2
 
 
 WTCSR_A:	.long 0xFFFE0000
-WTCSR_D0:	.long 0x0000A518
-WTCSR_D1:	.long 0x0000A51D
+WTCSR_D0:	.word 0xA518
+WTCSR_D1:	.word 0xA51D
 WTCNT_A:	.long 0xFFFE0002
-WTCNT_D:	.long 0x00005A84
+WTCNT_D:	.word 0x5A84
+.align 2
 FRQCR_A:	.long 0xFFFE0010
-FRQCR_D:	.long 0x00000104
+FRQCR_D:	.word 0x0104
+.align 2
 
-PCCRL4_D1:	.long 0x00000010
-PECRL1_D1:	.long 0x00000133
+PCCRL4_D1:	.word 0x0010
+PECRL1_D1:	.word 0x0133
 
 CMNCR_A:	.long 0xFFFC0000
 CMNCR_D:	.long 0x00001810
-SC0BCR_A:	.long 0xFFFC0004
-SC0BCR_D:	.long 0x10000400
+CS0BCR_A:	.long 0xFFFC0004
+CS0BCR_D:	.long 0x10000400
 CS0WCR_A:	.long 0xFFFC0028
 CS0WCR_D:	.long 0x00000B41
-PECRL4_D1:	.long 0x00000100
+PECRL4_D1:	.word 0x0100
+.align 2
 CS1WCR_A:	.long 0xFFFC002C
 CS1WCR_D:	.long 0x00000B01
-PCCRL4_D2:	.long 0x00000011
+PCCRL4_D2:	.word 0x0011
+.align 2
 PCCRL3_A:	.long 0xFFFE3912
-PCCRL3_D:	.long 0x00000011
+PCCRL3_D:	.word 0x0011
+.align 2
 PCCRL2_A:	.long 0xFFFE3914
-PCCRL2_D:	.long 0x00001111
+PCCRL2_D:	.word 0x1111
+.align 2
 PCCRL1_A:	.long 0xFFFE3916
-PCCRL1_D:	.long 0x00001010
+PCCRL1_D:	.word 0x1010
 PDCRL4_A:	.long 0xFFFE3990
-PDCRL4_D:	.long 0x00000011
+PDCRL4_D:	.word 0x0011
+.align 2
 PDCRL3_A:	.long 0xFFFE3992
-PDCRL3_D:	.long 0x00000011
+PDCRL3_D:	.word 0x00011
+.align 2
 PDCRL2_A:	.long 0xFFFE3994
-PDCRL2_D:	.long 0x00001111
+PDCRL2_D:	.word 0x1111
+.align 2
 PDCRL1_A:	.long 0xFFFE3996
-PDCRL1_D:	.long 0x00001000
+PDCRL1_D:	.word 0x1000
+.align 2
 CS3BCR_A:	.long 0xFFFC0010
 CS3BCR_D:	.long 0x00004400
 CS3WCR_A:	.long 0xFFFC0034
@@ -190,13 +209,5 @@ RTCOR_D:	.long 0xA55A0041
 RTCSR_A:	.long 0xFFFC0050
 RTCSR_D:	.long 0xa55a0010
 
-STBCR3_A:	.long 0xFFFE0408
-STBCR3_D:	.long 0x00000000
-STBCR4_A:	.long 0xFFFE040C
-STBCR4_D:	.long 0x00000008
-STBCR5_A:	.long 0xFFFE0410
-STBCR5_D:	.long 0x00000000
-STBCR6_A:	.long 0xFFFE0414
-STBCR6_D:	.long 0x00000002
 SDRAM_MODE:	.long 0xFFFC5040
 REPEAT_D:	.long 0x00009C40

board/renesas/sh7763rdp/lowlevel_init.S

@@ -266,8 +266,8 @@ SDR4_D:		.long	0x00000300
 SDMR00308_D:	.long	0x00000000
 SDMR00B08_D:	.long	0x00000000
 SDMR02000_D:	.long	0x00000000
-PSEL0_D:	.long	0x00000001
-PSEL1_D:	.long	0x00000244
+PSEL0_D:	.word	0x00000001
+PSEL1_D:	.word	0x00000244
 SR_MASK_D:	.long	0xEFFFFF0F
 WDTST_D:	.long	0x5A000FFF
 WDTCSR_D:	.long	0xA5000000

board/renesas/sh7785lcr/lowlevel_init.S

@@ -68,22 +68,22 @@ lowlevel_init:
 	wait_timer	WAIT_200US
 
 	/*------- GPIO -------*/
-	write16 PACR_A,	PACR_D
-	write16 PBCR_A,	PBCR_D
-	write16 PCCR_A,	PCCR_D
-	write16 PDCR_A,	PDCR_D
-	write16 PECR_A,	PECR_D
-	write16 PFCR_A,	PFCR_D
-	write16 PGCR_A,	PGCR_D
+	write16 PACR_A,	PXCR_D
+	write16 PBCR_A,	PXCR_D
+	write16 PCCR_A,	PXCR_D
+	write16 PDCR_A,	PXCR_D
+	write16 PECR_A,	PXCR_D
+	write16 PFCR_A,	PXCR_D
+	write16 PGCR_A,	PXCR_D
 	write16 PHCR_A,	PHCR_D
 	write16 PJCR_A,	PJCR_D
 	write16 PKCR_A,	PKCR_D
-	write16 PLCR_A,	PLCR_D
+	write16 PLCR_A,	PXCR_D
 	write16 PMCR_A,	PMCR_D
 	write16 PNCR_A,	PNCR_D
-	write16 PPCR_A,	PPCR_D
-	write16 PQCR_A,	PQCR_D
-	write16 PRCR_A,	PRCR_D
+	write16 PPCR_A,	PXCR_D
+	write16 PQCR_A,	PXCR_D
+	write16 PRCR_A,	PXCR_D
 
 	write8	PEPUPR_A,	PEPUPR_D
 	write8	PHPUPR_A,	PHPUPR_D
@@ -179,22 +179,14 @@ lbsc_end:
 	.align 4
 
 /*------- GPIO -------*/
-PACR_D:		.long	0x0000
-PBCR_D:		.long	0x0000
-PCCR_D:		.long	0x0000
-PDCR_D:		.long	0x0000
-PECR_D:		.long	0x0000
-PFCR_D:		.long	0x0000
-PGCR_D:		.long	0x0000
-PHCR_D:		.long	0x00c0
-PJCR_D:		.long	0xc3fc
-PKCR_D:		.long	0x03ff
-PLCR_D:		.long	0x0000
-PMCR_D:		.long	0xffff
-PNCR_D:		.long	0xf0c3
-PPCR_D:		.long	0x0000
-PQCR_D:		.long	0x0000
-PRCR_D:		.long	0x0000
+/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */ 
+PXCR_D:		.word	0x0000
+
+PHCR_D:		.word	0x00c0
+PJCR_D:		.word	0xc3fc
+PKCR_D:		.word	0x03ff
+PMCR_D:		.word	0xffff
+PNCR_D:		.word	0xf0c3
 
 PEPUPR_D:	.long	0xff
 PHPUPR_D:	.long	0x00
@@ -203,10 +195,10 @@ PKPUPR_D:	.long	0x00
 PLPUPR_D:	.long	0x00
 PMPUPR_D:	.long	0xfc
 PNPUPR_D:	.long	0x00
-PPUPR1_D:	.long	0xffbf
-PPUPR2_D:	.long	0xff00
-P1MSELR_D:	.long	0x3780
-P2MSELR_D:	.long	0x0000
+PPUPR1_D:	.word	0xffbf
+PPUPR2_D:	.word	0xff00
+P1MSELR_D:	.word	0x3780
+P2MSELR_D:	.word	0x0000
 
 #define GPIO_BASE	0xffe70000
 PACR_A:		.long	GPIO_BASE + 0x00

common/cmd_bdinfo.c

@@ -348,6 +348,25 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_SH)
+
+int do_bdinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	bd_t *bd = gd->bd;
+	print_num  ("mem start      ",	(ulong)bd->bi_memstart);
+	print_lnum ("mem size       ",	(u64)bd->bi_memsize);
+	print_num  ("flash start    ",	(ulong)bd->bi_flashstart);
+	print_num  ("flash size     ",	(ulong)bd->bi_flashsize);
+	print_num  ("flash offset   ",	(ulong)bd->bi_flashoffset);
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf ("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf ("baudrate    = %ld bps\n", (ulong)bd->bi_baudrate);
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif