Added support for PCI bridge on MPC8272ADS

Patch by Vitaly Bordug, Feb 09 2005

CHANGELOG

@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Added support for PCI bridge on MPC8272ADS
+  Patch by Vitaly Bordug, Feb 09 2005
+
 * Update multicore CM9XX support for Integrator AP to allow booting from flash
   Patch by Jean-Paul Saman, 8 Feb 2005
 

board/mpc8260ads/mpc8260ads.c

@@ -13,6 +13,10 @@
  * Yuli Barcohen <yuli@arabellasw.com>
  * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
  *
+ * Copyright (c) 2005 MontaVista Software, Inc.   
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -39,6 +43,9 @@
 #include <i2c.h>
 #include <spd.h>
 #include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
 
 /*
  * I/O Port configuration table
@@ -247,10 +254,23 @@ void reset_phy (void)
 #endif /* CONFIG_MII */
 }
 
+#ifdef CONFIG_PCI
+typedef struct pci_ic_s {
+	unsigned long pci_int_stat;
+	unsigned long pci_int_mask;
+}pci_ic_t;
+#endif
+
 int board_early_init_f (void)
 {
 	vu_long *bcsr = (vu_long *)CFG_BCSR;
 
+#ifdef CONFIG_PCI
+	volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
+	
+	/* mask alll the PCI interrupts */
+	pci_ic->pci_int_mask |= 0xfff00000;
+#endif
 #if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
 	bcsr[1] &= ~RS232EN_1;
 #endif
@@ -506,3 +526,14 @@ int checkboard (void)
 #endif
 	return 0;
 }
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif

cpu/mpc8260/pci.c

@@ -2,6 +2,10 @@
  * (C) Copyright 2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * Copyright (c) 2005 MontaVista Software, Inc.   
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI bridge on MPC8272ADS
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -230,7 +234,7 @@ static inline void pci_outl (u32 addr, u32 data)
 
 void pci_mpc8250_init (struct pci_controller *hose)
 {
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 	DECLARE_GLOBAL_DATA_PTR;
 #endif
 	u16 tempShort;
@@ -248,6 +252,27 @@ void pci_mpc8250_init (struct pci_controller *hose)
 	immap->im_siu_conf.sc_siumcr =
 		(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
 		| SIUMCR_LBPC01;
+#elif defined CONFIG_MPC8272
+	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & 
+                                  ~SIUMCR_BBD &
+                                  ~SIUMCR_ESE &
+                                  ~SIUMCR_PBSE &
+                                  ~SIUMCR_CDIS &
+                                  ~SIUMCR_DPPC11 &
+                                  ~SIUMCR_L2CPC11 &
+                                  ~SIUMCR_LBPC11 &
+                                  ~SIUMCR_APPC11 &
+                                  ~SIUMCR_CS10PC11 &
+                                  ~SIUMCR_BCTLC11 &
+                                  ~SIUMCR_MMR11)
+                                  | SIUMCR_DPPC11
+                                  | SIUMCR_L2CPC01
+                                  | SIUMCR_LBPC00
+                                  | SIUMCR_APPC10
+                                  | SIUMCR_CS10PC00
+                                  | SIUMCR_BCTLC00
+                                  | SIUMCR_MMR11;
+
 #else
 	/*
 	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
@@ -290,7 +315,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
 	immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
 	immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
 
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 	immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
 	immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
 #endif
@@ -300,7 +325,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
 
 	/* give it some time */
 	{
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 		/* Give the PCI cards more time to initialize before query
 		   This might be good for other boards also
 		 */
@@ -344,7 +369,11 @@ void pci_mpc8250_init (struct pci_controller *hose)
 	immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB);	/* Size & attribute */
 
 	/* See above for description - puts PCI request as highest priority */
+#ifdef CONFIG_MPC8272
+	immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
+#else
 	immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
+#endif
 
 	/* Park the bus on the PCI */
 	immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
@@ -370,7 +399,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
 	hose->last_busno = 0xff;
 
 	/* System memory space */
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 
 	pci_set_region (hose->regions + 0,
 			PCI_SLV_MEM_BUS,
 			PCI_SLV_MEM_LOCAL,
@@ -383,7 +412,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
 #endif
 
 	/* PCI memory space */
-#ifdef CONFIG_MPC8266ADS
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 
 	pci_set_region (hose->regions + 1,
 			PCI_MSTR_MEMIO_BUS,
 			PCI_MSTR_MEMIO_LOCAL,

include/configs/MPC8260ADS.h

@@ -13,6 +13,10 @@
  * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  * Ported to MPC8272ADS board.
  *
+ * Copyright (c) 2005 MontaVista Software, Inc.   
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI bridge on MPC8272ADS
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -173,6 +177,15 @@
 #endif
 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
 
+/*PCI*/
+#ifdef CONFIG_MPC8272
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_BOOTDELAY 0
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+
 #ifndef CONFIG_SDRAM_PBI
 #define CONFIG_SDRAM_PBI	0 /* By default, use bank-based interleaving */
 #endif
@@ -205,7 +218,6 @@
 				CFG_CMD_KGDB	| \
 				CFG_CMD_MMC	| \
 				CFG_CMD_NAND	| \
-				CFG_CMD_PCI	| \
 				CFG_CMD_PCMCIA	| \
 				CFG_CMD_REISER	| \
 				CFG_CMD_SCSI	| \
@@ -216,14 +228,21 @@
 				CFG_CMD_VFD	| \
 				CFG_CMD_XIMG
 
-#if CONFIG_ADSTYPE >= CFG_PQ2FADS
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+			         CFG_CMD_SDRAM	| \
+				 CFG_CMD_I2C	| \
+				 CFG_EXCLUDE	) )
+#elif CONFIG_ADSTYPE >= CFG_PQ2FADS
 #define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
 				 CFG_CMD_SDRAM	| \
 				 CFG_CMD_I2C	| \
+				 CFG_CMD_PCI	| \
 				 CFG_EXCLUDE	) )
 #else
 #define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
-				 CFG_EXCLUDE	) )
+				 CMD_CFG_PCI 	| \
+				 CFG_EXCLUDE 	) )
 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -295,6 +314,9 @@
 
 #define CFG_IMMR		0xF0000000
 #define CFG_BCSR		0xF4500000
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CFG_PCI_INT		0xF8200000
+#endif
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_LSDRAM_BASE		0xFD000000
 
@@ -385,6 +407,13 @@
 #define CFG_BR1_PRELIM		CFG_BCSR | 0x00001801
 #define CFG_OR1_PRELIM		0xFFFF8010
 
+/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CFG_BR3_PRELIM	(CFG_PCI_INT | 0x1801)	/* PCI interrupt controller */
+#define CFG_OR3_PRELIM	0xFFFF8010
+#endif
+
 #define CFG_RMR			RMR_CSRE
 #define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 #define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
@@ -417,4 +446,67 @@
 
 #define CFG_RESET_ADDRESS	0x04400000
 
+#if CONFIG_ADSTYPE == CFG_8272ADS
+
+/* PCI Memory map (if different from default map */
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
+#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+				 PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
+#define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
+/* PCIBR0 - for PCI IO*/
+#define CFG_PCI_MSTR0_LOCAL		CFG_PCI_MSTR_IO_LOCAL		/* Local base */
+#define CFG_PCIMSK0_MASK		~(CFG_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
+/* PCIBR1 - prefetch and non-prefetch regions joined together */
+#define CFG_PCI_MSTR1_LOCAL		CFG_PCI_MSTR_MEM_LOCAL	
+#define CFG_PCIMSK1_MASK		~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+
+#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
+
 #endif /* __CONFIG_H */