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@@ -1,5 +1,5 @@
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/*
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- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
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+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
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*
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* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
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*
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@@ -30,9 +30,9 @@
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(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
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#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \
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- (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
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+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0
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-static void force_precharge(void);
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+static void precharge_all_banks(void);
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static void setup_refresh_timer(void);
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static void program_mode_registers(void);
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@@ -47,7 +47,7 @@ void sdram_cfg(void)
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early_udelay(200);
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- force_precharge();
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+ precharge_all_banks();
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setup_refresh_timer();
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@@ -57,19 +57,37 @@ void sdram_cfg(void)
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writel(GLCONFIG_CKE, &sdram->glconfig);
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}
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-static void force_precharge(void)
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+static void precharge_all_banks(void)
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{
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+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
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+
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+ /* Issue PRECHARGE ALL commands */
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+ writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig);
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+
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/*
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- * Errata most EP93xx revisions say that PRECHARGE ALL isn't always
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- * issued.
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+ * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always
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+ * issued
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*
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- * Do a read from each bank to make sure they're precharged
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+ * Cirrus proposes a workaround which consists in performing a read from
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+ * each bank to force the precharge. This causes some boards to hang.
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+ * Writing to the SDRAM banks instead of reading has the same
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+ * side-effect (the SDRAM controller issues the necessary precharges),
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+ * but is known to work on all supported boards
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*/
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PRECHARGE_BANK(0);
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+
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+#if (CONFIG_NR_DRAM_BANKS >= 2)
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PRECHARGE_BANK(1);
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+#endif
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+
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+#if (CONFIG_NR_DRAM_BANKS >= 3)
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PRECHARGE_BANK(2);
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+#endif
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+
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+#if (CONFIG_NR_DRAM_BANKS == 4)
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PRECHARGE_BANK(3);
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+#endif
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}
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static void setup_refresh_timer(void)
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@@ -101,6 +119,11 @@ static void setup_refresh_timer(void)
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static void program_mode_registers(void)
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{
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+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
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+
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+ /* Select mode register update mode */
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+ writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
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+
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/*
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* The mode registers are programmed by performing a read from each
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* SDRAM bank. The value of the address that is read defines the value
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