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@@ -24,40 +24,193 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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+#include <ppc440.h>
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+#include "bamboo.h"
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-int board_early_init_f(void)
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-{
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- register uint reg;
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+void ext_bus_cntlr_init(void);
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+void configure_ppc440ep_pins(void);
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- /*--------------------------------------------------------------------
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- * Setup the external bus controller/chip selects
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- *-------------------------------------------------------------------*/
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- mtdcr(ebccfga, xbcfg);
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- reg = mfdcr(ebccfgd);
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- mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
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+gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
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+#if 0
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+{ /* GPIO Alternate1 Alternate2 Alternate3 */
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+ {
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+ /* GPIO Core 0 */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
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+ { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
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+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
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+ },
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+ {
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+ /* GPIO Core 1 */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
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+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
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+ }
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+};
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+#endif
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-#if 0 /* test-only */
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- mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
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- mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
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+/*----------------------------------------------------------------------------+
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+ | EBC Devices Characteristics
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+ | Peripheral Bank Access Parameters - EBC0_BnAP
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+ | Peripheral Bank Configuration Register - EBC0_BnCR
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+ +----------------------------------------------------------------------------*/
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+/* Small Flash */
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+#define EBC0_BNAP_SMALL_FLASH EBC0_BNAP_BME_DISABLED | \
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+ EBC0_BNAP_TWT_ENCODE(6) | \
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+ EBC0_BNAP_CSN_ENCODE(0) | \
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+ EBC0_BNAP_OEN_ENCODE(1) | \
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+ EBC0_BNAP_WBN_ENCODE(1) | \
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+ EBC0_BNAP_WBF_ENCODE(3) | \
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+ EBC0_BNAP_TH_ENCODE(1) | \
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+ EBC0_BNAP_RE_ENABLED | \
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+ EBC0_BNAP_SOR_DELAYED | \
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+ EBC0_BNAP_BEM_WRITEONLY | \
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+ EBC0_BNAP_PEN_DISABLED
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- mtebc(pb1ap, 0x00000000);
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- mtebc(pb1cr, 0x00000000);
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+#define EBC0_BNCR_SMALL_FLASH_CS0 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
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+ EBC0_BNCR_BS_1MB | \
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+ EBC0_BNCR_BU_RW | \
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+ EBC0_BNCR_BW_8BIT
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- mtebc(pb2ap, 0x04814500);
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- /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
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-#else
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- mtebc(pb0ap, 0x04055200); /* FLASH/SRAM */
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- mtebc(pb0cr, 0xfff18000); /* BAS=0xfe0 1MB r/w 8-bit */
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-#endif
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+#define EBC0_BNCR_SMALL_FLASH_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
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+ EBC0_BNCR_BS_8MB | \
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+ EBC0_BNCR_BU_RW | \
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+ EBC0_BNCR_BW_16BIT
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+
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+/* Large Flash or SRAM */
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+#define EBC0_BNAP_LARGE_FLASH_OR_SRAM EBC0_BNAP_BME_DISABLED | \
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+ EBC0_BNAP_TWT_ENCODE(8) | \
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+ EBC0_BNAP_CSN_ENCODE(0) | \
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+ EBC0_BNAP_OEN_ENCODE(1) | \
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+ EBC0_BNAP_WBN_ENCODE(1) | \
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+ EBC0_BNAP_WBF_ENCODE(1) | \
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+ EBC0_BNAP_TH_ENCODE(2) | \
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+ EBC0_BNAP_SOR_DELAYED | \
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+ EBC0_BNAP_BEM_RW | \
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+ EBC0_BNAP_PEN_DISABLED
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+
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+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
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+ EBC0_BNCR_BS_8MB | \
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+ EBC0_BNCR_BU_RW | \
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+ EBC0_BNCR_BW_16BIT
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+
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+
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+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
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+ EBC0_BNCR_BS_8MB | \
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+ EBC0_BNCR_BU_RW | \
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+ EBC0_BNCR_BW_16BIT
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- mtebc(pb3ap, 0x00000000);
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- mtebc(pb3cr, 0x00000000);
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+/* NVRAM - FPGA */
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+#define EBC0_BNAP_NVRAM_FPGA EBC0_BNAP_BME_DISABLED | \
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+ EBC0_BNAP_TWT_ENCODE(9) | \
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+ EBC0_BNAP_CSN_ENCODE(0) | \
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+ EBC0_BNAP_OEN_ENCODE(1) | \
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+ EBC0_BNAP_WBN_ENCODE(1) | \
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+ EBC0_BNAP_WBF_ENCODE(0) | \
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+ EBC0_BNAP_TH_ENCODE(2) | \
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+ EBC0_BNAP_RE_ENABLED | \
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+ EBC0_BNAP_SOR_DELAYED | \
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+ EBC0_BNAP_BEM_WRITEONLY | \
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+ EBC0_BNAP_PEN_DISABLED
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- mtebc(pb4ap, 0x00000000);
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- mtebc(pb4cr, 0x00000000);
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+#define EBC0_BNCR_NVRAM_FPGA_CS5 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
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+ EBC0_BNCR_BS_1MB | \
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+ EBC0_BNCR_BU_RW | \
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+ EBC0_BNCR_BW_8BIT
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- mtebc(pb5ap, 0x00000000);
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- mtebc(pb5cr, 0x00000000);
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+/* Nand Flash */
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+#define EBC0_BNAP_NAND_FLASH EBC0_BNAP_BME_DISABLED | \
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+ EBC0_BNAP_TWT_ENCODE(3) | \
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+ EBC0_BNAP_CSN_ENCODE(0) | \
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+ EBC0_BNAP_OEN_ENCODE(0) | \
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+ EBC0_BNAP_WBN_ENCODE(0) | \
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+ EBC0_BNAP_WBF_ENCODE(0) | \
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+ EBC0_BNAP_TH_ENCODE(1) | \
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+ EBC0_BNAP_RE_ENABLED | \
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+ EBC0_BNAP_SOR_NOT_DELAYED | \
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+ EBC0_BNAP_BEM_RW | \
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+ EBC0_BNAP_PEN_DISABLED
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+
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+
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+#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
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+
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+/* NAND0 */
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+#define EBC0_BNCR_NAND_FLASH_CS1 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
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+ EBC0_BNCR_BS_1MB | \
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+ EBC0_BNCR_BU_RW | \
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+ EBC0_BNCR_BW_32BIT
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+/* NAND1 - Bank2 */
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+#define EBC0_BNCR_NAND_FLASH_CS2 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
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+ EBC0_BNCR_BS_1MB | \
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+ EBC0_BNCR_BU_RW | \
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+ EBC0_BNCR_BW_32BIT
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+
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+/* NAND1 - Bank3 */
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+#define EBC0_BNCR_NAND_FLASH_CS3 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
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+ EBC0_BNCR_BS_1MB | \
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+ EBC0_BNCR_BU_RW | \
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+ EBC0_BNCR_BW_32BIT
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+
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+int board_early_init_f(void)
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+{
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+ ext_bus_cntlr_init();
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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@@ -81,52 +234,29 @@ int board_early_init_f(void)
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/*--------------------------------------------------------------------
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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- /*CPLD cs */
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- /*setup Address lines for flash sizes larger than 16Meg. */
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- out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
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- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
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- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
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-
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- /*setup emac */
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- out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
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- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
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- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
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- out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
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- out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
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-
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- /*UART1 */
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- out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
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- out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
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- out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
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-
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- /*setup USB 2.0 */
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- out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
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- out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
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- out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
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- out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
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- out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
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-
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- /*--------------------------------------------------------------------
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- * Setup other serial configuration
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- *-------------------------------------------------------------------*/
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- mfsdr(sdr_pci0, reg);
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- mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
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- mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
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- mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
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-
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-#if 0 /* test-only */
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- /*clear tmrclk divisor */
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- *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
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-
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- /*enable ethernet */
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- *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
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+ out32(GPIO0_OSRL, 0x00000400);
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+ out32(GPIO0_OSRH, 0x00000000);
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+ out32(GPIO0_TSRL, 0x00000400);
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+ out32(GPIO0_TSRH, 0x00000000);
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+ out32(GPIO0_ISR1L, 0x00000000);
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+ out32(GPIO0_ISR1H, 0x00000000);
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+ out32(GPIO0_ISR2L, 0x00000000);
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+ out32(GPIO0_ISR2H, 0x00000000);
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+ out32(GPIO0_ISR3L, 0x00000000);
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+ out32(GPIO0_ISR3H, 0x00000000);
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- /*enable usb 1.1 fs device and remove usb 2.0 reset */
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- *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
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+ out32(GPIO1_OSRL, 0x0C380000);
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+ out32(GPIO1_OSRH, 0x00000000);
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+ out32(GPIO1_TSRL, 0x0C380000);
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+ out32(GPIO1_TSRH, 0x00000000);
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+ out32(GPIO1_ISR1L, 0x0FC30000);
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+ out32(GPIO1_ISR1H, 0x00000000);
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+ out32(GPIO1_ISR2L, 0x0C010000);
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+ out32(GPIO1_ISR2H, 0x00000000);
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+ out32(GPIO1_ISR3L, 0x01400000);
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+ out32(GPIO1_ISR3H, 0x00000000);
|
|
|
|
|
|
- /*get rid of flash write protect */
|
|
|
- *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
|
|
|
-#endif
|
|
|
+ configure_ppc440ep_pins();
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
@@ -150,31 +280,35 @@ int checkboard(void)
|
|
|
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
|
|
|
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
|
|
|
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
|
|
|
+
|
|
|
return (0);
|
|
|
}
|
|
|
|
|
|
/*************************************************************************
|
|
|
- * sdram_init -- doesn't use serial presence detect.
|
|
|
*
|
|
|
- * Assumes: 256 MB, ECC, non-registered
|
|
|
+ * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
|
|
|
+ *
|
|
|
+ * Fixed memory is composed of :
|
|
|
+ * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
|
|
|
+ * 13 row add bits, 10 column add bits (but 12 row used only).
|
|
|
+ * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
|
|
|
+ * 12 row add bits, 10 column add bits.
|
|
|
+ * Prepare a subset (only the used ones) of SPD data
|
|
|
+ *
|
|
|
+ * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
|
|
|
+ * the corresponding bank is divided by 2 due to number of Row addresses
|
|
|
+ * 12 in the ECC module
|
|
|
+ *
|
|
|
+ * Assumes: 64 MB, ECC, non-registered
|
|
|
* PLB @ 133 MHz
|
|
|
*
|
|
|
************************************************************************/
|
|
|
-void sdram_init(void)
|
|
|
+void fixed_sdram_init(void)
|
|
|
{
|
|
|
- register uint reg;
|
|
|
-
|
|
|
- /*--------------------------------------------------------------------
|
|
|
- * Setup some default
|
|
|
- *------------------------------------------------------------------*/
|
|
|
- mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
|
|
|
- mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
|
|
|
- mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
|
|
|
- mtsdram(mem_clktr, 0x40000000); /* ?? */
|
|
|
- mtsdram(mem_wddctr, 0x40000000); /* ?? */
|
|
|
-
|
|
|
- /*clear this first, if the DDR is enabled by a debugger
|
|
|
- then you can not make changes. */
|
|
|
+ /*
|
|
|
+ * clear this first, if the DDR is enabled by a debugger
|
|
|
+ * then you can not make changes.
|
|
|
+ */
|
|
|
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
|
|
|
|
|
|
/*--------------------------------------------------------------------
|
|
|
@@ -183,36 +317,23 @@ void sdram_init(void)
|
|
|
/*
|
|
|
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
|
|
*/
|
|
|
- mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
|
|
|
- mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
|
|
|
-
|
|
|
- mtsdram(mem_tr0, 0x410a4012); /* ?? */
|
|
|
- mtsdram(mem_tr1, 0x8080080b); /* ?? */
|
|
|
- mtsdram(mem_rtr, 0x04080000); /* ?? */
|
|
|
- mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
|
|
|
- mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
|
|
|
- udelay(400); /* Delay 200 usecs (min) */
|
|
|
-
|
|
|
- /*--------------------------------------------------------------------
|
|
|
- * Enable the controller, then wait for DCEN to complete
|
|
|
- *------------------------------------------------------------------*/
|
|
|
- mtsdram(mem_cfg0, 0x84000000); /* Enable */
|
|
|
-
|
|
|
- for (;;) {
|
|
|
- mfsdram(mem_mcsts, reg);
|
|
|
- if (reg & 0x80000000)
|
|
|
- break;
|
|
|
- }
|
|
|
+ mtsdram(mem_b0cr, 0x00082001);
|
|
|
+ mtsdram(mem_b1cr, 0x00000000);
|
|
|
+ mtsdram(mem_b2cr, 0x00000000);
|
|
|
+ mtsdram(mem_b3cr, 0x00000000);
|
|
|
}
|
|
|
|
|
|
-/*************************************************************************
|
|
|
- * long int initdram
|
|
|
- *
|
|
|
- ************************************************************************/
|
|
|
-long int initdram(int board)
|
|
|
+long int initdram (int board_type)
|
|
|
{
|
|
|
- sdram_init();
|
|
|
- return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
|
|
|
+ long dram_size = 0;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * First init bank0 (onboard sdram) and then configure the DIMM-slots
|
|
|
+ */
|
|
|
+ fixed_sdram_init();
|
|
|
+ dram_size = spd_sdram (0);
|
|
|
+
|
|
|
+ return dram_size;
|
|
|
}
|
|
|
|
|
|
#if defined(CFG_DRAM_TEST)
|
|
|
@@ -425,15 +546,1450 @@ int is_pci_host(struct pci_controller *hose)
|
|
|
}
|
|
|
#endif /* defined(CONFIG_PCI) */
|
|
|
|
|
|
-/*************************************************************************
|
|
|
- * hw_watchdog_reset
|
|
|
- *
|
|
|
- * This routine is called to reset (keep alive) the watchdog timer
|
|
|
- *
|
|
|
- ************************************************************************/
|
|
|
-#if defined(CONFIG_HW_WATCHDOG)
|
|
|
-void hw_watchdog_reset(void)
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | is_powerpc440ep_pass1.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+int is_powerpc440ep_pass1(void)
|
|
|
+{
|
|
|
+ unsigned long pvr;
|
|
|
+
|
|
|
+ pvr = get_pvr();
|
|
|
+
|
|
|
+ if (pvr == PVR_POWERPC_440EP_PASS1)
|
|
|
+ return TRUE;
|
|
|
+ else if (pvr == PVR_POWERPC_440EP_PASS2)
|
|
|
+ return FALSE;
|
|
|
+ else {
|
|
|
+ printf("brdutil error 3\n");
|
|
|
+ for (;;)
|
|
|
+ ;
|
|
|
+ }
|
|
|
+
|
|
|
+ return(FALSE);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | is_nand_selected.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+int is_nand_selected(void)
|
|
|
+{
|
|
|
+ return FALSE; /* test-only */
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | config_on_ebc_cs4_is_small_flash => from EPLD
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+unsigned char config_on_ebc_cs4_is_small_flash(void)
|
|
|
+{
|
|
|
+ /* Not implemented yet => returns constant value */
|
|
|
+ return TRUE;
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | Ext_bus_cntlr_init.
|
|
|
+ | Initialize the external bus controller
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void ext_bus_cntlr_init(void)
|
|
|
+{
|
|
|
+ unsigned long sdr0_pstrp0, sdr0_sdstp1;
|
|
|
+ unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
|
|
|
+ int computed_boot_device = BOOT_DEVICE_UNKNOWN;
|
|
|
+ unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
|
|
|
+ unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
|
|
|
+ unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
|
|
|
+ unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
|
|
|
+ unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
|
|
|
+
|
|
|
+
|
|
|
+ /*-------------------------------------------------------------------------+
|
|
|
+ |
|
|
|
+ | PART 1 : Initialize EBC Bank 5
|
|
|
+ | ==============================
|
|
|
+ | Bank5 is always associated to the NVRAM/EPLD.
|
|
|
+ | It has to be initialized prior to other banks settings computation since
|
|
|
+ | some board registers values may be needed
|
|
|
+ |
|
|
|
+ +-------------------------------------------------------------------------*/
|
|
|
+ /* NVRAM - FPGA */
|
|
|
+ mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
|
|
|
+ mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
|
|
|
+
|
|
|
+ /*-------------------------------------------------------------------------+
|
|
|
+ |
|
|
|
+ | PART 2 : Determine which boot device was selected
|
|
|
+ | =========================================
|
|
|
+ |
|
|
|
+ | Read Pin Strap Register in PPC440EP
|
|
|
+ | In case of boot from IIC, read Serial Device Strap Register1
|
|
|
+ |
|
|
|
+ | Result can either be :
|
|
|
+ | - Boot from EBC 8bits => SMALL FLASH
|
|
|
+ | - Boot from EBC 16bits => Large Flash or SRAM
|
|
|
+ | - Boot from NAND Flash
|
|
|
+ | - Boot from PCI
|
|
|
+ |
|
|
|
+ +-------------------------------------------------------------------------*/
|
|
|
+ /* Read Pin Strap Register in PPC440EP */
|
|
|
+ mfsdr(sdr_pstrp0, sdr0_pstrp0);
|
|
|
+ bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
|
|
|
+
|
|
|
+ /*-------------------------------------------------------------------------+
|
|
|
+ | PPC440EP Pass1
|
|
|
+ +-------------------------------------------------------------------------*/
|
|
|
+ if (is_powerpc440ep_pass1() == TRUE) {
|
|
|
+ switch(bootstrap_settings) {
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
|
|
|
+ /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
|
|
|
+ /* Boot from Small Flash */
|
|
|
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
|
|
|
+ break;
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
|
|
|
+ /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
|
|
|
+ /* Boot from PCI */
|
|
|
+ computed_boot_device = BOOT_FROM_PCI;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
|
|
|
+ /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
|
|
|
+ /* Boot from Nand Flash */
|
|
|
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
|
|
|
+ /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
|
|
|
+ /* Boot from Small Flash */
|
|
|
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
|
|
|
+ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
|
|
|
+ /* Read Serial Device Strap Register1 in PPC440EP */
|
|
|
+ mfsdr(sdr_sdstp1, sdr0_sdstp1);
|
|
|
+ boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
|
|
|
+ ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
|
|
|
+
|
|
|
+ switch(boot_selection) {
|
|
|
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
|
|
|
+ switch(ebc_boot_size) {
|
|
|
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
|
|
|
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
|
|
|
+ break;
|
|
|
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
|
|
|
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
|
|
|
+ computed_boot_device = BOOT_FROM_PCI;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
|
|
|
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /*-------------------------------------------------------------------------+
|
|
|
+ | PPC440EP Pass2
|
|
|
+ +-------------------------------------------------------------------------*/
|
|
|
+ else {
|
|
|
+ switch(bootstrap_settings) {
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
|
|
|
+ /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
|
|
|
+ /* Boot from Small Flash */
|
|
|
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
|
|
|
+ break;
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
|
|
|
+ /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
|
|
|
+ /* Boot from PCI */
|
|
|
+ computed_boot_device = BOOT_FROM_PCI;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
|
|
|
+ /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
|
|
|
+ /* Boot from Nand Flash */
|
|
|
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
|
|
|
+ /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
|
|
|
+ /* Boot from Large Flash or SRAM */
|
|
|
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
|
|
|
+ /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
|
|
|
+ /* Boot from Large Flash or SRAM */
|
|
|
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
|
|
|
+ /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
|
|
|
+ /* Boot from PCI */
|
|
|
+ computed_boot_device = BOOT_FROM_PCI;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
|
|
|
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
|
|
|
+ /* Default Strap Settings 5-7 */
|
|
|
+ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
|
|
|
+ /* Read Serial Device Strap Register1 in PPC440EP */
|
|
|
+ mfsdr(sdr_sdstp1, sdr0_sdstp1);
|
|
|
+ boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
|
|
|
+ ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
|
|
|
+
|
|
|
+ switch(boot_selection) {
|
|
|
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
|
|
|
+ switch(ebc_boot_size) {
|
|
|
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
|
|
|
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
|
|
|
+ break;
|
|
|
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
|
|
|
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
|
|
|
+ computed_boot_device = BOOT_FROM_PCI;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
|
|
|
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /*-------------------------------------------------------------------------+
|
|
|
+ |
|
|
|
+ | PART 3 : Compute EBC settings depending on selected boot device
|
|
|
+ | ====== ======================================================
|
|
|
+ |
|
|
|
+ | Resulting EBC init will be among following configurations :
|
|
|
+ |
|
|
|
+ | - Boot from EBC 8bits => boot from SMALL FLASH selected
|
|
|
+ | EBC-CS0 = Small Flash
|
|
|
+ | EBC-CS1,2,3 = NAND Flash or
|
|
|
+ | Exp.Slot depending on Soft Config
|
|
|
+ | EBC-CS4 = SRAM/Large Flash or
|
|
|
+ | Large Flash/SRAM depending on jumpers
|
|
|
+ | EBC-CS5 = NVRAM / EPLD
|
|
|
+ |
|
|
|
+ | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
|
|
|
+ | EBC-CS0 = SRAM/Large Flash or
|
|
|
+ | Large Flash/SRAM depending on jumpers
|
|
|
+ | EBC-CS1,2,3 = NAND Flash or
|
|
|
+ | Exp.Slot depending on Software Configuration
|
|
|
+ | EBC-CS4 = Small Flash
|
|
|
+ | EBC-CS5 = NVRAM / EPLD
|
|
|
+ |
|
|
|
+ | - Boot from NAND Flash
|
|
|
+ | EBC-CS0 = NAND Flash0
|
|
|
+ | EBC-CS1,2,3 = NAND Flash1
|
|
|
+ | EBC-CS4 = SRAM/Large Flash or
|
|
|
+ | Large Flash/SRAM depending on jumpers
|
|
|
+ | EBC-CS5 = NVRAM / EPLD
|
|
|
+ |
|
|
|
+ | - Boot from PCI
|
|
|
+ | EBC-CS0 = ...
|
|
|
+ | EBC-CS1,2,3 = NAND Flash or
|
|
|
+ | Exp.Slot depending on Software Configuration
|
|
|
+ | EBC-CS4 = SRAM/Large Flash or
|
|
|
+ | Large Flash/SRAM or
|
|
|
+ | Small Flash depending on jumpers
|
|
|
+ | EBC-CS5 = NVRAM / EPLD
|
|
|
+ |
|
|
|
+ +-------------------------------------------------------------------------*/
|
|
|
+
|
|
|
+ switch(computed_boot_device) {
|
|
|
+ /*------------------------------------------------------------------------- */
|
|
|
+ case BOOT_FROM_SMALL_FLASH:
|
|
|
+ /*------------------------------------------------------------------------- */
|
|
|
+ ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
|
|
|
+ ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
|
|
|
+ if ((is_nand_selected()) == TRUE) {
|
|
|
+ /* NAND Flash */
|
|
|
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
|
|
|
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
|
|
|
+ /*ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
|
|
|
+ ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
|
|
|
+ ebc0_cs3_bnap_value = EBC0_BNAP_NAND_FLASH;
|
|
|
+ ebc0_cs3_bncr_value = EBC0_BNCR_NAND_FLASH_CS3;*/
|
|
|
+ ebc0_cs2_bnap_value = 0;
|
|
|
+ ebc0_cs2_bncr_value = 0;
|
|
|
+ ebc0_cs3_bnap_value = 0;
|
|
|
+ ebc0_cs3_bncr_value = 0;
|
|
|
+ } else {
|
|
|
+ /* Expansion Slot */
|
|
|
+ ebc0_cs1_bnap_value = 0;
|
|
|
+ ebc0_cs1_bncr_value = 0;
|
|
|
+ ebc0_cs2_bnap_value = 0;
|
|
|
+ ebc0_cs2_bncr_value = 0;
|
|
|
+ ebc0_cs3_bnap_value = 0;
|
|
|
+ ebc0_cs3_bncr_value = 0;
|
|
|
+ }
|
|
|
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
|
|
|
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ /*------------------------------------------------------------------------- */
|
|
|
+ case BOOT_FROM_LARGE_FLASH_OR_SRAM:
|
|
|
+ /*------------------------------------------------------------------------- */
|
|
|
+ ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
|
|
|
+ ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
|
|
|
+ if ((is_nand_selected()) == TRUE) {
|
|
|
+ /* NAND Flash */
|
|
|
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
|
|
|
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
|
|
|
+ ebc0_cs2_bnap_value = 0;
|
|
|
+ ebc0_cs2_bncr_value = 0;
|
|
|
+ ebc0_cs3_bnap_value = 0;
|
|
|
+ ebc0_cs3_bncr_value = 0;
|
|
|
+ } else {
|
|
|
+ /* Expansion Slot */
|
|
|
+ ebc0_cs1_bnap_value = 0;
|
|
|
+ ebc0_cs1_bncr_value = 0;
|
|
|
+ ebc0_cs2_bnap_value = 0;
|
|
|
+ ebc0_cs2_bncr_value = 0;
|
|
|
+ ebc0_cs3_bnap_value = 0;
|
|
|
+ ebc0_cs3_bncr_value = 0;
|
|
|
+ }
|
|
|
+ ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
|
|
|
+ ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ /*------------------------------------------------------------------------- */
|
|
|
+ case BOOT_FROM_NAND_FLASH0:
|
|
|
+ /*------------------------------------------------------------------------- */
|
|
|
+ ebc0_cs0_bnap_value = 0;
|
|
|
+ ebc0_cs0_bncr_value = 0;
|
|
|
+
|
|
|
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
|
|
|
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
|
|
|
+ ebc0_cs2_bnap_value = 0;
|
|
|
+ ebc0_cs2_bncr_value = 0;
|
|
|
+ ebc0_cs3_bnap_value = 0;
|
|
|
+ ebc0_cs3_bncr_value = 0;
|
|
|
+
|
|
|
+ /* Large Flash or SRAM */
|
|
|
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
|
|
|
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ /*------------------------------------------------------------------------- */
|
|
|
+ case BOOT_FROM_PCI:
|
|
|
+ /*------------------------------------------------------------------------- */
|
|
|
+ ebc0_cs0_bnap_value = 0;
|
|
|
+ ebc0_cs0_bncr_value = 0;
|
|
|
+
|
|
|
+ if ((is_nand_selected()) == TRUE) {
|
|
|
+ /* NAND Flash */
|
|
|
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
|
|
|
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
|
|
|
+ ebc0_cs2_bnap_value = 0;
|
|
|
+ ebc0_cs2_bncr_value = 0;
|
|
|
+ ebc0_cs3_bnap_value = 0;
|
|
|
+ ebc0_cs3_bncr_value = 0;
|
|
|
+ } else {
|
|
|
+ /* Expansion Slot */
|
|
|
+ ebc0_cs1_bnap_value = 0;
|
|
|
+ ebc0_cs1_bncr_value = 0;
|
|
|
+ ebc0_cs2_bnap_value = 0;
|
|
|
+ ebc0_cs2_bncr_value = 0;
|
|
|
+ ebc0_cs3_bnap_value = 0;
|
|
|
+ ebc0_cs3_bncr_value = 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
|
|
|
+ /* Small Flash */
|
|
|
+ ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
|
|
|
+ ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
|
|
|
+ } else {
|
|
|
+ /* Large Flash or SRAM */
|
|
|
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
|
|
|
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
|
|
|
+ }
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ /*------------------------------------------------------------------------- */
|
|
|
+ case BOOT_DEVICE_UNKNOWN:
|
|
|
+ /*------------------------------------------------------------------------- */
|
|
|
+ /* Error */
|
|
|
+ break;
|
|
|
+
|
|
|
+ }
|
|
|
+
|
|
|
+
|
|
|
+ /*-------------------------------------------------------------------------+
|
|
|
+ | Initialize EBC CONFIG
|
|
|
+ +-------------------------------------------------------------------------*/
|
|
|
+ mtdcr(ebccfga, xbcfg);
|
|
|
+ mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
|
|
|
+ EBC0_CFG_PTD_ENABLED |
|
|
|
+ EBC0_CFG_RTC_2048PERCLK |
|
|
|
+ EBC0_CFG_EMPL_LOW |
|
|
|
+ EBC0_CFG_EMPH_LOW |
|
|
|
+ EBC0_CFG_CSTC_DRIVEN |
|
|
|
+ EBC0_CFG_BPF_ONEDW |
|
|
|
+ EBC0_CFG_EMS_8BIT |
|
|
|
+ EBC0_CFG_PME_DISABLED |
|
|
|
+ EBC0_CFG_PMT_ENCODE(0) );
|
|
|
+
|
|
|
+ /*-------------------------------------------------------------------------+
|
|
|
+ | Initialize EBC Bank 0-4
|
|
|
+ +-------------------------------------------------------------------------*/
|
|
|
+ /* EBC Bank0 */
|
|
|
+ mtebc(pb0ap, ebc0_cs0_bnap_value);
|
|
|
+ mtebc(pb0cr, ebc0_cs0_bncr_value);
|
|
|
+ /* EBC Bank1 */
|
|
|
+ mtebc(pb1ap, ebc0_cs1_bnap_value);
|
|
|
+ mtebc(pb1cr, ebc0_cs1_bncr_value);
|
|
|
+ /* EBC Bank2 */
|
|
|
+ mtebc(pb2ap, ebc0_cs2_bnap_value);
|
|
|
+ mtebc(pb2cr, ebc0_cs2_bncr_value);
|
|
|
+ /* EBC Bank3 */
|
|
|
+ mtebc(pb3ap, ebc0_cs3_bnap_value);
|
|
|
+ mtebc(pb3cr, ebc0_cs3_bncr_value);
|
|
|
+ /* EBC Bank4 */
|
|
|
+ mtebc(pb4ap, ebc0_cs4_bnap_value);
|
|
|
+ mtebc(pb4cr, ebc0_cs4_bncr_value);
|
|
|
+
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | get_uart_configuration.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+uart_config_nb_t get_uart_configuration(void)
|
|
|
{
|
|
|
+ return (L4); /* test-only */
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | set_phy_configuration_through_fpga => to EPLD
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void set_phy_configuration_through_fpga(zmii_config_t config)
|
|
|
+{
|
|
|
+
|
|
|
+ unsigned long fpga_selection_reg;
|
|
|
+
|
|
|
+ fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
|
|
|
+
|
|
|
+ switch(config)
|
|
|
+ {
|
|
|
+ case ZMII_CONFIGURATION_IS_MII:
|
|
|
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
|
|
|
+ break;
|
|
|
+ case ZMII_CONFIGURATION_IS_RMII:
|
|
|
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
|
|
|
+ break;
|
|
|
+ case ZMII_CONFIGURATION_IS_SMII:
|
|
|
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
|
|
|
+ break;
|
|
|
+ case ZMII_CONFIGURATION_UNKNOWN:
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
|
|
|
|
|
|
}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | scp_selection_in_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void scp_selection_in_fpga(void)
|
|
|
+{
|
|
|
+ unsigned long fpga_selection_2_reg;
|
|
|
+
|
|
|
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
|
|
|
+ fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
|
|
|
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | iic1_selection_in_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void iic1_selection_in_fpga(void)
|
|
|
+{
|
|
|
+ unsigned long fpga_selection_2_reg;
|
|
|
+
|
|
|
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
|
|
|
+ fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
|
|
|
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | dma_a_b_selection_in_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void dma_a_b_selection_in_fpga(void)
|
|
|
+{
|
|
|
+ unsigned long fpga_selection_2_reg;
|
|
|
+
|
|
|
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
|
|
|
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | dma_a_b_unselect_in_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void dma_a_b_unselect_in_fpga(void)
|
|
|
+{
|
|
|
+ unsigned long fpga_selection_2_reg;
|
|
|
+
|
|
|
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
|
|
|
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | dma_c_d_selection_in_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void dma_c_d_selection_in_fpga(void)
|
|
|
+{
|
|
|
+ unsigned long fpga_selection_2_reg;
|
|
|
+
|
|
|
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
|
|
|
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | dma_c_d_unselect_in_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void dma_c_d_unselect_in_fpga(void)
|
|
|
+{
|
|
|
+ unsigned long fpga_selection_2_reg;
|
|
|
+
|
|
|
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
|
|
|
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | usb2_device_selection_in_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void usb2_device_selection_in_fpga(void)
|
|
|
+{
|
|
|
+ unsigned long fpga_selection_1_reg;
|
|
|
+
|
|
|
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
|
|
|
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | usb2_device_reset_through_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void usb2_device_reset_through_fpga(void)
|
|
|
+{
|
|
|
+ /* Perform soft Reset pulse */
|
|
|
+ unsigned long fpga_reset_reg;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ fpga_reset_reg = in8(FPGA_RESET_REG);
|
|
|
+ out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
|
|
|
+ for (i=0; i<500; i++)
|
|
|
+ udelay(1000);
|
|
|
+ out8(FPGA_RESET_REG,fpga_reset_reg);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | usb2_host_selection_in_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void usb2_host_selection_in_fpga(void)
|
|
|
+{
|
|
|
+ unsigned long fpga_selection_1_reg;
|
|
|
+
|
|
|
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
|
|
|
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | ndfc_selection_in_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void ndfc_selection_in_fpga(void)
|
|
|
+{
|
|
|
+ unsigned long fpga_selection_1_reg;
|
|
|
+
|
|
|
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
|
|
|
+ fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
|
|
|
+ /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; */
|
|
|
+ /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3; */
|
|
|
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | uart_selection_in_fpga.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void uart_selection_in_fpga(uart_config_nb_t uart_config)
|
|
|
+{
|
|
|
+ /* FPGA register */
|
|
|
+ unsigned char fpga_selection_3_reg;
|
|
|
+
|
|
|
+ /* Read FPGA Reagister */
|
|
|
+ fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
|
|
|
+
|
|
|
+ switch (uart_config)
|
|
|
+ {
|
|
|
+ case L1:
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* L1 configuration: UART0 = 8 pins */
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* Configure FPGA */
|
|
|
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
|
|
|
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
|
|
|
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ case L2:
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* L2 configuration: UART0 = 4 pins */
|
|
|
+ /* UART1 = 4 pins */
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* Configure FPGA */
|
|
|
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
|
|
|
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
|
|
|
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ case L3:
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* L3 configuration: UART0 = 4 pins */
|
|
|
+ /* UART1 = 2 pins */
|
|
|
+ /* UART2 = 2 pins */
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* Configure FPGA */
|
|
|
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
|
|
|
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
|
|
|
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
|
|
|
+ break;
|
|
|
+
|
|
|
+ case L4:
|
|
|
+ /* Configure FPGA */
|
|
|
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
|
|
|
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
|
|
|
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ default:
|
|
|
+ /* Unsupported UART configuration number */
|
|
|
+ for (;;)
|
|
|
+ ;
|
|
|
+ break;
|
|
|
+
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | init_default_gpio
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void init_default_gpio(void)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+
|
|
|
+ /* Init GPIO0 */
|
|
|
+ for(i=0; i<GPIO_MAX; i++)
|
|
|
+ {
|
|
|
+ gpio_tab[GPIO0][i].add = GPIO0_BASE;
|
|
|
+ gpio_tab[GPIO0][i].in_out = GPIO_DIS;
|
|
|
+ gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Init GPIO1 */
|
|
|
+ for(i=0; i<GPIO_MAX; i++)
|
|
|
+ {
|
|
|
+ gpio_tab[GPIO1][i].add = GPIO1_BASE;
|
|
|
+ gpio_tab[GPIO1][i].in_out = GPIO_DIS;
|
|
|
+ gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* EBC_CS_N(5) - GPIO0_10 */
|
|
|
+ gpio_tab[GPIO0][10].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ /* EBC_CS_N(4) - GPIO0_9 */
|
|
|
+ gpio_tab[GPIO0][9].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | update_uart_ios
|
|
|
+ +------------------------------------------------------------------------------
|
|
|
+ |
|
|
|
+ | Set UART Configuration in PowerPC440EP
|
|
|
+ |
|
|
|
+ | +---------------------------------------------------------------------+
|
|
|
+ | | Configuartion | Connector | Nb of pins | Pins | Associated |
|
|
|
+ | | Number | Port Name | available | naming | CORE |
|
|
|
+ | +-----------------+---------------+------------+--------+-------------+
|
|
|
+ | | L1 | Port_A | 8 | UART | UART core 0 |
|
|
|
+ | +-----------------+---------------+------------+--------+-------------+
|
|
|
+ | | L2 | Port_A | 4 | UART1 | UART core 0 |
|
|
|
+ | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
|
|
|
+ | +-----------------+---------------+------------+--------+-------------+
|
|
|
+ | | L3 | Port_A | 4 | UART1 | UART core 0 |
|
|
|
+ | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
|
|
|
+ | | | Port_C | 2 | UART3 | UART core 2 |
|
|
|
+ | +-----------------+---------------+------------+--------+-------------+
|
|
|
+ | | | Port_A | 2 | UART1 | UART core 0 |
|
|
|
+ | | L4 | Port_B | 2 | UART2 | UART core 1 |
|
|
|
+ | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
|
|
|
+ | | | Port_D | 2 | UART4 | UART core 3 |
|
|
|
+ | +-----------------+---------------+------------+--------+-------------+
|
|
|
+ |
|
|
|
+ | Involved GPIOs
|
|
|
+ |
|
|
|
+ | +------------------------------------------------------------------------------+
|
|
|
+ | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
|
|
|
+ | +---------+------------------+-----+-----------------+-----+-------------+-----+
|
|
|
+ | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
|
|
|
+ | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
|
|
|
+ | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
|
|
|
+ | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
|
|
|
+ | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
|
|
|
+ | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
|
|
|
+ | +------------------------------------------------------------------------------+
|
|
|
+ |
|
|
|
+ |
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+
|
|
|
+void update_uart_ios(uart_config_nb_t uart_config)
|
|
|
+{
|
|
|
+ switch (uart_config)
|
|
|
+ {
|
|
|
+ case L1:
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* L1 configuration: UART0 = 8 pins */
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* Update GPIO Configuration Table */
|
|
|
+ gpio_tab[GPIO1][2].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ case L2:
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* L2 configuration: UART0 = 4 pins */
|
|
|
+ /* UART1 = 4 pins */
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* Update GPIO Configuration Table */
|
|
|
+ gpio_tab[GPIO1][2].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][3].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ case L3:
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* L3 configuration: UART0 = 4 pins */
|
|
|
+ /* UART1 = 2 pins */
|
|
|
+ /* UART2 = 2 pins */
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* Update GPIO Configuration Table */
|
|
|
+ gpio_tab[GPIO1][2].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ case L4:
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* L4 configuration: UART0 = 2 pins */
|
|
|
+ /* UART1 = 2 pins */
|
|
|
+ /* UART2 = 2 pins */
|
|
|
+ /* UART3 = 2 pins */
|
|
|
+ /* ----------------------------------------------------------------------- */
|
|
|
+ /* Update GPIO Configuration Table */
|
|
|
+ gpio_tab[GPIO1][2].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
|
|
|
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
|
|
|
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ break;
|
|
|
+
|
|
|
+ default:
|
|
|
+ /* Unsupported UART configuration number */
|
|
|
+ printf("ERROR - Unsupported UART configuration number.\n\n");
|
|
|
+ for (;;)
|
|
|
+ ;
|
|
|
+ break;
|
|
|
+
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set input Selection Register on Alt_Receive for UART Input Core */
|
|
|
+ out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
|
|
|
+ out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
|
|
|
+ out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | update_ndfc_ios(void).
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void update_ndfc_ios(void)
|
|
|
+{
|
|
|
+ /* Update GPIO Configuration Table */
|
|
|
+ gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
|
|
|
+ gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+#if 0
|
|
|
+ gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
|
|
|
+ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
|
|
|
+ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
|
|
|
#endif
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | update_zii_ios(void).
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void update_zii_ios(void)
|
|
|
+{
|
|
|
+ /* Update GPIO Configuration Table */
|
|
|
+ gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
|
|
|
+ gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
|
|
|
+ gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
|
|
|
+ gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
|
|
|
+ gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
|
|
|
+ gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
|
|
|
+ gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
|
|
|
+ gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
|
|
|
+ gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
|
|
|
+ gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
|
|
|
+ gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
|
|
|
+ gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
|
|
|
+ gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
|
|
|
+ gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
|
|
|
+ gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | update_uic_0_3_irq_ios().
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void update_uic_0_3_irq_ios(void)
|
|
|
+{
|
|
|
+ gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
|
|
|
+ gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
|
|
|
+ gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
|
|
|
+ gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
|
|
|
+ gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | update_uic_4_9_irq_ios().
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void update_uic_4_9_irq_ios(void)
|
|
|
+{
|
|
|
+ gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
|
|
|
+ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
|
|
|
+ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
|
|
|
+ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
|
|
|
+ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
|
|
|
+ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | update_dma_a_b_ios().
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void update_dma_a_b_ios(void)
|
|
|
+{
|
|
|
+ gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
|
|
|
+ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
|
|
|
+ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
|
|
|
+ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
|
|
|
+ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
|
|
|
+ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | update_dma_c_d_ios().
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void update_dma_c_d_ios(void)
|
|
|
+{
|
|
|
+ gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
|
|
|
+ gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
|
|
|
+ gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
|
|
|
+ gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
|
|
|
+ gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
|
|
|
+ gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
|
|
|
+ gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | update_ebc_master_ios().
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void update_ebc_master_ios(void)
|
|
|
+{
|
|
|
+ gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
|
|
|
+ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
|
|
|
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
|
|
|
+ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
|
|
|
+ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | update_usb2_device_ios().
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void update_usb2_device_ios(void)
|
|
|
+{
|
|
|
+ gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
|
|
|
+ gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
|
|
|
+ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
|
|
|
+ gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
|
|
|
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
|
|
|
+ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
|
|
|
+ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
|
|
|
+ gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+ gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
|
|
|
+ gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | update_pci_patch_ios().
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void update_pci_patch_ios(void)
|
|
|
+{
|
|
|
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
|
|
|
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | set_chip_gpio_configuration(unsigned char gpio_core)
|
|
|
+ | Put the core impacted by clock modification and sharing in reset.
|
|
|
+ | Config the select registers to resolve the sharing depending of the config.
|
|
|
+ | Configure the GPIO registers.
|
|
|
+ |
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void set_chip_gpio_configuration(unsigned char gpio_core)
|
|
|
+{
|
|
|
+ unsigned char i=0, j=0, reg_offset = 0;
|
|
|
+ unsigned long gpio_reg, gpio_core_add;
|
|
|
+
|
|
|
+ /* GPIO config of the GPIOs 0 to 31 */
|
|
|
+ for (i=0; i<GPIO_MAX; i++, j++)
|
|
|
+ {
|
|
|
+ if (i == GPIO_MAX/2)
|
|
|
+ {
|
|
|
+ reg_offset = 4;
|
|
|
+ j = i-16;
|
|
|
+ }
|
|
|
+
|
|
|
+ gpio_core_add = gpio_tab[gpio_core][i].add;
|
|
|
+
|
|
|
+ if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
|
|
|
+ (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
|
|
|
+ {
|
|
|
+ switch (gpio_tab[gpio_core][i].alt_nb)
|
|
|
+ {
|
|
|
+ case GPIO_SEL:
|
|
|
+ break;
|
|
|
+
|
|
|
+ case GPIO_ALT1:
|
|
|
+ gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
|
|
|
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
|
|
|
+ out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
|
|
|
+ break;
|
|
|
+
|
|
|
+ case GPIO_ALT2:
|
|
|
+ gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
|
|
|
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
|
|
|
+ out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
|
|
|
+ break;
|
|
|
+
|
|
|
+ case GPIO_ALT3:
|
|
|
+ gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
|
|
|
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
|
|
|
+ out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
|
|
|
+ (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
|
|
|
+ {
|
|
|
+
|
|
|
+ switch (gpio_tab[gpio_core][i].alt_nb)
|
|
|
+ {
|
|
|
+ case GPIO_SEL:
|
|
|
+ break;
|
|
|
+ case GPIO_ALT1:
|
|
|
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
|
|
|
+ gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
|
|
|
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
|
|
|
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
|
|
|
+ gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
|
|
|
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
|
|
|
+ break;
|
|
|
+ case GPIO_ALT2:
|
|
|
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
|
|
|
+ gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
|
|
|
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
|
|
|
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
|
|
|
+ gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
|
|
|
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
|
|
|
+ break;
|
|
|
+ case GPIO_ALT3:
|
|
|
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
|
|
|
+ gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
|
|
|
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
|
|
|
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
|
|
|
+ gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
|
|
|
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | force_bup_core_selection.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
|
|
|
+{
|
|
|
+ /* Pointer invalid */
|
|
|
+ if (core_select_P == NULL)
|
|
|
+ {
|
|
|
+ printf("Configuration invalid pointer 1\n");
|
|
|
+ for (;;)
|
|
|
+ ;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* L4 Selection */
|
|
|
+ *(core_select_P+UART_CORE0) = CORE_SELECTED;
|
|
|
+ *(core_select_P+UART_CORE1) = CORE_SELECTED;
|
|
|
+ *(core_select_P+UART_CORE2) = CORE_SELECTED;
|
|
|
+ *(core_select_P+UART_CORE3) = CORE_SELECTED;
|
|
|
+
|
|
|
+ /* RMII Selection */
|
|
|
+ *(core_select_P+RMII_SEL) = CORE_SELECTED;
|
|
|
+
|
|
|
+ /* External Interrupt 0-9 selection */
|
|
|
+ *(core_select_P+UIC_0_3) = CORE_SELECTED;
|
|
|
+ *(core_select_P+UIC_4_9) = CORE_SELECTED;
|
|
|
+
|
|
|
+ *(core_select_P+SCP_CORE) = CORE_SELECTED;
|
|
|
+ *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
|
|
|
+ *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
|
|
|
+ *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
|
|
|
+
|
|
|
+ *config_val_P = CONFIG_IS_VALID;
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------+
|
|
|
+ | configure_ppc440ep_pins.
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+void configure_ppc440ep_pins(void)
|
|
|
+{
|
|
|
+ uart_config_nb_t uart_configuration;
|
|
|
+ config_validity_t config_val = CONFIG_IS_INVALID;
|
|
|
+
|
|
|
+ /* Create Core Selection Table */
|
|
|
+ core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
|
|
|
+ {
|
|
|
+ CORE_NOT_SELECTED, /* IIC_CORE, */
|
|
|
+ CORE_NOT_SELECTED, /* SPC_CORE, */
|
|
|
+ CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
|
|
|
+ CORE_NOT_SELECTED, /* UIC_4_9, */
|
|
|
+ CORE_NOT_SELECTED, /* USB2_HOST, */
|
|
|
+ CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
|
|
|
+ CORE_NOT_SELECTED, /* USB2_DEVICE, */
|
|
|
+ CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
|
|
|
+ CORE_NOT_SELECTED, /* USB1_DEVICE, */
|
|
|
+ CORE_NOT_SELECTED, /* EBC_MASTER, */
|
|
|
+ CORE_NOT_SELECTED, /* NAND_FLASH, */
|
|
|
+ CORE_NOT_SELECTED, /* UART_CORE0, */
|
|
|
+ CORE_NOT_SELECTED, /* UART_CORE1, */
|
|
|
+ CORE_NOT_SELECTED, /* UART_CORE2, */
|
|
|
+ CORE_NOT_SELECTED, /* UART_CORE3, */
|
|
|
+ CORE_NOT_SELECTED, /* MII_SEL, */
|
|
|
+ CORE_NOT_SELECTED, /* RMII_SEL, */
|
|
|
+ CORE_NOT_SELECTED, /* SMII_SEL, */
|
|
|
+ CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
|
|
|
+ CORE_NOT_SELECTED, /* UIC_0_3 */
|
|
|
+ CORE_NOT_SELECTED, /* USB1_HOST */
|
|
|
+ CORE_NOT_SELECTED /* PCI_PATCH */
|
|
|
+ };
|
|
|
+
|
|
|
+
|
|
|
+ /* Table Default Initialisation + FPGA Access */
|
|
|
+ init_default_gpio();
|
|
|
+ set_chip_gpio_configuration(GPIO0);
|
|
|
+ set_chip_gpio_configuration(GPIO1);
|
|
|
+
|
|
|
+ /* Update Table */
|
|
|
+ force_bup_core_selection(ppc440ep_core_selection, &config_val);
|
|
|
+#if 0 /* test-only */
|
|
|
+ /* If we are running PIBS 1, force known configuration */
|
|
|
+ update_core_selection_table(ppc440ep_core_selection, &config_val);
|
|
|
+#endif
|
|
|
+
|
|
|
+ /*----------------------------------------------------------------------------+
|
|
|
+ | SDR + ios table update + fpga initialization
|
|
|
+ +----------------------------------------------------------------------------*/
|
|
|
+ unsigned long sdr0_pfc1 = 0;
|
|
|
+ unsigned long sdr0_usb0 = 0;
|
|
|
+ unsigned long sdr0_mfr = 0;
|
|
|
+
|
|
|
+ /* PCI Always selected */
|
|
|
+
|
|
|
+ /* I2C Selection */
|
|
|
+ if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
|
|
|
+ iic1_selection_in_fpga();
|
|
|
+ }
|
|
|
+
|
|
|
+ /* SCP Selection */
|
|
|
+ if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
|
|
|
+ scp_selection_in_fpga();
|
|
|
+ }
|
|
|
+
|
|
|
+ /* UIC 0:3 Selection */
|
|
|
+ if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ update_uic_0_3_irq_ios();
|
|
|
+ dma_a_b_unselect_in_fpga();
|
|
|
+ }
|
|
|
+
|
|
|
+ /* UIC 4:9 Selection */
|
|
|
+ if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
|
|
|
+ update_uic_4_9_irq_ios();
|
|
|
+ }
|
|
|
+
|
|
|
+ /* DMA AB Selection */
|
|
|
+ if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
|
|
|
+ update_dma_a_b_ios();
|
|
|
+ dma_a_b_selection_in_fpga();
|
|
|
+ }
|
|
|
+
|
|
|
+ /* DMA CD Selection */
|
|
|
+ if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ update_dma_c_d_ios();
|
|
|
+ dma_c_d_selection_in_fpga();
|
|
|
+ }
|
|
|
+
|
|
|
+ /* EBC Master Selection */
|
|
|
+ if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
|
|
|
+ update_ebc_master_ios();
|
|
|
+ }
|
|
|
+
|
|
|
+ /* PCI Patch Enable */
|
|
|
+ if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
|
|
|
+ update_pci_patch_ios();
|
|
|
+ }
|
|
|
+
|
|
|
+ /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
|
|
|
+ if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
|
|
|
+ printf("Invalid configuration => USB2 Host selected\n");
|
|
|
+ for (;;)
|
|
|
+ ;
|
|
|
+ /*usb2_host_selection_in_fpga(); */
|
|
|
+ }
|
|
|
+
|
|
|
+ /* USB2.0 Device Selection */
|
|
|
+ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ update_usb2_device_ios();
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
|
|
|
+
|
|
|
+ mfsdr(sdr_usb0, sdr0_usb0);
|
|
|
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
|
|
|
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
|
|
|
+ mtsdr(sdr_usb0, sdr0_usb0);
|
|
|
+
|
|
|
+ usb2_device_selection_in_fpga();
|
|
|
+ }
|
|
|
+
|
|
|
+ /* USB1.1 Device Selection */
|
|
|
+ if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ mfsdr(sdr_usb0, sdr0_usb0);
|
|
|
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
|
|
|
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
|
|
|
+ mtsdr(sdr_usb0, sdr0_usb0);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* USB1.1 Host Selection */
|
|
|
+ if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ mfsdr(sdr_usb0, sdr0_usb0);
|
|
|
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
|
|
|
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
|
|
|
+ mtsdr(sdr_usb0, sdr0_usb0);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* NAND Flash Selection */
|
|
|
+ if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ update_ndfc_ios();
|
|
|
+
|
|
|
+ mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
|
|
|
+ SDR0_CUST0_NDFC_ENABLE |
|
|
|
+ SDR0_CUST0_NDFC_BW_8_BIT |
|
|
|
+ SDR0_CUST0_NDFC_ARE_MASK |
|
|
|
+ SDR0_CUST0_CHIPSELGAT_EN1 );
|
|
|
+ /*SDR0_CUST0_CHIPSELGAT_EN2 ); */
|
|
|
+ /*SDR0_CUST0_CHIPSELGAT_EN3 ); */
|
|
|
+
|
|
|
+ ndfc_selection_in_fpga();
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* Set Mux on EMAC */
|
|
|
+ mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* MII Selection */
|
|
|
+ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ update_zii_ios();
|
|
|
+ mfsdr(sdr_mfr, sdr0_mfr);
|
|
|
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
|
|
|
+ mtsdr(sdr_mfr, sdr0_mfr);
|
|
|
+
|
|
|
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* RMII Selection */
|
|
|
+ if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ update_zii_ios();
|
|
|
+ mfsdr(sdr_mfr, sdr0_mfr);
|
|
|
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
|
|
|
+ mtsdr(sdr_mfr, sdr0_mfr);
|
|
|
+
|
|
|
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* SMII Selection */
|
|
|
+ if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ update_zii_ios();
|
|
|
+ mfsdr(sdr_mfr, sdr0_mfr);
|
|
|
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
|
|
|
+ mtsdr(sdr_mfr, sdr0_mfr);
|
|
|
+
|
|
|
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* UART Selection */
|
|
|
+ uart_configuration = get_uart_configuration();
|
|
|
+ switch (uart_configuration)
|
|
|
+ {
|
|
|
+ case L1: /* L1 Selection */
|
|
|
+ /* UART0 8 pins Only */
|
|
|
+ /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
|
|
|
+ break;
|
|
|
+ case L2: /* L2 Selection */
|
|
|
+ /* UART0 and UART1 4 pins */
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
|
|
|
+ break;
|
|
|
+ case L3: /* L3 Selection */
|
|
|
+ /* UART0 4 pins, UART1 and UART2 2 pins */
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
|
|
|
+ break;
|
|
|
+ case L4: /* L4 Selection */
|
|
|
+ /* UART0, UART1, UART2 and UART3 2 pins */
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ update_uart_ios(uart_configuration);
|
|
|
+
|
|
|
+ /* UART Selection in all cases */
|
|
|
+ uart_selection_in_fpga(uart_configuration);
|
|
|
+
|
|
|
+ /* Packet Reject Function Available */
|
|
|
+ if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ /* Set UPR Bit in SDR0_PFC1 Register */
|
|
|
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Packet Reject Function Enable */
|
|
|
+ if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
|
|
|
+ {
|
|
|
+ mfsdr(sdr_mfr, sdr0_mfr);
|
|
|
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
|
|
|
+ mtsdr(sdr_mfr, sdr0_mfr);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Perform effective access to hardware */
|
|
|
+ mtsdr(sdr_pfc1, sdr0_pfc1);
|
|
|
+ set_chip_gpio_configuration(GPIO0);
|
|
|
+ set_chip_gpio_configuration(GPIO1);
|
|
|
+
|
|
|
+ /* USB2.0 Device Reset must be done after GPIO setting */
|
|
|
+ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
|
|
|
+ usb2_device_reset_through_fpga();
|
|
|
+
|
|
|
+}
|
Stefan Roese