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@@ -1647,7 +1647,7 @@ typedef struct ccsr_gur {
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u8 res4[12];
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u32 gpindr; /* General-purpose input data */
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u8 res5[12];
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- u32 pmuxcr; /* Alt function signal multiplex control */
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+ u32 alt_pmuxcr; /* Alt function signal multiplex control */
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u8 res6[12];
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u32 devdisr; /* Device disable control */
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#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
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@@ -1750,7 +1750,17 @@ typedef struct ccsr_gur {
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u32 cgencrl; /* Core general control */
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u8 res31[184];
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u32 sriopstecr; /* SRIO prescaler timer enable control */
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- u8 res32[2300];
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+ u8 res32[1788];
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+ u32 pmuxcr; /* Pin multiplexing control */
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+ u8 res33[60];
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+ u32 iovselsr; /* I/O voltage selection status */
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+ u8 res34[28];
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+ u32 ddrclkdr; /* DDR clock disable */
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+ u8 res35;
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+ u32 elbcclkdr; /* eLBC clock disable */
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+ u8 res36[20];
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+ u32 sdhcpcr; /* eSDHC polarity configuration */
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+ u8 res37[380];
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} ccsr_gur_t;
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typedef struct ccsr_clk {
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