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+/*
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+ * (C) Copyright 2002
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+ * Custom IDEAS, Inc. <www.cideas.com>
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+ * Jon Diekema <diekema@cideas.com>
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+#ifndef FALSE
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+#define FALSE 0
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+#define TRUE (!FALSE)
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+#endif
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+
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+#define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */
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+
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+#define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */
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+#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
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+#define MAX_64x_SAMPLE_RATE 86805 /* Maximum 64x sample rate */
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+
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+#define KHZ ((uint)1000)
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+#define MHZ ((uint)(1000 * KHZ))
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+
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+#define MCLK_BRG 3 /* MCLK, Master CLocK for the A/D & D/A */
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+#define SCLK_BRG 7 /* SCLK, Sample CLocK for the A/D & D/A */
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+#define LRCLK_BRG 5 /* LRCLK, L/R CLocK for the A/D & D/A */
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+ /* 0 == BRG1 (used for SMC1) */
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+ /* 1 == BRG2 (used for SMC2) */
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+ /* 2 == BRG3 (used for SCC1) */
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+ /* 3 == BRG4 (MCLK) */
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+ /* 4 == BRG5 */
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+ /* 5 == BRG6 (LRCLK) */
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+ /* 6 == BRG7 */
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+ /* 7 == BRG8 (SCLK) */
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+
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+#define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */
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+#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
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+ /* LRCLK = SCLK / SCLK_DIVISOR */
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+
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+#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */
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+#define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */
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+ /* The 8260 (Mask B.3) seems to have */
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+ /* problems generating SCLK from MCLK */
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+ /* via CLK9. */
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+#define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */
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+ /* The 8260 (Mask B.3) seems to have */
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+ /* problems generating LRCLK from SCLK */
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+
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+#define CPM_CLK (gd->bd->bi_cpmfreq)
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+#define DFBRG 4
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+#define BRG_INT_CLK (CPM_CLK * 2 / DFBRG)
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+ /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
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+ /* BRG = CPM * 2 / 4 */
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+ /* BRG = CPM / 2 */
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+
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+#define CPM_BRG_EXTC_MASK ((uint)0x0000C000)
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+#define CPM_BRG_EXTC_SHIFT 14
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+
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+#define CPM_BRG_DIV16_MASK ((uint)0x00000001)
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+#define CPM_BRG_DIV16_SHIFT 1
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+
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+#define CPM_BRG_EXTC_BRGCLK 0
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+#define CPM_BRG_EXTC_CLK3 1
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+#define CPM_BRG_EXTC_CLK9 CPM_BRG_EXTC_CLK3
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+#define CPM_BRG_EXTC_CLK5 2
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+#define CPM_BRG_EXTC_CLK15 CPM_BRG_EXTC_CLK5
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+
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+/*
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+ * External declarations
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+ */
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+
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+extern int Daq64xSampling;
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+
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+extern void Daq_BRG_Reset(uint brg);
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+extern void Daq_BRG_Run(uint brg);
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+
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+extern void Daq_BRG_Disable(uint brg);
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+extern void Daq_BRG_Enable(uint brg);
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+
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+extern uint Daq_BRG_Get_Div16(uint brg);
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+extern void Daq_BRG_Set_Div16(uint brg, uint div16);
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+
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+extern uint Daq_BRG_Get_Count(uint brg);
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+extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);
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+
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+extern uint Daq_BRG_Get_ExtClk(uint brg);
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+extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
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+extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
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+
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+extern uint Daq_BRG_Rate(uint brg);
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+
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+extern uint Daq_Get_SampleRate(void);
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+extern uint Daq_Set_SampleRate(uint rate, uint force);
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+
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+extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
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+extern void Daq_Stop_Clocks(void);
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+extern void Daq_Start_Clocks(int sample_rate);
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+extern void Daq_Display_Clocks(void);
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wdenk