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@@ -20,16 +20,11 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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-
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#include <asm/io.h>
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-#include <asm/arch/tegra20.h>
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#include <asm/arch/ap20.h>
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-#include <asm/arch/clk_rst.h>
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-#include <asm/arch/clock.h>
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#include <asm/arch/fuse.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/pmc.h>
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-#include <asm/arch/pinmux.h>
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#include <asm/arch/scu.h>
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#include <asm/arch/warmboot.h>
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#include <common.h>
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@@ -68,235 +63,7 @@ int tegra_get_chip_type(void)
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return TEGRA_SOC_UNKNOWN;
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}
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-/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
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-static int ap20_cpu_is_cortexa9(void)
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-{
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- u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
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- return id == (PG_UP_TAG_0_PID_CPU & 0xff);
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-}
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-
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-void init_pllx(void)
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-{
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- struct clk_rst_ctlr *clkrst =
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- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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- struct clk_pll_simple *pll =
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- &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
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- u32 reg;
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-
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- /* If PLLX is already enabled, just return */
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- if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
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- return;
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-
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- /* Set PLLX_MISC */
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- writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
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-
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- /* Use 12MHz clock here */
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- reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
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- reg |= 1000 << PLL_DIVN_SHIFT;
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- writel(reg, &pll->pll_base);
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-
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- reg |= PLL_ENABLE_MASK;
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- writel(reg, &pll->pll_base);
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-
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- reg &= ~PLL_BYPASS_MASK;
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- writel(reg, &pll->pll_base);
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-}
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-
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-static void enable_cpu_clock(int enable)
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-{
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- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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- u32 clk;
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-
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- /*
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- * NOTE:
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- * Regardless of whether the request is to enable or disable the CPU
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- * clock, every processor in the CPU complex except the master (CPU 0)
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- * will have it's clock stopped because the AVP only talks to the
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- * master. The AVP does not know (nor does it need to know) that there
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- * are multiple processors in the CPU complex.
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- */
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-
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- if (enable) {
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- /* Initialize PLLX */
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- init_pllx();
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-
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- /* Wait until all clocks are stable */
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- udelay(PLL_STABILIZATION_DELAY);
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-
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- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
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- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
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- }
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-
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- /*
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- * Read the register containing the individual CPU clock enables and
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- * always stop the clock to CPU 1.
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- */
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- clk = readl(&clkrst->crc_clk_cpu_cmplx);
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- clk |= 1 << CPU1_CLK_STP_SHIFT;
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-
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- /* Stop/Unstop the CPU clock */
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- clk &= ~CPU0_CLK_STP_MASK;
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- clk |= !enable << CPU0_CLK_STP_SHIFT;
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- writel(clk, &clkrst->crc_clk_cpu_cmplx);
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-
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- clock_enable(PERIPH_ID_CPU);
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-}
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-
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-static int is_cpu_powered(void)
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-{
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- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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-
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- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
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-}
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-
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-static void remove_cpu_io_clamps(void)
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-{
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- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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- u32 reg;
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-
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- /* Remove the clamps on the CPU I/O signals */
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- reg = readl(&pmc->pmc_remove_clamping);
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- reg |= CPU_CLMP;
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- writel(reg, &pmc->pmc_remove_clamping);
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-
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- /* Give I/O signals time to stabilize */
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- udelay(IO_STABILIZATION_DELAY);
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-}
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-
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-static void powerup_cpu(void)
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-{
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- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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- u32 reg;
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- int timeout = IO_STABILIZATION_DELAY;
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-
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- if (!is_cpu_powered()) {
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- /* Toggle the CPU power state (OFF -> ON) */
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- reg = readl(&pmc->pmc_pwrgate_toggle);
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- reg &= PARTID_CP;
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- reg |= START_CP;
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- writel(reg, &pmc->pmc_pwrgate_toggle);
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-
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- /* Wait for the power to come up */
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- while (!is_cpu_powered()) {
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- if (timeout-- == 0)
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- printf("CPU failed to power up!\n");
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- else
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- udelay(10);
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- }
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-
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- /*
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- * Remove the I/O clamps from CPU power partition.
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- * Recommended only on a Warm boot, if the CPU partition gets
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- * power gated. Shouldn't cause any harm when called after a
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- * cold boot according to HW, probably just redundant.
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- */
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- remove_cpu_io_clamps();
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- }
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-}
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-
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-static void enable_cpu_power_rail(void)
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-{
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- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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- u32 reg;
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-
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- reg = readl(&pmc->pmc_cntrl);
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- reg |= CPUPWRREQ_OE;
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- writel(reg, &pmc->pmc_cntrl);
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-
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- /*
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- * The TI PMU65861C needs a 3.75ms delay between enabling
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- * the power rail and enabling the CPU clock. This delay
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- * between SM1EN and SM1 is for switching time + the ramp
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- * up of the voltage to the CPU (VDD_CPU from PMU).
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- */
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- udelay(3750);
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-}
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-
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-static void reset_A9_cpu(int reset)
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-{
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- /*
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- * NOTE: Regardless of whether the request is to hold the CPU in reset
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- * or take it out of reset, every processor in the CPU complex
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- * except the master (CPU 0) will be held in reset because the
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- * AVP only talks to the master. The AVP does not know that there
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- * are multiple processors in the CPU complex.
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- */
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-
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- /* Hold CPU 1 in reset, and CPU 0 if asked */
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- reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
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- reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
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- reset);
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-
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- /* Enable/Disable master CPU reset */
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- reset_set_enable(PERIPH_ID_CPU, reset);
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-}
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-
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-static void clock_enable_coresight(int enable)
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-{
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- u32 rst, src;
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-
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- clock_set_enable(PERIPH_ID_CORESIGHT, enable);
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- reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
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-
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- if (enable) {
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- /*
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- * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
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- * 1.5, giving an effective frequency of 144MHz.
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- * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
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- * (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
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- */
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- src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
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- clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
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-
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- /* Unlock the CPU CoreSight interfaces */
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- rst = 0xC5ACCE55;
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- writel(rst, CSITE_CPU_DBG0_LAR);
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- writel(rst, CSITE_CPU_DBG1_LAR);
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- }
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-}
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-
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-void start_cpu(u32 reset_vector)
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-{
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- /* Enable VDD_CPU */
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- enable_cpu_power_rail();
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-
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- /* Hold the CPUs in reset */
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- reset_A9_cpu(1);
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-
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- /* Disable the CPU clock */
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- enable_cpu_clock(0);
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-
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- /* Enable CoreSight */
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- clock_enable_coresight(1);
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-
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- /*
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- * Set the entry point for CPU execution from reset,
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- * if it's a non-zero value.
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- */
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- if (reset_vector)
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- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
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-
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- /* Enable the CPU clock */
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- enable_cpu_clock(1);
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-
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- /* If the CPU doesn't already have power, power it up */
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- powerup_cpu();
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-
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- /* Take the CPU out of reset */
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- reset_A9_cpu(0);
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-}
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-
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-
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-void halt_avp(void)
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-{
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- for (;;) {
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- writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
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- | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
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- FLOW_CTLR_HALT_COP_EVENTS);
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- }
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-}
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-
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-void enable_scu(void)
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+static void enable_scu(void)
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{
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struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
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u32 reg;
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@@ -332,7 +99,7 @@ static u32 get_odmdata(void)
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return odmdata;
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}
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-void init_pmc_scratch(void)
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+static void init_pmc_scratch(void)
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{
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struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
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u32 odmdata;
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@@ -347,27 +114,8 @@ void init_pmc_scratch(void)
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writel(odmdata, &pmc->pmc_scratch20);
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}
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-void tegra20_start(void)
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+void s_init(void)
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{
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- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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-
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- /* If we are the AVP, start up the first Cortex-A9 */
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- if (!ap20_cpu_is_cortexa9()) {
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- /* enable JTAG */
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- writel(0xC0, &pmt->pmt_cfg_ctl);
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-
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- /*
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- * If we are ARM7 - give it a different stack. We are about to
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- * start up the A9 which will want to use this one.
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- */
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- asm volatile("mov sp, %0\n"
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- : : "r"(AVP_EARLY_BOOT_STACK_LIMIT));
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-
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- start_cpu((u32)_start);
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- halt_avp();
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- /* not reached */
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- }
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-
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/* Init PMC scratch memory */
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init_pmc_scratch();
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Allen Martin