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@@ -30,16 +30,27 @@
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struct sdram_conf_s {
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unsigned long size;
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unsigned long reg;
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+#ifdef CONFIG_TQM8548
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+ unsigned long refresh;
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+#endif /* CONFIG_TQM8548 */
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};
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typedef struct sdram_conf_s sdram_conf_t;
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+#ifdef CONFIG_TQM8548
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+sdram_conf_t ddr_cs_conf[] = {
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+ {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
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+ {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
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+ {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
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+};
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+#else /* !CONFIG_TQM8548 */
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sdram_conf_t ddr_cs_conf[] = {
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{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
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{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
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{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
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{( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
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};
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+#endif /* CONFIG_TQM8548 */
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#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
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@@ -56,8 +67,12 @@ long int sdram_setup (int casl)
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{
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int i;
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volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
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+#ifdef CONFIG_TQM8548
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+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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+#else /* !CONFIG_TQM8548 */
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unsigned long cfg_ddr_timing1;
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unsigned long cfg_ddr_mode;
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+#endif /* CONFIG_TQM8548 */
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/*
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* Disable memory controller.
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@@ -65,6 +80,122 @@ long int sdram_setup (int casl)
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ddr->cs0_config = 0;
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ddr->sdram_cfg = 0;
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+#ifdef CONFIG_TQM8548
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+ ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
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+ ddr->cs0_config = ddr_cs_conf[0].reg;
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+ ddr->timing_cfg_3 = 0x00010000;
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+
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+ /* TIMING CFG 1, 533MHz
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+ * PRETOACT: 4 Clocks
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+ * ACTTOPRE: 12 Clocks
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+ * ACTTORW: 4 Clocks
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+ * CASLAT: 4 Clocks
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+ * REFREC: 34 Clocks
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+ * WRREC: 4 Clocks
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+ * ACTTOACT: 3 Clocks
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+ * WRTORD: 2 Clocks
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+ */
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+ ddr->timing_cfg_1 = 0x4C47A432;
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+
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+ /* TIMING CFG 2, 533MHz
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+ * ADD_LAT: 3 Clocks
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+ * CPO: READLAT + 1
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+ * WR_LAT: 3 Clocks
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+ * RD_TO_PRE: 2 Clocks
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+ * WR_DATA_DELAY: 1/2 Clock
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+ * CKE_PLS: 1 Clock
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+ * FOUR_ACT: 13 Clocks
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+ */
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+ ddr->timing_cfg_2 = 0x3318484D;
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+
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+ /* DDR SDRAM Mode, 533MHz
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+ * MRS: Extended Mode Register
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+ * OUT: Outputs enabled
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+ * RDQS: no
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+ * DQS: enabled
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+ * OCD: default state
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+ * RTT: 75 Ohms
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+ * Posted CAS: 3 Clocks
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+ * ODS: reduced strength
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+ * DLL: enabled
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+ * MR: Mode Register
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+ * PD: fast exit
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+ * WR: 4 Clocks
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+ * DLL: no DLL reset
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+ * TM: normal
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+ * CAS latency: 4 Clocks
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+ * BT: sequential
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+ * Burst length: 4
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+ */
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+ ddr->sdram_mode = 0x439E0642;
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+
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+ /* DDR SDRAM Interval, 533MHz
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+ * REFINT: 1040 Clocks
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+ * BSTOPRE: 256
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+ */
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+ ddr->sdram_interval = (1040 << 16) | 0x100;
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+
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+ /*
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+ * workaround for erratum DD10 of MPC8458 family below rev. 2.0:
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+ * DDR IO receiver must be set to an acceptable bias point by modifying
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+ * a hidden register.
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+ */
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+ if (SVR_REV (get_svr ()) < 0x20) {
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+ gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
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+ }
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+
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+ /* DDR SDRAM CFG 2
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+ * FRC_SR: normal mode
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+ * SR_IE: no self-refresh interrupt
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+ * DLL_RST_DIS: don't care, leave at reset value
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+ * DQS_CFG: differential DQS signals
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+ * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
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+ * LVWx_CFG: don't care, leave at reset value
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+ * NUM_PR: 1 refresh will be issued at a time
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+ * DM_CFG: don't care, leave at reset value
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+ * D_INIT: no data initialization
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+ */
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+ ddr->sdram_cfg_2 = 0x04401000;
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+
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+ /* DDR SDRAM MODE 2
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+ * MRS: Extended Mode Register 2
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+ */
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+ ddr->sdram_mode_2 = 0x8000C000;
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+
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+ /* DDR SDRAM CLK CNTL
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+ * CLK_ADJUST: 1/2 Clock 0x02000000
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+ * CLK_ADJUST: 5/8 Clock 0x02800000
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+ */
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+ ddr->sdram_clk_cntl = 0x02800000;
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+
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+ /* wait for clock stabilization */
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+ asm ("sync;isync;msync");
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+ udelay(1000);
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+
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+ /* DDR SDRAM CLK CNTL
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+ * MEM_EN: enabled
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+ * SREN: don't care, leave at reset value
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+ * ECC_EN: no error report
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+ * RD_EN: no register DIMMs
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+ * SDRAM_TYPE: DDR2
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+ * DYN_PWR: no power management
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+ * 32_BE: don't care, leave at reset value
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+ * 8_BE: 4 beat burst
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+ * NCAP: don't care, leave at reset value
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+ * 2T_EN: 1T Timing
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+ * BA_INTLV_CTL: no interleaving
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+ * x32_EN: x16 organization
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+ * PCHB8: MA[10] for auto-precharge
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+ * HSE: half strength for single and 2-layer stacks
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+ * (full strength for 3- and 4-layer stacks no yet considered)
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+ * MEM_HALT: no halt
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+ * BI: automatic initialization
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+ */
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+ ddr->sdram_cfg = 0x83000008;
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+ asm ("sync; isync; msync");
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+ udelay(1000);
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+
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+#else /* !CONFIG_TQM8548 */
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switch (casl) {
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case 20:
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cfg_ddr_timing1 = 0x47405331 | (3 << 16);
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@@ -97,6 +228,7 @@ long int sdram_setup (int casl)
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ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
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asm ("sync; isync; msync");
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udelay (1000);
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+#endif /* CONFIG_TQM8548 */
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for (i = 0; i < N_DDR_CS_CONF; i++) {
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ddr->cs0_config = ddr_cs_conf[i].reg;
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@@ -108,11 +240,25 @@ long int sdram_setup (int casl)
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*/
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ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
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- return ddr_cs_conf[i].size;
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+ break;
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}
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}
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- return 0; /* nothing found ! */
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+#ifdef CONFIG_TQM8548
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+ if (i < N_DDR_CS_CONF) {
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+ /* Adjust refresh rate for DDR2 */
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+
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+ ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
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+
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+ ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
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+ (ddr_cs_conf[i].refresh & 0x0000F000);
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+
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+ return ddr_cs_conf[i].size;
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+ }
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+#endif /* CONFIG_TQM8548 */
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+
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+ /* return size if detected, else return 0 */
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+ return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
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}
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void board_add_ram_info (int use_default)
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Wolfgang Grandegger