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@@ -179,6 +179,11 @@ l2_disabled:
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andi. r1,r3,L1CSR0_DCE@l
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beq 2b
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+/*
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+ * Ne need to setup interrupt vector for NAND SPL
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+ * because NAND SPL never compiles it.
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+ */
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+#if !defined(CONFIG_NAND_SPL)
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/* Setup interrupt vectors */
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lis r1,CONFIG_SYS_MONITOR_BASE@h
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mtspr IVPR,r1
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@@ -217,6 +222,7 @@ l2_disabled:
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mtspr IVOR14,r4 /* 14: Instruction TLB error */
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addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
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mtspr IVOR15,r4 /* 15: Debug */
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+#endif
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/* Clear and set up some registers. */
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li r0,0x0000
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