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@@ -406,4 +406,28 @@ static void set_ddr_config(void) {
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(DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
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(DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
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(DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
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(DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
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SYNC;
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SYNC;
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+
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+ /* Workaround for DDR6 Erratum
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+ * see MPC8349E Device Errata Rev.8, 2/2006
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+ * This workaround influences the MPC internal "input enables"
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+ * dependent on CAS latency and MPC revision. According to errata
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+ * sheet the internal reserved registers for this workaround are
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+ * not available from revision 2.0 and up.
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+ */
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+
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+ /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
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+ * (0x200)
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+ */
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+ if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
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+
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+ /* There is a internal reserved register at IMMRBAR+0x2F00
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+ * which has to be written with a certain value defined by
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+ * errata sheet.
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+ */
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+#if defined(DDR_CASLAT_20)
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+ *((u8 *)im + 0x2f00) = 0x201c0000;
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+#else
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+ *((u8 *)im + 0x2f00) = 0x202c0000;
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+#endif
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+ }
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}
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}
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