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@@ -73,33 +73,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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void
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ddr_enable_ecc(unsigned int dram_size)
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{
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- uint *p = 0;
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- uint i = 0;
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volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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- for (*p = 0; p < (uint *)(8 * 1024); p++) {
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- if (((unsigned int)p & 0x1f) == 0) {
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- ppcDcbz((unsigned long) p);
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- }
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- *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
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- if (((unsigned int)p & 0x1c) == 0x1c) {
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- ppcDcbf((unsigned long) p);
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- }
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- }
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-
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- dmacpy(0x002000, 0, 0x2000); /* 8K */
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- dmacpy(0x004000, 0, 0x4000); /* 16K */
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- dmacpy(0x008000, 0, 0x8000); /* 32K */
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- dmacpy(0x010000, 0, 0x10000); /* 64K */
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- dmacpy(0x020000, 0, 0x20000); /* 128K */
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- dmacpy(0x040000, 0, 0x40000); /* 256K */
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- dmacpy(0x080000, 0, 0x80000); /* 512K */
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- dmacpy(0x100000, 0, 0x100000); /* 1M */
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- dmacpy(0x200000, 0, 0x200000); /* 2M */
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- dmacpy(0x400000, 0, 0x400000); /* 4M */
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-
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- for (i = 1; i < dram_size / 0x800000; i++)
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- dmacpy(0x800000 *i, 0, 0x800000);
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+ dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
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/*
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* Enable errors for ECC.
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