pantheon: define CONFIG_SYS_CACHELINE_SIZE

By default, on Pantheon SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>

arch/arm/include/asm/arch-pantheon/config.h

@@ -28,6 +28,8 @@
 #include <asm/arch/pantheon.h>
 
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
+/* default Dcache Line length for pantheon */
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */