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@@ -115,7 +115,18 @@ int clk_get(enum davinci_clk_ids id)
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out:
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return pll_out;
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}
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-#endif /* CONFIG_SOC_DA8XX */
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+#ifdef CONFIG_DISPLAY_CPUINFO
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+int print_cpuinfo(void)
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+{
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+ printf("Cores: ARM %d MHz",
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+ clk_get(DAVINCI_ARM_CLKID) / 1000000);
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+ printf("\nDDR: %d MHz\n",
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+ /* DDR PHY uses an x2 input clock */
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+ clk_get(0x10001) / 1000000);
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+ return 0;
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+}
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+#endif
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+#else /* CONFIG_SOC_DA8XX */
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#ifdef CONFIG_DISPLAY_CPUINFO
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@@ -194,7 +205,8 @@ unsigned int davinci_arm_clk_get()
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return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
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}
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#endif
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-#endif
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+#endif /* CONFIG_DISPLAY_CPUINFO */
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+#endif /* !CONFIG_SOC_DA8XX */
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/*
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* Initializes on-chip ethernet controllers.
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