Merge branch 'master' of /home/wd/git/u-boot/custodians

board/amcc/sequoia/Makefile

@@ -25,9 +25,11 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cmd_sequoia.o sdram.o
+COBJS-y	= $(BOARD).o sdram.o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
 SOBJS	= init.o
 
+COBJS   := $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))

board/amcc/sequoia/chip_config.c

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"333-133-nor", "NOR  CPU: 333 PLB: 133 OPB:  66 EBC:  66",
+		{
+			0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"333-166-nor", "NOR  CPU: 333 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"333-166-nand", "NAND CPU: 333 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"400-133-nor", "NOR  CPU: 400 PLB: 133 OPB:  66 EBC:  66",
+		{
+			0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"400-160-nor", "NOR  CPU: 400 PLB: 160 OPB:  80 EBC:  53",
+		{
+			0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"416-166-nor", "NOR  CPU: 416 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"416-166-nand", "NAND CPU: 416 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"500-166-nor", "NOR  CPU: 500 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"500-166-nand", "NAND CPU: 500 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"533-133-nor", "NOR  CPU: 533 PLB: 133 OPB:  66 EBC:  66",
+		{
+			0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"667-133-nor", "NOR  CPU: 667 PLB: 133 OPB:  66 EBC:  66",
+		{
+			0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"667-166-nor", "NOR  CPU: 667 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"667-166-nand", "NAND CPU: 667 PLB: 166 OPB:  83 EBC:  55",
+		{
+			0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);

board/amcc/sequoia/cmd_sequoia.c

@@ -1,231 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <asm/io.h>
-
-/*
- * There are 2 versions of production Sequoia & Rainier platforms.
- * The primary difference is the reference clock. Those with
- * 33333333 reference clocks will also have 667MHz rated
- * processors. Not enough differences to have unique clock
- * settings.
- *
- * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
- * values are independent of the rest of the clock settings.
- *
- * All Sequoias & Rainiers select from two possible EEPROMs in Boot
- * Config F. One for 33MHz PCI, one for 66MHz PCI. The following
- * values are for the 33MHz PCI configuration. Byte 5 (0 base) is
- * the only value affected for a 33MHz PCI and simply needs a | 0x08.
- */
-
-#define NAND_COMPATIBLE	0x01
-#define NOR_COMPATIBLE  0x02
-
-/* check with Stefan on CONFIG_SYS_I2C_EEPROM_ADDR */
-#define I2C_EEPROM_ADDR 0x52
-
-static char *config_labels[] = {
-	"CPU: 333 PLB: 133 OPB: 66 EBC: 66",
-	"CPU: 333 PLB: 166 OPB: 83 EBC: 55",
-	"CPU: 400 PLB: 133 OPB: 66 EBC: 66",
-	"CPU: 400 PLB: 160 OPB: 80 EBC: 53",
-	"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
-	"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
-	"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
-	"CPU: 667 PLB: 133 OPB: 66 EBC: 66",
-	"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
-	NULL
-};
-
-static u8 boot_configs[][17] = {
-	{
-		(NOR_COMPATIBLE),
-		0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
-		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-	},
-	{
-		(NAND_COMPATIBLE | NOR_COMPATIBLE),
-		0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
-		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-	},
-	{
-		(NOR_COMPATIBLE),
-		0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
-		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-	},
-	{
-		(NOR_COMPATIBLE),
-		0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
-		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-	},
-	{
-		(NAND_COMPATIBLE | NOR_COMPATIBLE),
-		0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
-		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-	},
-	{
-		(NAND_COMPATIBLE | NOR_COMPATIBLE),
-		0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
-		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-	},
-	{
-		(NOR_COMPATIBLE),
-		0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
-		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-	},
-	{
-		(NOR_COMPATIBLE),
-		0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
-		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-	},
-	{
-		(NAND_COMPATIBLE | NOR_COMPATIBLE),
-		0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
-		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-	},
-	{
-		0,
-		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-	}
-};
-
-/*
- * Bytes 6,8,9,11 change for NAND boot
- */
-static u8 nand_boot[] = {
-	0xd0,  0xa0, 0x68, 0x58
-};
-
-static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	u8 *buf, bNAND;
-	int x, y, nbytes, selcfg;
-	extern char console_buffer[];
-
-	if (argc < 2) {
-		cmd_usage(cmdtp);
-		return 1;
-	}
-
-	if ((strcmp(argv[1], "nor") != 0) &&
-	    (strcmp(argv[1], "nand") != 0)) {
-		printf("Unsupported boot-device - only nor|nand support\n");
-		return 1;
-	}
-
-	/* set the nand flag based on provided input */
-	if ((strcmp(argv[1], "nand") == 0))
-		bNAND = 1;
-	else
-		bNAND = 0;
-
-	printf("Available configurations: \n\n");
-
-	if (bNAND) {
-		for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
-			/* filter on nand compatible */
-			if (boot_configs[x][0] & NAND_COMPATIBLE) {
-				printf(" %d - %s\n", (y+1), config_labels[x]);
-				y++;
-			}
-		}
-	} else {
-		for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
-			/* filter on nor compatible */
-			if (boot_configs[x][0] & NOR_COMPATIBLE) {
-				printf(" %d - %s\n", (y+1), config_labels[x]);
-				y++;
-			}
-		}
-	}
-
-	do {
-		nbytes = readline(" Selection [1-x / quit]: ");
-
-		if (nbytes) {
-			if (strcmp(console_buffer, "quit") == 0)
-				return 0;
-			selcfg = simple_strtol(console_buffer, NULL, 10);
-			if ((selcfg < 1) || (selcfg > y))
-				nbytes = 0;
-		}
-	} while (nbytes == 0);
-
-
-	y = (selcfg - 1);
-
-	for (x = 0; boot_configs[x][0] != 0; x++) {
-		if (bNAND) {
-			if (boot_configs[x][0] & NAND_COMPATIBLE) {
-				if (y > 0)
-					y--;
-				else if (y < 1)
-					break;
-			}
-		} else {
-			if (boot_configs[x][0] & NOR_COMPATIBLE) {
-				if (y > 0)
-					y--;
-				else if (y < 1)
-					break;
-			}
-		}
-	}
-
-	buf = &boot_configs[x][1];
-
-	if (bNAND) {
-		buf[6] = nand_boot[0];
-		buf[8] = nand_boot[1];
-		buf[9] = nand_boot[2];
-		buf[11] = nand_boot[3];
-	}
-
-	/* check CPLD register +5 for PCI 66MHz flag */
-	if ((in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN) == 0)
-		/*
-		 * PLB-to-PCI divisor = 3 for 33MHz sync PCI
-		 * instead of 2 for 66MHz systems
-		 */
-		buf[5] |= 0x08;
-
-	if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
-		printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
-	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-
-	printf("Done\n");
-	printf("Please power-cycle the board for the changes to take effect\n");
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	bootstrap,	2,	0,	do_bootstrap,
-	"program the I2C bootstrap EEPROM",
-	"<nand|nor> - strap to boot from NAND or NOR flash"
-);

board/amcc/sequoia/sequoia.c

@@ -40,6 +40,15 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
 extern void __ft_board_setup(void *blob, bd_t *bd);
 ulong flash_get_size(ulong base, int banknum);
 
+static inline u32 get_async_pci_freq(void)
+{
+	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
+		CONFIG_SYS_BCSR5_PCI66EN)
+		return 66666666;
+	else
+		return 33333333;
+}
+
 int board_early_init_f(void)
 {
 	u32 sdr0_cust0;
@@ -76,6 +85,9 @@ int board_early_init_f(void)
 	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
 	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 
+	/* Check and reconfigure the PCI sync clock if necessary */
+	ppc4xx_pci_sync_clock_config(get_async_pci_freq());
+
 	/* 50MHz tmrclk */
 	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
 
@@ -319,7 +331,7 @@ int checkboard(void)
 {
 	char *s = getenv("serial#");
 	u8 rev;
-	u8 val;
+	u32 clock = get_async_pci_freq();
 
 #ifdef CONFIG_440EPX
 	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
@@ -328,8 +340,7 @@ int checkboard(void)
 #endif
 
 	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
-	val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
-	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
 
 	if (s != NULL) {
 		puts(", serial# ");
@@ -337,6 +348,15 @@ int checkboard(void)
 	}
 	putc('\n');
 
+	/*
+	 * Reconfiguration of the PCI sync clock is already done,
+	 * now check again if everything is in range:
+	 */
+	if (ppc4xx_pci_sync_clock_config(clock)) {
+		printf("ERROR: PCI clocking incorrect (async=%d "
+		       "sync=%ld)!\n", clock, get_PCI_freq());
+	}
+
 	return (0);
 }
 

board/amcc/yosemite/yosemite.c

@@ -33,6 +33,15 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
+static inline u32 get_async_pci_freq(void)
+{
+	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
+		CONFIG_SYS_BCSR5_PCI66EN)
+		return 66666666;
+	else
+		return 33333333;
+}
+
 int board_early_init_f(void)
 {
 	register uint reg;
@@ -106,6 +115,9 @@ int board_early_init_f(void)
 	mtsdr(SDR0_PFC0, 0x00003e00);	/* Pin function */
 	mtsdr(SDR0_PFC1, 0x00048000);	/* Pin function: UART0 has 4 pins */
 
+	/* Check and reconfigure the PCI sync clock if necessary */
+	ppc4xx_pci_sync_clock_config(get_async_pci_freq());
+
 	/*clear tmrclk divisor */
 	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
 
@@ -178,7 +190,7 @@ int checkboard(void)
 {
 	char *s = getenv("serial#");
 	u8 rev;
-	u8 val;
+	u32 clock = get_async_pci_freq();
 
 #ifdef CONFIG_440EP
 	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
@@ -187,8 +199,7 @@ int checkboard(void)
 #endif
 
 	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
-	val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
-	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
 
 	if (s != NULL) {
 		puts(", serial# ");
@@ -196,6 +207,15 @@ int checkboard(void)
 	}
 	putc('\n');
 
+	/*
+	 * Reconfiguration of the PCI sync clock is already done,
+	 * now check again if everything is in range:
+	 */
+	if (ppc4xx_pci_sync_clock_config(clock)) {
+		printf("ERROR: PCI clocking incorrect (async=%d "
+		       "sync=%ld)!\n", clock, get_PCI_freq());
+	}
+
 	return (0);
 }
 

common/fdt_support.c

@@ -692,3 +692,47 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+/*
+ * This function can be used to update the size in the "reg" property
+ * of the NOR FLASH device nodes. This is necessary for boards with
+ * non-fixed NOR FLASH sizes.
+ */
+int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
+{
+	char compat[][16] = { "cfi-flash", "jedec-flash" };
+	int off;
+	int len;
+	struct fdt_property *prop;
+	u32 *reg;
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		off = fdt_node_offset_by_compatible(blob, -1, compat[i]);
+		while (off != -FDT_ERR_NOTFOUND) {
+			/*
+			 * Found one compatible node, now check if this one
+			 * has the correct CS
+			 */
+			prop = fdt_get_property_w(blob, off, "reg", &len);
+			if (prop) {
+				reg = (u32 *)&prop->data[0];
+				if (reg[0] == cs) {
+					reg[2] = size;
+					fdt_setprop(blob, off, "reg", reg,
+						    3 * sizeof(u32));
+
+					return 0;
+				}
+			}
+
+			/* Move to next compatible node */
+			off = fdt_node_offset_by_compatible(blob, off,
+							    compat[i]);
+		}
+	}
+
+	return -1;
+}
+#endif

cpu/ppc4xx/cpu.c

@@ -608,10 +608,17 @@ int checkcpu (void)
 		break;
 	}
 
-	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
+	printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
+		strmhz(buf, clock),
 		sys_info.freqPLB / 1000000,
 		get_OPB_freq() / 1000000,
 		sys_info.freqEBC / 1000000);
+#if defined(CONFIG_PCI) && \
+	(defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+	 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
+	printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
+#endif
+	printf(")\n");
 
 	if (addstr[0] != 0)
 		printf("       %s\n", addstr);

cpu/ppc4xx/cpu_init.c

@@ -330,3 +330,72 @@ int cpu_init_r (void)
 
 	return 0;
 }
+
+#if defined(CONFIG_PCI) && \
+	(defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+	 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
+/*
+ * 440EP(x)/GR(x) PCI async/sync clocking restriction:
+ *
+ * In asynchronous PCI mode, the synchronous PCI clock must meet
+ * certain requirements. The following equation describes the
+ * relationship that must be maintained between the asynchronous PCI
+ * clock and synchronous PCI clock. Select an appropriate PCI:PLB
+ * ratio to maintain the relationship:
+ *
+ * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
+ */
+static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
+{
+	if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000)))
+		return 0;
+	else
+		return 1;
+}
+
+int ppc4xx_pci_sync_clock_config(u32 async)
+{
+	sys_info_t sys_info;
+	u32 sync;
+	int div;
+	u32 reg;
+	u32 spcid_val[] = {
+		CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
+		CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };
+
+	get_sys_info(&sys_info);
+	sync = sys_info.freqPCI;
+
+	/*
+	 * First check if the equation above is met
+	 */
+	if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
+		/*
+		 * Reconfigure PCI sync clock to meet the equation.
+		 * Start with highest possible PCI sync frequency
+		 * (divider 1).
+		 */
+		for (div = 1; div <= 4; div++) {
+			sync = sys_info.freqPLB / div;
+			if (ppc4xx_pci_sync_clock_ok(sync, async))
+			    break;
+		}
+
+		if (div <= 4) {
+			mtcpr(CPR0_SPCID, spcid_val[div]);
+
+			mfcpr(CPR0_ICFG, reg);
+			reg |= CPR0_ICFG_RLI_MASK;
+			mtcpr(CPR0_ICFG, reg);
+
+			/* do chip reset */
+			mtspr(SPRN_DBCR0, 0x20000000);
+		} else {
+			/* Impossible to configure the PCI sync clock */
+			return -1;
+		}
+	}
+
+	return 0;
+}
+#endif

cpu/ppc4xx/fdt.c

@@ -59,11 +59,17 @@ void __ft_board_setup(void *blob, bd_t *bd)
 			*p++ = 0;
 			*p++ = bxcr & EBC_BXCR_BAS_MASK;
 			*p++ = EBC_BXCR_BANK_SIZE(bxcr);
+
+#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+			/* Try to update reg property in nor flash node too */
+			fdt_fixup_nor_flash_size(blob, i,
+						 EBC_BXCR_BANK_SIZE(bxcr));
+#endif
 		}
 	}
 
 	/* Some 405 PPC's have EBC as direct PLB child in the dts */
-	if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
+	if (fdt_path_offset(blob, ebc_path) < 0)
 		strcpy(ebc_path, "/plb/ebc");
 	rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
 				  (p - ranges) * sizeof(u32), 1);

include/configs/amcc-common.h

@@ -156,6 +156,8 @@
  */
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
+/* Update size in "reg" property of NOR FLASH device tree nodes */
+#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 
 /*
  * Booting and default environment

include/configs/sequoia.h

@@ -243,6 +243,11 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
+
 /* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
 #define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
 #define CONFIG_DTT_AD7414	1	/* use AD7414			*/
@@ -300,6 +305,7 @@
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
+#define CONFIG_CMD_CHIP_CONFIG
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_NAND

include/fdt_support.h

@@ -79,5 +79,7 @@ void ft_pci_setup(void *blob, bd_t *bd);
 void set_working_fdt_addr(void *addr);
 int fdt_resize(void *blob);
 
+int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
+
 #endif /* ifdef CONFIG_OF_LIBFDT */
 #endif /* ifndef __FDT_SUPPORT_H */

include/ppc440.h

@@ -1701,9 +1701,14 @@
 #define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
 #endif /* CONFIG_440GX */
 
-#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define CPR0_ICFG_RLI_MASK	0x80000000
 #define CPR0_SPCID_SPCIDV0_MASK	0x03000000
+#define CPR0_SPCID_SPCIDV0_DIV1	0x01000000
+#define CPR0_SPCID_SPCIDV0_DIV2	0x02000000
+#define CPR0_SPCID_SPCIDV0_DIV3	0x03000000
+#define CPR0_SPCID_SPCIDV0_DIV4	0x00000000
 #define CPR0_PERD_PERDV0_MASK	0x07000000
 #endif
 

include/ppc4xx.h

@@ -221,6 +221,8 @@ static inline void set_mcsr(u32 val)
 	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
 }
 
+int ppc4xx_pci_sync_clock_config(u32 async);
+
 #endif	/* __ASSEMBLY__ */
 
 /* for multi-cpu support */