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@@ -474,8 +474,27 @@ static void program_ecc(u32 start_address,
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blank_string(strlen(str));
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} else {
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/* ECC bit set method for cached memory */
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+#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
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+ /*
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+ * Some boards (like lwmon5) need to preserve the memory
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+ * content upon ECC generation (for the log-buffer).
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+ * Therefore we don't fill the memory with a pattern or
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+ * just zero it, but write the same values back that are
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+ * already in the memory cells.
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+ */
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+ address_increment = CFG_CACHELINE_SIZE;
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+ end_address = current_address + num_bytes;
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+
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+ current_address = start_address;
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+ while (current_address < end_address) {
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+ ppcDcbi(current_address);
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+ ppcDcbf(current_address);
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+ current_address += CFG_CACHELINE_SIZE;
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+ }
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+#else
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dcbz_area(start_address, num_bytes);
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dflush();
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+#endif
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}
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sync();
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@@ -518,6 +537,8 @@ long int initdram (int board_type)
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{
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u32 val;
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+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
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+ /* CL=3 */
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mtsdram(DDR0_02, 0x00000000);
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mtsdram(DDR0_00, 0x0000190A);
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@@ -558,6 +579,49 @@ long int initdram (int board_type)
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mtsdram(DDR0_43, 0x030A0200);
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mtsdram(DDR0_44, 0x00000003);
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mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
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+#else
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+ /* CL=4 */
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+ mtsdram(DDR0_02, 0x00000000);
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+
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+ mtsdram(DDR0_00, 0x0000190A);
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+ mtsdram(DDR0_01, 0x01000000);
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+ mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
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+
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+ mtsdram(DDR0_04, 0x0B030300);
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+ mtsdram(DDR0_05, 0x02020308);
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+ mtsdram(DDR0_06, 0x0003C812);
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+ mtsdram(DDR0_07, 0x00090100);
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+ mtsdram(DDR0_08, 0x03c80001);
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+ mtsdram(DDR0_09, 0x00011D5F);
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+ mtsdram(DDR0_10, 0x00000300);
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+ mtsdram(DDR0_11, 0x000CC800);
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+ mtsdram(DDR0_12, 0x00000003);
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+ mtsdram(DDR0_14, 0x00000000);
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+ mtsdram(DDR0_17, 0x1e000000);
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+ mtsdram(DDR0_18, 0x1e1e1e1e);
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+ mtsdram(DDR0_19, 0x1e1e1e1e);
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+ mtsdram(DDR0_20, 0x0B0B0B0B);
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+ mtsdram(DDR0_21, 0x0B0B0B0B);
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+#ifdef CONFIG_DDR_ECC
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+ mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
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+#else
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+ mtsdram(DDR0_22, 0x00267F0B);
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+#endif
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+
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+ mtsdram(DDR0_23, 0x01000000);
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+ mtsdram(DDR0_24, 0x01010001);
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+
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+ mtsdram(DDR0_26, 0x2D93028A);
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+ mtsdram(DDR0_27, 0x0784682B);
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+
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+ mtsdram(DDR0_28, 0x00000080);
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+ mtsdram(DDR0_31, 0x00000000);
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+ mtsdram(DDR0_42, 0x01000008);
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+
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+ mtsdram(DDR0_43, 0x050A0200);
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+ mtsdram(DDR0_44, 0x00000005);
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+ mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
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+#endif
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wait_for_dlllock();
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