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@@ -30,6 +30,18 @@
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#include "ehci.h"
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#include "ehci.h"
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+/* Check USB PHY clock valid */
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+static int usb_phy_clk_valid(struct usb_ehci *ehci)
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+{
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+ if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
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+ in_be32(&ehci->prictrl))) {
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+ printf("USB PHY clock invalid!\n");
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+ return 0;
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+ } else {
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+ return 1;
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+ }
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+}
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+
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/*
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/*
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* Create the appropriate control structures to manage
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* Create the appropriate control structures to manage
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* a new EHCI host controller.
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* a new EHCI host controller.
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@@ -82,18 +94,16 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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udelay(1000); /* delay required for PHY Clk to appear */
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udelay(1000); /* delay required for PHY Clk to appear */
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#endif
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#endif
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out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
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out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
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+ setbits_be32(&ehci->control, USB_EN);
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} else {
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} else {
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-#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
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- clrbits_be32(&ehci->control, UTMI_PHY_EN);
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setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
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setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
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+ clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
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udelay(1000); /* delay required for PHY Clk to appear */
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udelay(1000); /* delay required for PHY Clk to appear */
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-#endif
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+ if (!usb_phy_clk_valid(ehci))
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+ return -EINVAL;
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out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
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out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
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}
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}
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- /* Enable interface. */
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- setbits_be32(&ehci->control, USB_EN);
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-
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out_be32(&ehci->prictrl, 0x0000000c);
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out_be32(&ehci->prictrl, 0x0000000c);
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out_be32(&ehci->age_cnt_limit, 0x00000040);
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out_be32(&ehci->age_cnt_limit, 0x00000040);
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out_be32(&ehci->sictrl, 0x00000001);
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out_be32(&ehci->sictrl, 0x00000001);
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