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@@ -153,12 +153,12 @@
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| SDRAM_CFG_32_BE )
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| SDRAM_CFG_32_BE )
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/* 0x43080000 */
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/* 0x43080000 */
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#endif
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#endif
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-#define CFG_SDRAM_CFG2 0x00401000;
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+#define CFG_SDRAM_CFG2 0x00401000
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/* set burst length to 8 for 32-bit data path */
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/* set burst length to 8 for 32-bit data path */
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#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
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#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
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| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
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| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
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/* 0x44480632 */
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/* 0x44480632 */
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-#define CFG_DDR_MODE_2 0x8000C000;
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+#define CFG_DDR_MODE_2 0x8000C000
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#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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/*0x02000000*/
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/*0x02000000*/
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