irq-lh7a404.c 4.1 KB

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  1. /* arch/arm/mach-lh7a40x/irq-lh7a404.c
  2. *
  3. * Copyright (C) 2004 Logic Product Development
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * version 2 as published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/ptrace.h>
  14. #include <asm/hardware.h>
  15. #include <asm/irq.h>
  16. #include <asm/mach/irq.h>
  17. #include <asm/arch/irqs.h>
  18. #include "common.h"
  19. #define USE_PRIORITIES
  20. /* See Documentation/arm/Sharp-LH/VectoredInterruptController for more
  21. * information on using the vectored interrupt controller's
  22. * prioritizing feature. */
  23. static unsigned char irq_pri_vic1[] = {
  24. #if defined (USE_PRIORITIES)
  25. IRQ_GPIO3INTR, /* CPLD */
  26. IRQ_DMAM2P4, IRQ_DMAM2P5, /* AC97 */
  27. #endif
  28. };
  29. static unsigned char irq_pri_vic2[] = {
  30. #if defined (USE_PRIORITIES)
  31. IRQ_T3UI, /* Timer */
  32. IRQ_GPIO7INTR, /* CPLD */
  33. IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR,
  34. IRQ_LCDINTR, /* LCD */
  35. IRQ_TSCINTR, /* ADC/Touchscreen */
  36. #endif
  37. };
  38. /* CPU IRQ handling */
  39. static void lh7a404_vic1_mask_irq (u32 irq)
  40. {
  41. VIC1_INTENCLR = (1 << irq);
  42. }
  43. static void lh7a404_vic1_unmask_irq (u32 irq)
  44. {
  45. VIC1_INTEN = (1 << irq);
  46. }
  47. static void lh7a404_vic2_mask_irq (u32 irq)
  48. {
  49. VIC2_INTENCLR = (1 << (irq - 32));
  50. }
  51. static void lh7a404_vic2_unmask_irq (u32 irq)
  52. {
  53. VIC2_INTEN = (1 << (irq - 32));
  54. }
  55. static void lh7a404_vic1_ack_gpio_irq (u32 irq)
  56. {
  57. GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
  58. VIC1_INTENCLR = (1 << irq);
  59. }
  60. static void lh7a404_vic2_ack_gpio_irq (u32 irq)
  61. {
  62. GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
  63. VIC2_INTENCLR = (1 << irq);
  64. }
  65. static struct irqchip lh7a404_vic1_chip = {
  66. .ack = lh7a404_vic1_mask_irq, /* Because level-triggered */
  67. .mask = lh7a404_vic1_mask_irq,
  68. .unmask = lh7a404_vic1_unmask_irq,
  69. };
  70. static struct irqchip lh7a404_vic2_chip = {
  71. .ack = lh7a404_vic2_mask_irq, /* Because level-triggered */
  72. .mask = lh7a404_vic2_mask_irq,
  73. .unmask = lh7a404_vic2_unmask_irq,
  74. };
  75. static struct irqchip lh7a404_gpio_vic1_chip = {
  76. .ack = lh7a404_vic1_ack_gpio_irq,
  77. .mask = lh7a404_vic1_mask_irq,
  78. .unmask = lh7a404_vic1_unmask_irq,
  79. };
  80. static struct irqchip lh7a404_gpio_vic2_chip = {
  81. .ack = lh7a404_vic2_ack_gpio_irq,
  82. .mask = lh7a404_vic2_mask_irq,
  83. .unmask = lh7a404_vic2_unmask_irq,
  84. };
  85. /* IRQ initialization */
  86. #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
  87. extern void* branch_irq_lh7a400;
  88. #endif
  89. void __init lh7a404_init_irq (void)
  90. {
  91. int irq;
  92. #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
  93. #define NOP 0xe1a00000 /* mov r0, r0 */
  94. branch_irq_lh7a400 = NOP;
  95. #endif
  96. VIC1_INTENCLR = 0xffffffff;
  97. VIC2_INTENCLR = 0xffffffff;
  98. VIC1_INTSEL = 0; /* All IRQs */
  99. VIC2_INTSEL = 0; /* All IRQs */
  100. VIC1_NVADDR = VA_VIC1DEFAULT;
  101. VIC2_NVADDR = VA_VIC2DEFAULT;
  102. VIC1_VECTADDR = 0;
  103. VIC2_VECTADDR = 0;
  104. GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */
  105. barrier ();
  106. /* Install prioritized interrupts, if there are any. */
  107. /* The | 0x20*/
  108. for (irq = 0; irq < 16; ++irq) {
  109. (&VIC1_VAD0)[irq]
  110. = (irq < ARRAY_SIZE (irq_pri_vic1))
  111. ? (irq_pri_vic1[irq] | VA_VECTORED) : 0;
  112. (&VIC1_VECTCNTL0)[irq]
  113. = (irq < ARRAY_SIZE (irq_pri_vic1))
  114. ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0;
  115. (&VIC2_VAD0)[irq]
  116. = (irq < ARRAY_SIZE (irq_pri_vic2))
  117. ? (irq_pri_vic2[irq] | VA_VECTORED) : 0;
  118. (&VIC2_VECTCNTL0)[irq]
  119. = (irq < ARRAY_SIZE (irq_pri_vic2))
  120. ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0;
  121. }
  122. for (irq = 0; irq < NR_IRQS; ++irq) {
  123. switch (irq) {
  124. case IRQ_GPIO0INTR:
  125. case IRQ_GPIO1INTR:
  126. case IRQ_GPIO2INTR:
  127. case IRQ_GPIO3INTR:
  128. case IRQ_GPIO4INTR:
  129. case IRQ_GPIO5INTR:
  130. case IRQ_GPIO6INTR:
  131. case IRQ_GPIO7INTR:
  132. set_irq_chip (irq, irq < 32
  133. ? &lh7a404_gpio_vic1_chip
  134. : &lh7a404_gpio_vic2_chip);
  135. set_irq_handler (irq, do_level_IRQ); /* OK default */
  136. break;
  137. default:
  138. set_irq_chip (irq, irq < 32
  139. ? &lh7a404_vic1_chip
  140. : &lh7a404_vic2_chip);
  141. set_irq_handler (irq, do_level_IRQ);
  142. }
  143. set_irq_flags (irq, IRQF_VALID);
  144. }
  145. lh7a40x_init_board_irq ();
  146. }