Kconfig 65 KB

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  1. config ARM
  2. bool
  3. default y
  4. select HAVE_AOUT
  5. select HAVE_DMA_API_DEBUG
  6. select HAVE_IDE if PCI || ISA || PCMCIA
  7. select HAVE_MEMBLOCK
  8. select RTC_LIB
  9. select SYS_SUPPORTS_APM_EMULATION
  10. select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  11. select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  12. select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  13. select HAVE_ARCH_KGDB
  14. select HAVE_ARCH_TRACEHOOK
  15. select HAVE_KPROBES if !XIP_KERNEL
  16. select HAVE_KRETPROBES if (HAVE_KPROBES)
  17. select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  18. select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  19. select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  20. select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  21. select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  22. select HAVE_GENERIC_DMA_COHERENT
  23. select HAVE_KERNEL_GZIP
  24. select HAVE_KERNEL_LZO
  25. select HAVE_KERNEL_LZMA
  26. select HAVE_KERNEL_XZ
  27. select HAVE_IRQ_WORK
  28. select HAVE_PERF_EVENTS
  29. select PERF_USE_VMALLOC
  30. select HAVE_REGS_AND_STACK_ACCESS_API
  31. select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  32. select HAVE_C_RECORDMCOUNT
  33. select HAVE_GENERIC_HARDIRQS
  34. select HARDIRQS_SW_RESEND
  35. select GENERIC_IRQ_PROBE
  36. select GENERIC_IRQ_SHOW
  37. select CPU_PM if (SUSPEND || CPU_IDLE)
  38. select GENERIC_PCI_IOMAP
  39. select HAVE_BPF_JIT
  40. help
  41. The ARM series is a line of low-power-consumption RISC chip designs
  42. licensed by ARM Ltd and targeted at embedded applications and
  43. handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
  44. manufactured, but legacy ARM-based PC hardware remains popular in
  45. Europe. There is an ARM Linux project with a web page at
  46. <http://www.arm.linux.org.uk/>.
  47. config ARM_HAS_SG_CHAIN
  48. bool
  49. config HAVE_PWM
  50. bool
  51. config MIGHT_HAVE_PCI
  52. bool
  53. config SYS_SUPPORTS_APM_EMULATION
  54. bool
  55. config GENERIC_GPIO
  56. bool
  57. config ARCH_USES_GETTIMEOFFSET
  58. bool
  59. default n
  60. config GENERIC_CLOCKEVENTS
  61. bool
  62. config GENERIC_CLOCKEVENTS_BROADCAST
  63. bool
  64. depends on GENERIC_CLOCKEVENTS
  65. default y if SMP
  66. config KTIME_SCALAR
  67. bool
  68. default y
  69. config HAVE_TCM
  70. bool
  71. select GENERIC_ALLOCATOR
  72. config HAVE_PROC_CPU
  73. bool
  74. config NO_IOPORT
  75. bool
  76. config EISA
  77. bool
  78. ---help---
  79. The Extended Industry Standard Architecture (EISA) bus was
  80. developed as an open alternative to the IBM MicroChannel bus.
  81. The EISA bus provided some of the features of the IBM MicroChannel
  82. bus while maintaining backward compatibility with cards made for
  83. the older ISA bus. The EISA bus saw limited use between 1988 and
  84. 1995 when it was made obsolete by the PCI bus.
  85. Say Y here if you are building a kernel for an EISA-based machine.
  86. Otherwise, say N.
  87. config SBUS
  88. bool
  89. config MCA
  90. bool
  91. help
  92. MicroChannel Architecture is found in some IBM PS/2 machines and
  93. laptops. It is a bus system similar to PCI or ISA. See
  94. <file:Documentation/mca.txt> (and especially the web page given
  95. there) before attempting to build an MCA bus kernel.
  96. config STACKTRACE_SUPPORT
  97. bool
  98. default y
  99. config HAVE_LATENCYTOP_SUPPORT
  100. bool
  101. depends on !SMP
  102. default y
  103. config LOCKDEP_SUPPORT
  104. bool
  105. default y
  106. config TRACE_IRQFLAGS_SUPPORT
  107. bool
  108. default y
  109. config GENERIC_LOCKBREAK
  110. bool
  111. default y
  112. depends on SMP && PREEMPT
  113. config RWSEM_GENERIC_SPINLOCK
  114. bool
  115. default y
  116. config RWSEM_XCHGADD_ALGORITHM
  117. bool
  118. config ARCH_HAS_ILOG2_U32
  119. bool
  120. config ARCH_HAS_ILOG2_U64
  121. bool
  122. config ARCH_HAS_CPUFREQ
  123. bool
  124. help
  125. Internal node to signify that the ARCH has CPUFREQ support
  126. and that the relevant menu configurations are displayed for
  127. it.
  128. config ARCH_HAS_CPU_IDLE_WAIT
  129. def_bool y
  130. config GENERIC_HWEIGHT
  131. bool
  132. default y
  133. config GENERIC_CALIBRATE_DELAY
  134. bool
  135. default y
  136. config ARCH_MAY_HAVE_PC_FDC
  137. bool
  138. config ZONE_DMA
  139. bool
  140. config NEED_DMA_MAP_STATE
  141. def_bool y
  142. config ARCH_HAS_DMA_SET_COHERENT_MASK
  143. bool
  144. config GENERIC_ISA_DMA
  145. bool
  146. config FIQ
  147. bool
  148. config NEED_RET_TO_USER
  149. bool
  150. config ARCH_MTD_XIP
  151. bool
  152. config VECTORS_BASE
  153. hex
  154. default 0xffff0000 if MMU || CPU_HIGH_VECTOR
  155. default DRAM_BASE if REMAP_VECTORS_TO_RAM
  156. default 0x00000000
  157. help
  158. The base address of exception vectors.
  159. config ARM_PATCH_PHYS_VIRT
  160. bool "Patch physical to virtual translations at runtime" if EMBEDDED
  161. default y
  162. depends on !XIP_KERNEL && MMU
  163. depends on !ARCH_REALVIEW || !SPARSEMEM
  164. help
  165. Patch phys-to-virt and virt-to-phys translation functions at
  166. boot and module load time according to the position of the
  167. kernel in system memory.
  168. This can only be used with non-XIP MMU kernels where the base
  169. of physical memory is at a 16MB boundary.
  170. Only disable this option if you know that you do not require
  171. this feature (eg, building a kernel for a single machine) and
  172. you need to shrink the kernel to the minimal size.
  173. config NEED_MACH_IO_H
  174. bool
  175. help
  176. Select this when mach/io.h is required to provide special
  177. definitions for this platform. The need for mach/io.h should
  178. be avoided when possible.
  179. config NEED_MACH_MEMORY_H
  180. bool
  181. help
  182. Select this when mach/memory.h is required to provide special
  183. definitions for this platform. The need for mach/memory.h should
  184. be avoided when possible.
  185. config PHYS_OFFSET
  186. hex "Physical address of main memory" if MMU
  187. depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
  188. default DRAM_BASE if !MMU
  189. help
  190. Please provide the physical address corresponding to the
  191. location of main memory in your system.
  192. config GENERIC_BUG
  193. def_bool y
  194. depends on BUG
  195. source "init/Kconfig"
  196. source "kernel/Kconfig.freezer"
  197. menu "System Type"
  198. config MMU
  199. bool "MMU-based Paged Memory Management Support"
  200. default y
  201. help
  202. Select if you want MMU-based virtualised addressing space
  203. support by paged memory management. If unsure, say 'Y'.
  204. #
  205. # The "ARM system type" choice list is ordered alphabetically by option
  206. # text. Please add new entries in the option alphabetic order.
  207. #
  208. choice
  209. prompt "ARM system type"
  210. default ARCH_VERSATILE
  211. config ARCH_INTEGRATOR
  212. bool "ARM Ltd. Integrator family"
  213. select ARM_AMBA
  214. select ARCH_HAS_CPUFREQ
  215. select CLKDEV_LOOKUP
  216. select HAVE_MACH_CLKDEV
  217. select HAVE_TCM
  218. select ICST
  219. select GENERIC_CLOCKEVENTS
  220. select PLAT_VERSATILE
  221. select PLAT_VERSATILE_FPGA_IRQ
  222. select NEED_MACH_IO_H
  223. select NEED_MACH_MEMORY_H
  224. select SPARSE_IRQ
  225. select MULTI_IRQ_HANDLER
  226. help
  227. Support for ARM's Integrator platform.
  228. config ARCH_REALVIEW
  229. bool "ARM Ltd. RealView family"
  230. select ARM_AMBA
  231. select CLKDEV_LOOKUP
  232. select HAVE_MACH_CLKDEV
  233. select ICST
  234. select GENERIC_CLOCKEVENTS
  235. select ARCH_WANT_OPTIONAL_GPIOLIB
  236. select PLAT_VERSATILE
  237. select PLAT_VERSATILE_CLCD
  238. select ARM_TIMER_SP804
  239. select GPIO_PL061 if GPIOLIB
  240. select NEED_MACH_MEMORY_H
  241. help
  242. This enables support for ARM Ltd RealView boards.
  243. config ARCH_VERSATILE
  244. bool "ARM Ltd. Versatile family"
  245. select ARM_AMBA
  246. select ARM_VIC
  247. select CLKDEV_LOOKUP
  248. select HAVE_MACH_CLKDEV
  249. select ICST
  250. select GENERIC_CLOCKEVENTS
  251. select ARCH_WANT_OPTIONAL_GPIOLIB
  252. select PLAT_VERSATILE
  253. select PLAT_VERSATILE_CLCD
  254. select PLAT_VERSATILE_FPGA_IRQ
  255. select ARM_TIMER_SP804
  256. help
  257. This enables support for ARM Ltd Versatile board.
  258. config ARCH_VEXPRESS
  259. bool "ARM Ltd. Versatile Express family"
  260. select ARCH_WANT_OPTIONAL_GPIOLIB
  261. select ARM_AMBA
  262. select ARM_TIMER_SP804
  263. select CLKDEV_LOOKUP
  264. select HAVE_MACH_CLKDEV
  265. select GENERIC_CLOCKEVENTS
  266. select HAVE_CLK
  267. select HAVE_PATA_PLATFORM
  268. select ICST
  269. select NO_IOPORT
  270. select PLAT_VERSATILE
  271. select PLAT_VERSATILE_CLCD
  272. help
  273. This enables support for the ARM Ltd Versatile Express boards.
  274. config ARCH_AT91
  275. bool "Atmel AT91"
  276. select ARCH_REQUIRE_GPIOLIB
  277. select HAVE_CLK
  278. select CLKDEV_LOOKUP
  279. select IRQ_DOMAIN
  280. select NEED_MACH_IO_H if PCCARD
  281. help
  282. This enables support for systems based on the Atmel AT91RM9200,
  283. AT91SAM9 processors.
  284. config ARCH_BCMRING
  285. bool "Broadcom BCMRING"
  286. depends on MMU
  287. select CPU_V6
  288. select ARM_AMBA
  289. select ARM_TIMER_SP804
  290. select CLKDEV_LOOKUP
  291. select GENERIC_CLOCKEVENTS
  292. select ARCH_WANT_OPTIONAL_GPIOLIB
  293. help
  294. Support for Broadcom's BCMRing platform.
  295. config ARCH_HIGHBANK
  296. bool "Calxeda Highbank-based"
  297. select ARCH_WANT_OPTIONAL_GPIOLIB
  298. select ARM_AMBA
  299. select ARM_GIC
  300. select ARM_TIMER_SP804
  301. select CACHE_L2X0
  302. select CLKDEV_LOOKUP
  303. select CPU_V7
  304. select GENERIC_CLOCKEVENTS
  305. select HAVE_ARM_SCU
  306. select HAVE_SMP
  307. select SPARSE_IRQ
  308. select USE_OF
  309. help
  310. Support for the Calxeda Highbank SoC based boards.
  311. config ARCH_CLPS711X
  312. bool "Cirrus Logic CLPS711x/EP721x-based"
  313. select CPU_ARM720T
  314. select ARCH_USES_GETTIMEOFFSET
  315. select NEED_MACH_MEMORY_H
  316. help
  317. Support for Cirrus Logic 711x/721x based boards.
  318. config ARCH_CNS3XXX
  319. bool "Cavium Networks CNS3XXX family"
  320. select CPU_V6K
  321. select GENERIC_CLOCKEVENTS
  322. select ARM_GIC
  323. select MIGHT_HAVE_CACHE_L2X0
  324. select MIGHT_HAVE_PCI
  325. select PCI_DOMAINS if PCI
  326. help
  327. Support for Cavium Networks CNS3XXX platform.
  328. config ARCH_GEMINI
  329. bool "Cortina Systems Gemini"
  330. select CPU_FA526
  331. select ARCH_REQUIRE_GPIOLIB
  332. select ARCH_USES_GETTIMEOFFSET
  333. help
  334. Support for the Cortina Systems Gemini family SoCs
  335. config ARCH_PRIMA2
  336. bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
  337. select CPU_V7
  338. select NO_IOPORT
  339. select GENERIC_CLOCKEVENTS
  340. select CLKDEV_LOOKUP
  341. select GENERIC_IRQ_CHIP
  342. select MIGHT_HAVE_CACHE_L2X0
  343. select USE_OF
  344. select ZONE_DMA
  345. help
  346. Support for CSR SiRFSoC ARM Cortex A9 Platform
  347. config ARCH_EBSA110
  348. bool "EBSA-110"
  349. select CPU_SA110
  350. select ISA
  351. select NO_IOPORT
  352. select ARCH_USES_GETTIMEOFFSET
  353. select NEED_MACH_IO_H
  354. select NEED_MACH_MEMORY_H
  355. help
  356. This is an evaluation board for the StrongARM processor available
  357. from Digital. It has limited hardware on-board, including an
  358. Ethernet interface, two PCMCIA sockets, two serial ports and a
  359. parallel port.
  360. config ARCH_EP93XX
  361. bool "EP93xx-based"
  362. select CPU_ARM920T
  363. select ARM_AMBA
  364. select ARM_VIC
  365. select CLKDEV_LOOKUP
  366. select ARCH_REQUIRE_GPIOLIB
  367. select ARCH_HAS_HOLES_MEMORYMODEL
  368. select ARCH_USES_GETTIMEOFFSET
  369. select NEED_MACH_MEMORY_H
  370. help
  371. This enables support for the Cirrus EP93xx series of CPUs.
  372. config ARCH_FOOTBRIDGE
  373. bool "FootBridge"
  374. select CPU_SA110
  375. select FOOTBRIDGE
  376. select GENERIC_CLOCKEVENTS
  377. select HAVE_IDE
  378. select NEED_MACH_IO_H
  379. select NEED_MACH_MEMORY_H
  380. help
  381. Support for systems based on the DC21285 companion chip
  382. ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
  383. config ARCH_MXC
  384. bool "Freescale MXC/iMX-based"
  385. select GENERIC_CLOCKEVENTS
  386. select ARCH_REQUIRE_GPIOLIB
  387. select CLKDEV_LOOKUP
  388. select CLKSRC_MMIO
  389. select GENERIC_IRQ_CHIP
  390. select MULTI_IRQ_HANDLER
  391. help
  392. Support for Freescale MXC/iMX-based family of processors
  393. config ARCH_MXS
  394. bool "Freescale MXS-based"
  395. select GENERIC_CLOCKEVENTS
  396. select ARCH_REQUIRE_GPIOLIB
  397. select CLKDEV_LOOKUP
  398. select CLKSRC_MMIO
  399. select HAVE_CLK_PREPARE
  400. help
  401. Support for Freescale MXS-based family of processors
  402. config ARCH_NETX
  403. bool "Hilscher NetX based"
  404. select CLKSRC_MMIO
  405. select CPU_ARM926T
  406. select ARM_VIC
  407. select GENERIC_CLOCKEVENTS
  408. help
  409. This enables support for systems based on the Hilscher NetX Soc
  410. config ARCH_H720X
  411. bool "Hynix HMS720x-based"
  412. select CPU_ARM720T
  413. select ISA_DMA_API
  414. select ARCH_USES_GETTIMEOFFSET
  415. help
  416. This enables support for systems based on the Hynix HMS720x
  417. config ARCH_IOP13XX
  418. bool "IOP13xx-based"
  419. depends on MMU
  420. select CPU_XSC3
  421. select PLAT_IOP
  422. select PCI
  423. select ARCH_SUPPORTS_MSI
  424. select VMSPLIT_1G
  425. select NEED_MACH_IO_H
  426. select NEED_MACH_MEMORY_H
  427. select NEED_RET_TO_USER
  428. help
  429. Support for Intel's IOP13XX (XScale) family of processors.
  430. config ARCH_IOP32X
  431. bool "IOP32x-based"
  432. depends on MMU
  433. select CPU_XSCALE
  434. select NEED_MACH_IO_H
  435. select NEED_RET_TO_USER
  436. select PLAT_IOP
  437. select PCI
  438. select ARCH_REQUIRE_GPIOLIB
  439. help
  440. Support for Intel's 80219 and IOP32X (XScale) family of
  441. processors.
  442. config ARCH_IOP33X
  443. bool "IOP33x-based"
  444. depends on MMU
  445. select CPU_XSCALE
  446. select NEED_MACH_IO_H
  447. select NEED_RET_TO_USER
  448. select PLAT_IOP
  449. select PCI
  450. select ARCH_REQUIRE_GPIOLIB
  451. help
  452. Support for Intel's IOP33X (XScale) family of processors.
  453. config ARCH_IXP23XX
  454. bool "IXP23XX-based"
  455. depends on MMU
  456. select CPU_XSC3
  457. select PCI
  458. select ARCH_USES_GETTIMEOFFSET
  459. select NEED_MACH_IO_H
  460. select NEED_MACH_MEMORY_H
  461. help
  462. Support for Intel's IXP23xx (XScale) family of processors.
  463. config ARCH_IXP2000
  464. bool "IXP2400/2800-based"
  465. depends on MMU
  466. select CPU_XSCALE
  467. select PCI
  468. select ARCH_USES_GETTIMEOFFSET
  469. select NEED_MACH_IO_H
  470. select NEED_MACH_MEMORY_H
  471. help
  472. Support for Intel's IXP2400/2800 (XScale) family of processors.
  473. config ARCH_IXP4XX
  474. bool "IXP4xx-based"
  475. depends on MMU
  476. select ARCH_HAS_DMA_SET_COHERENT_MASK
  477. select CLKSRC_MMIO
  478. select CPU_XSCALE
  479. select GENERIC_GPIO
  480. select GENERIC_CLOCKEVENTS
  481. select MIGHT_HAVE_PCI
  482. select NEED_MACH_IO_H
  483. select DMABOUNCE if PCI
  484. help
  485. Support for Intel's IXP4XX (XScale) family of processors.
  486. config ARCH_DOVE
  487. bool "Marvell Dove"
  488. select CPU_V7
  489. select PCI
  490. select ARCH_REQUIRE_GPIOLIB
  491. select GENERIC_CLOCKEVENTS
  492. select NEED_MACH_IO_H
  493. select PLAT_ORION
  494. help
  495. Support for the Marvell Dove SoC 88AP510
  496. config ARCH_KIRKWOOD
  497. bool "Marvell Kirkwood"
  498. select CPU_FEROCEON
  499. select PCI
  500. select ARCH_REQUIRE_GPIOLIB
  501. select GENERIC_CLOCKEVENTS
  502. select NEED_MACH_IO_H
  503. select PLAT_ORION
  504. help
  505. Support for the following Marvell Kirkwood series SoCs:
  506. 88F6180, 88F6192 and 88F6281.
  507. config ARCH_LPC32XX
  508. bool "NXP LPC32XX"
  509. select CLKSRC_MMIO
  510. select CPU_ARM926T
  511. select ARCH_REQUIRE_GPIOLIB
  512. select HAVE_IDE
  513. select ARM_AMBA
  514. select USB_ARCH_HAS_OHCI
  515. select CLKDEV_LOOKUP
  516. select GENERIC_CLOCKEVENTS
  517. help
  518. Support for the NXP LPC32XX family of processors
  519. config ARCH_MV78XX0
  520. bool "Marvell MV78xx0"
  521. select CPU_FEROCEON
  522. select PCI
  523. select ARCH_REQUIRE_GPIOLIB
  524. select GENERIC_CLOCKEVENTS
  525. select NEED_MACH_IO_H
  526. select PLAT_ORION
  527. help
  528. Support for the following Marvell MV78xx0 series SoCs:
  529. MV781x0, MV782x0.
  530. config ARCH_ORION5X
  531. bool "Marvell Orion"
  532. depends on MMU
  533. select CPU_FEROCEON
  534. select PCI
  535. select ARCH_REQUIRE_GPIOLIB
  536. select GENERIC_CLOCKEVENTS
  537. select PLAT_ORION
  538. help
  539. Support for the following Marvell Orion 5x series SoCs:
  540. Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
  541. Orion-2 (5281), Orion-1-90 (6183).
  542. config ARCH_MMP
  543. bool "Marvell PXA168/910/MMP2"
  544. depends on MMU
  545. select ARCH_REQUIRE_GPIOLIB
  546. select CLKDEV_LOOKUP
  547. select GENERIC_CLOCKEVENTS
  548. select GPIO_PXA
  549. select PLAT_PXA
  550. select SPARSE_IRQ
  551. select GENERIC_ALLOCATOR
  552. help
  553. Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
  554. config ARCH_KS8695
  555. bool "Micrel/Kendin KS8695"
  556. select CPU_ARM922T
  557. select ARCH_REQUIRE_GPIOLIB
  558. select ARCH_USES_GETTIMEOFFSET
  559. select NEED_MACH_MEMORY_H
  560. help
  561. Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
  562. System-on-Chip devices.
  563. config ARCH_W90X900
  564. bool "Nuvoton W90X900 CPU"
  565. select CPU_ARM926T
  566. select ARCH_REQUIRE_GPIOLIB
  567. select CLKDEV_LOOKUP
  568. select CLKSRC_MMIO
  569. select GENERIC_CLOCKEVENTS
  570. help
  571. Support for Nuvoton (Winbond logic dept.) ARM9 processor,
  572. At present, the w90x900 has been renamed nuc900, regarding
  573. the ARM series product line, you can login the following
  574. link address to know more.
  575. <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
  576. ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
  577. config ARCH_TEGRA
  578. bool "NVIDIA Tegra"
  579. select CLKDEV_LOOKUP
  580. select CLKSRC_MMIO
  581. select GENERIC_CLOCKEVENTS
  582. select GENERIC_GPIO
  583. select HAVE_CLK
  584. select HAVE_SMP
  585. select MIGHT_HAVE_CACHE_L2X0
  586. select NEED_MACH_IO_H if PCI
  587. select ARCH_HAS_CPUFREQ
  588. help
  589. This enables support for NVIDIA Tegra based systems (Tegra APX,
  590. Tegra 6xx and Tegra 2 series).
  591. config ARCH_PICOXCELL
  592. bool "Picochip picoXcell"
  593. select ARCH_REQUIRE_GPIOLIB
  594. select ARM_PATCH_PHYS_VIRT
  595. select ARM_VIC
  596. select CPU_V6K
  597. select DW_APB_TIMER
  598. select GENERIC_CLOCKEVENTS
  599. select GENERIC_GPIO
  600. select HAVE_TCM
  601. select NO_IOPORT
  602. select SPARSE_IRQ
  603. select USE_OF
  604. help
  605. This enables support for systems based on the Picochip picoXcell
  606. family of Femtocell devices. The picoxcell support requires device tree
  607. for all boards.
  608. config ARCH_PNX4008
  609. bool "Philips Nexperia PNX4008 Mobile"
  610. select CPU_ARM926T
  611. select CLKDEV_LOOKUP
  612. select ARCH_USES_GETTIMEOFFSET
  613. help
  614. This enables support for Philips PNX4008 mobile platform.
  615. config ARCH_PXA
  616. bool "PXA2xx/PXA3xx-based"
  617. depends on MMU
  618. select ARCH_MTD_XIP
  619. select ARCH_HAS_CPUFREQ
  620. select CLKDEV_LOOKUP
  621. select CLKSRC_MMIO
  622. select ARCH_REQUIRE_GPIOLIB
  623. select GENERIC_CLOCKEVENTS
  624. select GPIO_PXA
  625. select PLAT_PXA
  626. select SPARSE_IRQ
  627. select AUTO_ZRELADDR
  628. select MULTI_IRQ_HANDLER
  629. select ARM_CPU_SUSPEND if PM
  630. select HAVE_IDE
  631. help
  632. Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
  633. config ARCH_MSM
  634. bool "Qualcomm MSM"
  635. select HAVE_CLK
  636. select GENERIC_CLOCKEVENTS
  637. select ARCH_REQUIRE_GPIOLIB
  638. select CLKDEV_LOOKUP
  639. help
  640. Support for Qualcomm MSM/QSD based systems. This runs on the
  641. apps processor of the MSM/QSD and depends on a shared memory
  642. interface to the modem processor which runs the baseband
  643. stack and controls some vital subsystems
  644. (clock and power control, etc).
  645. config ARCH_SHMOBILE
  646. bool "Renesas SH-Mobile / R-Mobile"
  647. select HAVE_CLK
  648. select CLKDEV_LOOKUP
  649. select HAVE_MACH_CLKDEV
  650. select HAVE_SMP
  651. select GENERIC_CLOCKEVENTS
  652. select MIGHT_HAVE_CACHE_L2X0
  653. select NO_IOPORT
  654. select SPARSE_IRQ
  655. select MULTI_IRQ_HANDLER
  656. select PM_GENERIC_DOMAINS if PM
  657. select NEED_MACH_MEMORY_H
  658. help
  659. Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
  660. config ARCH_RPC
  661. bool "RiscPC"
  662. select ARCH_ACORN
  663. select FIQ
  664. select ARCH_MAY_HAVE_PC_FDC
  665. select HAVE_PATA_PLATFORM
  666. select ISA_DMA_API
  667. select NO_IOPORT
  668. select ARCH_SPARSEMEM_ENABLE
  669. select ARCH_USES_GETTIMEOFFSET
  670. select HAVE_IDE
  671. select NEED_MACH_IO_H
  672. select NEED_MACH_MEMORY_H
  673. help
  674. On the Acorn Risc-PC, Linux can support the internal IDE disk and
  675. CD-ROM interface, serial and parallel port, and the floppy drive.
  676. config ARCH_SA1100
  677. bool "SA1100-based"
  678. select CLKSRC_MMIO
  679. select CPU_SA1100
  680. select ISA
  681. select ARCH_SPARSEMEM_ENABLE
  682. select ARCH_MTD_XIP
  683. select ARCH_HAS_CPUFREQ
  684. select CPU_FREQ
  685. select GENERIC_CLOCKEVENTS
  686. select CLKDEV_LOOKUP
  687. select ARCH_REQUIRE_GPIOLIB
  688. select HAVE_IDE
  689. select NEED_MACH_MEMORY_H
  690. select SPARSE_IRQ
  691. help
  692. Support for StrongARM 11x0 based boards.
  693. config ARCH_S3C24XX
  694. bool "Samsung S3C24XX SoCs"
  695. select GENERIC_GPIO
  696. select ARCH_HAS_CPUFREQ
  697. select HAVE_CLK
  698. select CLKDEV_LOOKUP
  699. select ARCH_USES_GETTIMEOFFSET
  700. select HAVE_S3C2410_I2C if I2C
  701. select HAVE_S3C_RTC if RTC_CLASS
  702. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  703. select NEED_MACH_IO_H
  704. help
  705. Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
  706. and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
  707. (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
  708. Samsung SMDK2410 development board (and derivatives).
  709. config ARCH_S3C64XX
  710. bool "Samsung S3C64XX"
  711. select PLAT_SAMSUNG
  712. select CPU_V6
  713. select ARM_VIC
  714. select HAVE_CLK
  715. select HAVE_TCM
  716. select CLKDEV_LOOKUP
  717. select NO_IOPORT
  718. select ARCH_USES_GETTIMEOFFSET
  719. select ARCH_HAS_CPUFREQ
  720. select ARCH_REQUIRE_GPIOLIB
  721. select SAMSUNG_CLKSRC
  722. select SAMSUNG_IRQ_VIC_TIMER
  723. select S3C_GPIO_TRACK
  724. select S3C_DEV_NAND
  725. select USB_ARCH_HAS_OHCI
  726. select SAMSUNG_GPIOLIB_4BIT
  727. select HAVE_S3C2410_I2C if I2C
  728. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  729. help
  730. Samsung S3C64XX series based systems
  731. config ARCH_S5P64X0
  732. bool "Samsung S5P6440 S5P6450"
  733. select CPU_V6
  734. select GENERIC_GPIO
  735. select HAVE_CLK
  736. select CLKDEV_LOOKUP
  737. select CLKSRC_MMIO
  738. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  739. select GENERIC_CLOCKEVENTS
  740. select HAVE_S3C2410_I2C if I2C
  741. select HAVE_S3C_RTC if RTC_CLASS
  742. help
  743. Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
  744. SMDK6450.
  745. config ARCH_S5PC100
  746. bool "Samsung S5PC100"
  747. select GENERIC_GPIO
  748. select HAVE_CLK
  749. select CLKDEV_LOOKUP
  750. select CPU_V7
  751. select ARCH_USES_GETTIMEOFFSET
  752. select HAVE_S3C2410_I2C if I2C
  753. select HAVE_S3C_RTC if RTC_CLASS
  754. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  755. help
  756. Samsung S5PC100 series based systems
  757. config ARCH_S5PV210
  758. bool "Samsung S5PV210/S5PC110"
  759. select CPU_V7
  760. select ARCH_SPARSEMEM_ENABLE
  761. select ARCH_HAS_HOLES_MEMORYMODEL
  762. select GENERIC_GPIO
  763. select HAVE_CLK
  764. select CLKDEV_LOOKUP
  765. select CLKSRC_MMIO
  766. select ARCH_HAS_CPUFREQ
  767. select GENERIC_CLOCKEVENTS
  768. select HAVE_S3C2410_I2C if I2C
  769. select HAVE_S3C_RTC if RTC_CLASS
  770. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  771. select NEED_MACH_MEMORY_H
  772. help
  773. Samsung S5PV210/S5PC110 series based systems
  774. config ARCH_EXYNOS
  775. bool "SAMSUNG EXYNOS"
  776. select CPU_V7
  777. select ARCH_SPARSEMEM_ENABLE
  778. select ARCH_HAS_HOLES_MEMORYMODEL
  779. select GENERIC_GPIO
  780. select HAVE_CLK
  781. select CLKDEV_LOOKUP
  782. select ARCH_HAS_CPUFREQ
  783. select GENERIC_CLOCKEVENTS
  784. select HAVE_S3C_RTC if RTC_CLASS
  785. select HAVE_S3C2410_I2C if I2C
  786. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  787. select NEED_MACH_MEMORY_H
  788. help
  789. Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
  790. config ARCH_SHARK
  791. bool "Shark"
  792. select CPU_SA110
  793. select ISA
  794. select ISA_DMA
  795. select ZONE_DMA
  796. select PCI
  797. select ARCH_USES_GETTIMEOFFSET
  798. select NEED_MACH_MEMORY_H
  799. select NEED_MACH_IO_H
  800. help
  801. Support for the StrongARM based Digital DNARD machine, also known
  802. as "Shark" (<http://www.shark-linux.de/shark.html>).
  803. config ARCH_U300
  804. bool "ST-Ericsson U300 Series"
  805. depends on MMU
  806. select CLKSRC_MMIO
  807. select CPU_ARM926T
  808. select HAVE_TCM
  809. select ARM_AMBA
  810. select ARM_PATCH_PHYS_VIRT
  811. select ARM_VIC
  812. select GENERIC_CLOCKEVENTS
  813. select CLKDEV_LOOKUP
  814. select HAVE_MACH_CLKDEV
  815. select GENERIC_GPIO
  816. select ARCH_REQUIRE_GPIOLIB
  817. help
  818. Support for ST-Ericsson U300 series mobile platforms.
  819. config ARCH_U8500
  820. bool "ST-Ericsson U8500 Series"
  821. depends on MMU
  822. select CPU_V7
  823. select ARM_AMBA
  824. select GENERIC_CLOCKEVENTS
  825. select CLKDEV_LOOKUP
  826. select ARCH_REQUIRE_GPIOLIB
  827. select ARCH_HAS_CPUFREQ
  828. select HAVE_SMP
  829. select MIGHT_HAVE_CACHE_L2X0
  830. help
  831. Support for ST-Ericsson's Ux500 architecture
  832. config ARCH_NOMADIK
  833. bool "STMicroelectronics Nomadik"
  834. select ARM_AMBA
  835. select ARM_VIC
  836. select CPU_ARM926T
  837. select CLKDEV_LOOKUP
  838. select GENERIC_CLOCKEVENTS
  839. select MIGHT_HAVE_CACHE_L2X0
  840. select ARCH_REQUIRE_GPIOLIB
  841. help
  842. Support for the Nomadik platform by ST-Ericsson
  843. config ARCH_DAVINCI
  844. bool "TI DaVinci"
  845. select GENERIC_CLOCKEVENTS
  846. select ARCH_REQUIRE_GPIOLIB
  847. select ZONE_DMA
  848. select HAVE_IDE
  849. select CLKDEV_LOOKUP
  850. select GENERIC_ALLOCATOR
  851. select GENERIC_IRQ_CHIP
  852. select ARCH_HAS_HOLES_MEMORYMODEL
  853. help
  854. Support for TI's DaVinci platform.
  855. config ARCH_OMAP
  856. bool "TI OMAP"
  857. select HAVE_CLK
  858. select ARCH_REQUIRE_GPIOLIB
  859. select ARCH_HAS_CPUFREQ
  860. select CLKSRC_MMIO
  861. select GENERIC_CLOCKEVENTS
  862. select ARCH_HAS_HOLES_MEMORYMODEL
  863. help
  864. Support for TI's OMAP platform (OMAP1/2/3/4).
  865. config PLAT_SPEAR
  866. bool "ST SPEAr"
  867. select ARM_AMBA
  868. select ARCH_REQUIRE_GPIOLIB
  869. select CLKDEV_LOOKUP
  870. select CLKSRC_MMIO
  871. select GENERIC_CLOCKEVENTS
  872. select HAVE_CLK
  873. help
  874. Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
  875. config ARCH_VT8500
  876. bool "VIA/WonderMedia 85xx"
  877. select CPU_ARM926T
  878. select GENERIC_GPIO
  879. select ARCH_HAS_CPUFREQ
  880. select GENERIC_CLOCKEVENTS
  881. select ARCH_REQUIRE_GPIOLIB
  882. select HAVE_PWM
  883. help
  884. Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
  885. config ARCH_ZYNQ
  886. bool "Xilinx Zynq ARM Cortex A9 Platform"
  887. select CPU_V7
  888. select GENERIC_CLOCKEVENTS
  889. select CLKDEV_LOOKUP
  890. select ARM_GIC
  891. select ARM_AMBA
  892. select ICST
  893. select MIGHT_HAVE_CACHE_L2X0
  894. select USE_OF
  895. help
  896. Support for Xilinx Zynq ARM Cortex A9 Platform
  897. endchoice
  898. #
  899. # This is sorted alphabetically by mach-* pathname. However, plat-*
  900. # Kconfigs may be included either alphabetically (according to the
  901. # plat- suffix) or along side the corresponding mach-* source.
  902. #
  903. source "arch/arm/mach-at91/Kconfig"
  904. source "arch/arm/mach-bcmring/Kconfig"
  905. source "arch/arm/mach-clps711x/Kconfig"
  906. source "arch/arm/mach-cns3xxx/Kconfig"
  907. source "arch/arm/mach-davinci/Kconfig"
  908. source "arch/arm/mach-dove/Kconfig"
  909. source "arch/arm/mach-ep93xx/Kconfig"
  910. source "arch/arm/mach-footbridge/Kconfig"
  911. source "arch/arm/mach-gemini/Kconfig"
  912. source "arch/arm/mach-h720x/Kconfig"
  913. source "arch/arm/mach-integrator/Kconfig"
  914. source "arch/arm/mach-iop32x/Kconfig"
  915. source "arch/arm/mach-iop33x/Kconfig"
  916. source "arch/arm/mach-iop13xx/Kconfig"
  917. source "arch/arm/mach-ixp4xx/Kconfig"
  918. source "arch/arm/mach-ixp2000/Kconfig"
  919. source "arch/arm/mach-ixp23xx/Kconfig"
  920. source "arch/arm/mach-kirkwood/Kconfig"
  921. source "arch/arm/mach-ks8695/Kconfig"
  922. source "arch/arm/mach-lpc32xx/Kconfig"
  923. source "arch/arm/mach-msm/Kconfig"
  924. source "arch/arm/mach-mv78xx0/Kconfig"
  925. source "arch/arm/plat-mxc/Kconfig"
  926. source "arch/arm/mach-mxs/Kconfig"
  927. source "arch/arm/mach-netx/Kconfig"
  928. source "arch/arm/mach-nomadik/Kconfig"
  929. source "arch/arm/plat-nomadik/Kconfig"
  930. source "arch/arm/plat-omap/Kconfig"
  931. source "arch/arm/mach-omap1/Kconfig"
  932. source "arch/arm/mach-omap2/Kconfig"
  933. source "arch/arm/mach-orion5x/Kconfig"
  934. source "arch/arm/mach-pxa/Kconfig"
  935. source "arch/arm/plat-pxa/Kconfig"
  936. source "arch/arm/mach-mmp/Kconfig"
  937. source "arch/arm/mach-realview/Kconfig"
  938. source "arch/arm/mach-sa1100/Kconfig"
  939. source "arch/arm/plat-samsung/Kconfig"
  940. source "arch/arm/plat-s3c24xx/Kconfig"
  941. source "arch/arm/plat-s5p/Kconfig"
  942. source "arch/arm/plat-spear/Kconfig"
  943. source "arch/arm/mach-s3c24xx/Kconfig"
  944. if ARCH_S3C24XX
  945. source "arch/arm/mach-s3c2412/Kconfig"
  946. source "arch/arm/mach-s3c2440/Kconfig"
  947. endif
  948. if ARCH_S3C64XX
  949. source "arch/arm/mach-s3c64xx/Kconfig"
  950. endif
  951. source "arch/arm/mach-s5p64x0/Kconfig"
  952. source "arch/arm/mach-s5pc100/Kconfig"
  953. source "arch/arm/mach-s5pv210/Kconfig"
  954. source "arch/arm/mach-exynos/Kconfig"
  955. source "arch/arm/mach-shmobile/Kconfig"
  956. source "arch/arm/mach-tegra/Kconfig"
  957. source "arch/arm/mach-u300/Kconfig"
  958. source "arch/arm/mach-ux500/Kconfig"
  959. source "arch/arm/mach-versatile/Kconfig"
  960. source "arch/arm/mach-vexpress/Kconfig"
  961. source "arch/arm/plat-versatile/Kconfig"
  962. source "arch/arm/mach-vt8500/Kconfig"
  963. source "arch/arm/mach-w90x900/Kconfig"
  964. # Definitions to make life easier
  965. config ARCH_ACORN
  966. bool
  967. config PLAT_IOP
  968. bool
  969. select GENERIC_CLOCKEVENTS
  970. config PLAT_ORION
  971. bool
  972. select CLKSRC_MMIO
  973. select GENERIC_IRQ_CHIP
  974. config PLAT_PXA
  975. bool
  976. config PLAT_VERSATILE
  977. bool
  978. config ARM_TIMER_SP804
  979. bool
  980. select CLKSRC_MMIO
  981. select HAVE_SCHED_CLOCK
  982. source arch/arm/mm/Kconfig
  983. config ARM_NR_BANKS
  984. int
  985. default 16 if ARCH_EP93XX
  986. default 8
  987. config IWMMXT
  988. bool "Enable iWMMXt support"
  989. depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
  990. default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
  991. help
  992. Enable support for iWMMXt context switching at run time if
  993. running on a CPU that supports it.
  994. config XSCALE_PMU
  995. bool
  996. depends on CPU_XSCALE
  997. default y
  998. config CPU_HAS_PMU
  999. depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
  1000. (!ARCH_OMAP3 || OMAP3_EMU)
  1001. default y
  1002. bool
  1003. config MULTI_IRQ_HANDLER
  1004. bool
  1005. help
  1006. Allow each machine to specify it's own IRQ handler at run time.
  1007. if !MMU
  1008. source "arch/arm/Kconfig-nommu"
  1009. endif
  1010. config ARM_ERRATA_326103
  1011. bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
  1012. depends on CPU_V6
  1013. help
  1014. Executing a SWP instruction to read-only memory does not set bit 11
  1015. of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
  1016. treat the access as a read, preventing a COW from occurring and
  1017. causing the faulting task to livelock.
  1018. config ARM_ERRATA_411920
  1019. bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
  1020. depends on CPU_V6 || CPU_V6K
  1021. help
  1022. Invalidation of the Instruction Cache operation can
  1023. fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
  1024. It does not affect the MPCore. This option enables the ARM Ltd.
  1025. recommended workaround.
  1026. config ARM_ERRATA_430973
  1027. bool "ARM errata: Stale prediction on replaced interworking branch"
  1028. depends on CPU_V7
  1029. help
  1030. This option enables the workaround for the 430973 Cortex-A8
  1031. (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
  1032. interworking branch is replaced with another code sequence at the
  1033. same virtual address, whether due to self-modifying code or virtual
  1034. to physical address re-mapping, Cortex-A8 does not recover from the
  1035. stale interworking branch prediction. This results in Cortex-A8
  1036. executing the new code sequence in the incorrect ARM or Thumb state.
  1037. The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
  1038. and also flushes the branch target cache at every context switch.
  1039. Note that setting specific bits in the ACTLR register may not be
  1040. available in non-secure mode.
  1041. config ARM_ERRATA_458693
  1042. bool "ARM errata: Processor deadlock when a false hazard is created"
  1043. depends on CPU_V7
  1044. help
  1045. This option enables the workaround for the 458693 Cortex-A8 (r2p0)
  1046. erratum. For very specific sequences of memory operations, it is
  1047. possible for a hazard condition intended for a cache line to instead
  1048. be incorrectly associated with a different cache line. This false
  1049. hazard might then cause a processor deadlock. The workaround enables
  1050. the L1 caching of the NEON accesses and disables the PLD instruction
  1051. in the ACTLR register. Note that setting specific bits in the ACTLR
  1052. register may not be available in non-secure mode.
  1053. config ARM_ERRATA_460075
  1054. bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
  1055. depends on CPU_V7
  1056. help
  1057. This option enables the workaround for the 460075 Cortex-A8 (r2p0)
  1058. erratum. Any asynchronous access to the L2 cache may encounter a
  1059. situation in which recent store transactions to the L2 cache are lost
  1060. and overwritten with stale memory contents from external memory. The
  1061. workaround disables the write-allocate mode for the L2 cache via the
  1062. ACTLR register. Note that setting specific bits in the ACTLR register
  1063. may not be available in non-secure mode.
  1064. config ARM_ERRATA_742230
  1065. bool "ARM errata: DMB operation may be faulty"
  1066. depends on CPU_V7 && SMP
  1067. help
  1068. This option enables the workaround for the 742230 Cortex-A9
  1069. (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
  1070. between two write operations may not ensure the correct visibility
  1071. ordering of the two writes. This workaround sets a specific bit in
  1072. the diagnostic register of the Cortex-A9 which causes the DMB
  1073. instruction to behave as a DSB, ensuring the correct behaviour of
  1074. the two writes.
  1075. config ARM_ERRATA_742231
  1076. bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
  1077. depends on CPU_V7 && SMP
  1078. help
  1079. This option enables the workaround for the 742231 Cortex-A9
  1080. (r2p0..r2p2) erratum. Under certain conditions, specific to the
  1081. Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
  1082. accessing some data located in the same cache line, may get corrupted
  1083. data due to bad handling of the address hazard when the line gets
  1084. replaced from one of the CPUs at the same time as another CPU is
  1085. accessing it. This workaround sets specific bits in the diagnostic
  1086. register of the Cortex-A9 which reduces the linefill issuing
  1087. capabilities of the processor.
  1088. config PL310_ERRATA_588369
  1089. bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
  1090. depends on CACHE_L2X0
  1091. help
  1092. The PL310 L2 cache controller implements three types of Clean &
  1093. Invalidate maintenance operations: by Physical Address
  1094. (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
  1095. They are architecturally defined to behave as the execution of a
  1096. clean operation followed immediately by an invalidate operation,
  1097. both performing to the same memory location. This functionality
  1098. is not correctly implemented in PL310 as clean lines are not
  1099. invalidated as a result of these operations.
  1100. config ARM_ERRATA_720789
  1101. bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
  1102. depends on CPU_V7
  1103. help
  1104. This option enables the workaround for the 720789 Cortex-A9 (prior to
  1105. r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
  1106. broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
  1107. As a consequence of this erratum, some TLB entries which should be
  1108. invalidated are not, resulting in an incoherency in the system page
  1109. tables. The workaround changes the TLB flushing routines to invalidate
  1110. entries regardless of the ASID.
  1111. config PL310_ERRATA_727915
  1112. bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
  1113. depends on CACHE_L2X0
  1114. help
  1115. PL310 implements the Clean & Invalidate by Way L2 cache maintenance
  1116. operation (offset 0x7FC). This operation runs in background so that
  1117. PL310 can handle normal accesses while it is in progress. Under very
  1118. rare circumstances, due to this erratum, write data can be lost when
  1119. PL310 treats a cacheable write transaction during a Clean &
  1120. Invalidate by Way operation.
  1121. config ARM_ERRATA_743622
  1122. bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
  1123. depends on CPU_V7
  1124. help
  1125. This option enables the workaround for the 743622 Cortex-A9
  1126. (r2p*) erratum. Under very rare conditions, a faulty
  1127. optimisation in the Cortex-A9 Store Buffer may lead to data
  1128. corruption. This workaround sets a specific bit in the diagnostic
  1129. register of the Cortex-A9 which disables the Store Buffer
  1130. optimisation, preventing the defect from occurring. This has no
  1131. visible impact on the overall performance or power consumption of the
  1132. processor.
  1133. config ARM_ERRATA_751472
  1134. bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
  1135. depends on CPU_V7
  1136. help
  1137. This option enables the workaround for the 751472 Cortex-A9 (prior
  1138. to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
  1139. completion of a following broadcasted operation if the second
  1140. operation is received by a CPU before the ICIALLUIS has completed,
  1141. potentially leading to corrupted entries in the cache or TLB.
  1142. config PL310_ERRATA_753970
  1143. bool "PL310 errata: cache sync operation may be faulty"
  1144. depends on CACHE_PL310
  1145. help
  1146. This option enables the workaround for the 753970 PL310 (r3p0) erratum.
  1147. Under some condition the effect of cache sync operation on
  1148. the store buffer still remains when the operation completes.
  1149. This means that the store buffer is always asked to drain and
  1150. this prevents it from merging any further writes. The workaround
  1151. is to replace the normal offset of cache sync operation (0x730)
  1152. by another offset targeting an unmapped PL310 register 0x740.
  1153. This has the same effect as the cache sync operation: store buffer
  1154. drain and waiting for all buffers empty.
  1155. config ARM_ERRATA_754322
  1156. bool "ARM errata: possible faulty MMU translations following an ASID switch"
  1157. depends on CPU_V7
  1158. help
  1159. This option enables the workaround for the 754322 Cortex-A9 (r2p*,
  1160. r3p*) erratum. A speculative memory access may cause a page table walk
  1161. which starts prior to an ASID switch but completes afterwards. This
  1162. can populate the micro-TLB with a stale entry which may be hit with
  1163. the new ASID. This workaround places two dsb instructions in the mm
  1164. switching code so that no page table walks can cross the ASID switch.
  1165. config ARM_ERRATA_754327
  1166. bool "ARM errata: no automatic Store Buffer drain"
  1167. depends on CPU_V7 && SMP
  1168. help
  1169. This option enables the workaround for the 754327 Cortex-A9 (prior to
  1170. r2p0) erratum. The Store Buffer does not have any automatic draining
  1171. mechanism and therefore a livelock may occur if an external agent
  1172. continuously polls a memory location waiting to observe an update.
  1173. This workaround defines cpu_relax() as smp_mb(), preventing correctly
  1174. written polling loops from denying visibility of updates to memory.
  1175. config ARM_ERRATA_364296
  1176. bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
  1177. depends on CPU_V6 && !SMP
  1178. help
  1179. This options enables the workaround for the 364296 ARM1136
  1180. r0p2 erratum (possible cache data corruption with
  1181. hit-under-miss enabled). It sets the undocumented bit 31 in
  1182. the auxiliary control register and the FI bit in the control
  1183. register, thus disabling hit-under-miss without putting the
  1184. processor into full low interrupt latency mode. ARM11MPCore
  1185. is not affected.
  1186. config ARM_ERRATA_764369
  1187. bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
  1188. depends on CPU_V7 && SMP
  1189. help
  1190. This option enables the workaround for erratum 764369
  1191. affecting Cortex-A9 MPCore with two or more processors (all
  1192. current revisions). Under certain timing circumstances, a data
  1193. cache line maintenance operation by MVA targeting an Inner
  1194. Shareable memory region may fail to proceed up to either the
  1195. Point of Coherency or to the Point of Unification of the
  1196. system. This workaround adds a DSB instruction before the
  1197. relevant cache maintenance functions and sets a specific bit
  1198. in the diagnostic control register of the SCU.
  1199. config PL310_ERRATA_769419
  1200. bool "PL310 errata: no automatic Store Buffer drain"
  1201. depends on CACHE_L2X0
  1202. help
  1203. On revisions of the PL310 prior to r3p2, the Store Buffer does
  1204. not automatically drain. This can cause normal, non-cacheable
  1205. writes to be retained when the memory system is idle, leading
  1206. to suboptimal I/O performance for drivers using coherent DMA.
  1207. This option adds a write barrier to the cpu_idle loop so that,
  1208. on systems with an outer cache, the store buffer is drained
  1209. explicitly.
  1210. endmenu
  1211. source "arch/arm/common/Kconfig"
  1212. menu "Bus support"
  1213. config ARM_AMBA
  1214. bool
  1215. config ISA
  1216. bool
  1217. help
  1218. Find out whether you have ISA slots on your motherboard. ISA is the
  1219. name of a bus system, i.e. the way the CPU talks to the other stuff
  1220. inside your box. Other bus systems are PCI, EISA, MicroChannel
  1221. (MCA) or VESA. ISA is an older system, now being displaced by PCI;
  1222. newer boards don't support it. If you have ISA, say Y, otherwise N.
  1223. # Select ISA DMA controller support
  1224. config ISA_DMA
  1225. bool
  1226. select ISA_DMA_API
  1227. # Select ISA DMA interface
  1228. config ISA_DMA_API
  1229. bool
  1230. config PCI
  1231. bool "PCI support" if MIGHT_HAVE_PCI
  1232. help
  1233. Find out whether you have a PCI motherboard. PCI is the name of a
  1234. bus system, i.e. the way the CPU talks to the other stuff inside
  1235. your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
  1236. VESA. If you have PCI, say Y, otherwise N.
  1237. config PCI_DOMAINS
  1238. bool
  1239. depends on PCI
  1240. config PCI_NANOENGINE
  1241. bool "BSE nanoEngine PCI support"
  1242. depends on SA1100_NANOENGINE
  1243. help
  1244. Enable PCI on the BSE nanoEngine board.
  1245. config PCI_SYSCALL
  1246. def_bool PCI
  1247. # Select the host bridge type
  1248. config PCI_HOST_VIA82C505
  1249. bool
  1250. depends on PCI && ARCH_SHARK
  1251. default y
  1252. config PCI_HOST_ITE8152
  1253. bool
  1254. depends on PCI && MACH_ARMCORE
  1255. default y
  1256. select DMABOUNCE
  1257. source "drivers/pci/Kconfig"
  1258. source "drivers/pcmcia/Kconfig"
  1259. endmenu
  1260. menu "Kernel Features"
  1261. source "kernel/time/Kconfig"
  1262. config HAVE_SMP
  1263. bool
  1264. help
  1265. This option should be selected by machines which have an SMP-
  1266. capable CPU.
  1267. The only effect of this option is to make the SMP-related
  1268. options available to the user for configuration.
  1269. config SMP
  1270. bool "Symmetric Multi-Processing"
  1271. depends on CPU_V6K || CPU_V7
  1272. depends on GENERIC_CLOCKEVENTS
  1273. depends on HAVE_SMP
  1274. depends on MMU
  1275. select USE_GENERIC_SMP_HELPERS
  1276. select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
  1277. help
  1278. This enables support for systems with more than one CPU. If you have
  1279. a system with only one CPU, like most personal computers, say N. If
  1280. you have a system with more than one CPU, say Y.
  1281. If you say N here, the kernel will run on single and multiprocessor
  1282. machines, but will use only one CPU of a multiprocessor machine. If
  1283. you say Y here, the kernel will run on many, but not all, single
  1284. processor machines. On a single processor machine, the kernel will
  1285. run faster if you say N here.
  1286. See also <file:Documentation/x86/i386/IO-APIC.txt>,
  1287. <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
  1288. <http://tldp.org/HOWTO/SMP-HOWTO.html>.
  1289. If you don't know what to do here, say N.
  1290. config SMP_ON_UP
  1291. bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
  1292. depends on EXPERIMENTAL
  1293. depends on SMP && !XIP_KERNEL
  1294. default y
  1295. help
  1296. SMP kernels contain instructions which fail on non-SMP processors.
  1297. Enabling this option allows the kernel to modify itself to make
  1298. these instructions safe. Disabling it allows about 1K of space
  1299. savings.
  1300. If you don't know what to do here, say Y.
  1301. config ARM_CPU_TOPOLOGY
  1302. bool "Support cpu topology definition"
  1303. depends on SMP && CPU_V7
  1304. default y
  1305. help
  1306. Support ARM cpu topology definition. The MPIDR register defines
  1307. affinity between processors which is then used to describe the cpu
  1308. topology of an ARM System.
  1309. config SCHED_MC
  1310. bool "Multi-core scheduler support"
  1311. depends on ARM_CPU_TOPOLOGY
  1312. help
  1313. Multi-core scheduler support improves the CPU scheduler's decision
  1314. making when dealing with multi-core CPU chips at a cost of slightly
  1315. increased overhead in some places. If unsure say N here.
  1316. config SCHED_SMT
  1317. bool "SMT scheduler support"
  1318. depends on ARM_CPU_TOPOLOGY
  1319. help
  1320. Improves the CPU scheduler's decision making when dealing with
  1321. MultiThreading at a cost of slightly increased overhead in some
  1322. places. If unsure say N here.
  1323. config HAVE_ARM_SCU
  1324. bool
  1325. help
  1326. This option enables support for the ARM system coherency unit
  1327. config ARM_ARCH_TIMER
  1328. bool "Architected timer support"
  1329. depends on CPU_V7
  1330. help
  1331. This option enables support for the ARM architected timer
  1332. config HAVE_ARM_TWD
  1333. bool
  1334. depends on SMP
  1335. help
  1336. This options enables support for the ARM timer and watchdog unit
  1337. choice
  1338. prompt "Memory split"
  1339. default VMSPLIT_3G
  1340. help
  1341. Select the desired split between kernel and user memory.
  1342. If you are not absolutely sure what you are doing, leave this
  1343. option alone!
  1344. config VMSPLIT_3G
  1345. bool "3G/1G user/kernel split"
  1346. config VMSPLIT_2G
  1347. bool "2G/2G user/kernel split"
  1348. config VMSPLIT_1G
  1349. bool "1G/3G user/kernel split"
  1350. endchoice
  1351. config PAGE_OFFSET
  1352. hex
  1353. default 0x40000000 if VMSPLIT_1G
  1354. default 0x80000000 if VMSPLIT_2G
  1355. default 0xC0000000
  1356. config NR_CPUS
  1357. int "Maximum number of CPUs (2-32)"
  1358. range 2 32
  1359. depends on SMP
  1360. default "4"
  1361. config HOTPLUG_CPU
  1362. bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
  1363. depends on SMP && HOTPLUG && EXPERIMENTAL
  1364. help
  1365. Say Y here to experiment with turning CPUs off and on. CPUs
  1366. can be controlled through /sys/devices/system/cpu.
  1367. config LOCAL_TIMERS
  1368. bool "Use local timer interrupts"
  1369. depends on SMP
  1370. default y
  1371. select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
  1372. help
  1373. Enable support for local timers on SMP platforms, rather then the
  1374. legacy IPI broadcast method. Local timers allows the system
  1375. accounting to be spread across the timer interval, preventing a
  1376. "thundering herd" at every timer tick.
  1377. config ARCH_NR_GPIO
  1378. int
  1379. default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
  1380. default 355 if ARCH_U8500
  1381. default 264 if MACH_H4700
  1382. default 0
  1383. help
  1384. Maximum number of GPIOs in the system.
  1385. If unsure, leave the default value.
  1386. source kernel/Kconfig.preempt
  1387. config HZ
  1388. int
  1389. default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
  1390. ARCH_S5PV210 || ARCH_EXYNOS4
  1391. default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
  1392. default AT91_TIMER_HZ if ARCH_AT91
  1393. default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
  1394. default 100
  1395. config THUMB2_KERNEL
  1396. bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
  1397. depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
  1398. select AEABI
  1399. select ARM_ASM_UNIFIED
  1400. select ARM_UNWIND
  1401. help
  1402. By enabling this option, the kernel will be compiled in
  1403. Thumb-2 mode. A compiler/assembler that understand the unified
  1404. ARM-Thumb syntax is needed.
  1405. If unsure, say N.
  1406. config THUMB2_AVOID_R_ARM_THM_JUMP11
  1407. bool "Work around buggy Thumb-2 short branch relocations in gas"
  1408. depends on THUMB2_KERNEL && MODULES
  1409. default y
  1410. help
  1411. Various binutils versions can resolve Thumb-2 branches to
  1412. locally-defined, preemptible global symbols as short-range "b.n"
  1413. branch instructions.
  1414. This is a problem, because there's no guarantee the final
  1415. destination of the symbol, or any candidate locations for a
  1416. trampoline, are within range of the branch. For this reason, the
  1417. kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
  1418. relocation in modules at all, and it makes little sense to add
  1419. support.
  1420. The symptom is that the kernel fails with an "unsupported
  1421. relocation" error when loading some modules.
  1422. Until fixed tools are available, passing
  1423. -fno-optimize-sibling-calls to gcc should prevent gcc generating
  1424. code which hits this problem, at the cost of a bit of extra runtime
  1425. stack usage in some cases.
  1426. The problem is described in more detail at:
  1427. https://bugs.launchpad.net/binutils-linaro/+bug/725126
  1428. Only Thumb-2 kernels are affected.
  1429. Unless you are sure your tools don't have this problem, say Y.
  1430. config ARM_ASM_UNIFIED
  1431. bool
  1432. config AEABI
  1433. bool "Use the ARM EABI to compile the kernel"
  1434. help
  1435. This option allows for the kernel to be compiled using the latest
  1436. ARM ABI (aka EABI). This is only useful if you are using a user
  1437. space environment that is also compiled with EABI.
  1438. Since there are major incompatibilities between the legacy ABI and
  1439. EABI, especially with regard to structure member alignment, this
  1440. option also changes the kernel syscall calling convention to
  1441. disambiguate both ABIs and allow for backward compatibility support
  1442. (selected with CONFIG_OABI_COMPAT).
  1443. To use this you need GCC version 4.0.0 or later.
  1444. config OABI_COMPAT
  1445. bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
  1446. depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
  1447. default y
  1448. help
  1449. This option preserves the old syscall interface along with the
  1450. new (ARM EABI) one. It also provides a compatibility layer to
  1451. intercept syscalls that have structure arguments which layout
  1452. in memory differs between the legacy ABI and the new ARM EABI
  1453. (only for non "thumb" binaries). This option adds a tiny
  1454. overhead to all syscalls and produces a slightly larger kernel.
  1455. If you know you'll be using only pure EABI user space then you
  1456. can say N here. If this option is not selected and you attempt
  1457. to execute a legacy ABI binary then the result will be
  1458. UNPREDICTABLE (in fact it can be predicted that it won't work
  1459. at all). If in doubt say Y.
  1460. config ARCH_HAS_HOLES_MEMORYMODEL
  1461. bool
  1462. config ARCH_SPARSEMEM_ENABLE
  1463. bool
  1464. config ARCH_SPARSEMEM_DEFAULT
  1465. def_bool ARCH_SPARSEMEM_ENABLE
  1466. config ARCH_SELECT_MEMORY_MODEL
  1467. def_bool ARCH_SPARSEMEM_ENABLE
  1468. config HAVE_ARCH_PFN_VALID
  1469. def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
  1470. config HIGHMEM
  1471. bool "High Memory Support"
  1472. depends on MMU
  1473. help
  1474. The address space of ARM processors is only 4 Gigabytes large
  1475. and it has to accommodate user address space, kernel address
  1476. space as well as some memory mapped IO. That means that, if you
  1477. have a large amount of physical memory and/or IO, not all of the
  1478. memory can be "permanently mapped" by the kernel. The physical
  1479. memory that is not permanently mapped is called "high memory".
  1480. Depending on the selected kernel/user memory split, minimum
  1481. vmalloc space and actual amount of RAM, you may not need this
  1482. option which should result in a slightly faster kernel.
  1483. If unsure, say n.
  1484. config HIGHPTE
  1485. bool "Allocate 2nd-level pagetables from highmem"
  1486. depends on HIGHMEM
  1487. config HW_PERF_EVENTS
  1488. bool "Enable hardware performance counter support for perf events"
  1489. depends on PERF_EVENTS && CPU_HAS_PMU
  1490. default y
  1491. help
  1492. Enable hardware performance counter support for perf events. If
  1493. disabled, perf events will use software events only.
  1494. source "mm/Kconfig"
  1495. config FORCE_MAX_ZONEORDER
  1496. int "Maximum zone order" if ARCH_SHMOBILE
  1497. range 11 64 if ARCH_SHMOBILE
  1498. default "9" if SA1111
  1499. default "11"
  1500. help
  1501. The kernel memory allocator divides physically contiguous memory
  1502. blocks into "zones", where each zone is a power of two number of
  1503. pages. This option selects the largest power of two that the kernel
  1504. keeps in the memory allocator. If you need to allocate very large
  1505. blocks of physically contiguous memory, then you may need to
  1506. increase this value.
  1507. This config option is actually maximum order plus one. For example,
  1508. a value of 11 means that the largest free memory block is 2^10 pages.
  1509. config LEDS
  1510. bool "Timer and CPU usage LEDs"
  1511. depends on ARCH_CDB89712 || ARCH_EBSA110 || \
  1512. ARCH_EBSA285 || ARCH_INTEGRATOR || \
  1513. ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
  1514. ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
  1515. ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
  1516. ARCH_AT91 || ARCH_DAVINCI || \
  1517. ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
  1518. help
  1519. If you say Y here, the LEDs on your machine will be used
  1520. to provide useful information about your current system status.
  1521. If you are compiling a kernel for a NetWinder or EBSA-285, you will
  1522. be able to select which LEDs are active using the options below. If
  1523. you are compiling a kernel for the EBSA-110 or the LART however, the
  1524. red LED will simply flash regularly to indicate that the system is
  1525. still functional. It is safe to say Y here if you have a CATS
  1526. system, but the driver will do nothing.
  1527. config LEDS_TIMER
  1528. bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
  1529. OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
  1530. || MACH_OMAP_PERSEUS2
  1531. depends on LEDS
  1532. depends on !GENERIC_CLOCKEVENTS
  1533. default y if ARCH_EBSA110
  1534. help
  1535. If you say Y here, one of the system LEDs (the green one on the
  1536. NetWinder, the amber one on the EBSA285, or the red one on the LART)
  1537. will flash regularly to indicate that the system is still
  1538. operational. This is mainly useful to kernel hackers who are
  1539. debugging unstable kernels.
  1540. The LART uses the same LED for both Timer LED and CPU usage LED
  1541. functions. You may choose to use both, but the Timer LED function
  1542. will overrule the CPU usage LED.
  1543. config LEDS_CPU
  1544. bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
  1545. !ARCH_OMAP) \
  1546. || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
  1547. || MACH_OMAP_PERSEUS2
  1548. depends on LEDS
  1549. help
  1550. If you say Y here, the red LED will be used to give a good real
  1551. time indication of CPU usage, by lighting whenever the idle task
  1552. is not currently executing.
  1553. The LART uses the same LED for both Timer LED and CPU usage LED
  1554. functions. You may choose to use both, but the Timer LED function
  1555. will overrule the CPU usage LED.
  1556. config ALIGNMENT_TRAP
  1557. bool
  1558. depends on CPU_CP15_MMU
  1559. default y if !ARCH_EBSA110
  1560. select HAVE_PROC_CPU if PROC_FS
  1561. help
  1562. ARM processors cannot fetch/store information which is not
  1563. naturally aligned on the bus, i.e., a 4 byte fetch must start at an
  1564. address divisible by 4. On 32-bit ARM processors, these non-aligned
  1565. fetch/store instructions will be emulated in software if you say
  1566. here, which has a severe performance impact. This is necessary for
  1567. correct operation of some network protocols. With an IP-only
  1568. configuration it is safe to say N, otherwise say Y.
  1569. config UACCESS_WITH_MEMCPY
  1570. bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
  1571. depends on MMU && EXPERIMENTAL
  1572. default y if CPU_FEROCEON
  1573. help
  1574. Implement faster copy_to_user and clear_user methods for CPU
  1575. cores where a 8-word STM instruction give significantly higher
  1576. memory write throughput than a sequence of individual 32bit stores.
  1577. A possible side effect is a slight increase in scheduling latency
  1578. between threads sharing the same address space if they invoke
  1579. such copy operations with large buffers.
  1580. However, if the CPU data cache is using a write-allocate mode,
  1581. this option is unlikely to provide any performance gain.
  1582. config SECCOMP
  1583. bool
  1584. prompt "Enable seccomp to safely compute untrusted bytecode"
  1585. ---help---
  1586. This kernel feature is useful for number crunching applications
  1587. that may need to compute untrusted bytecode during their
  1588. execution. By using pipes or other transports made available to
  1589. the process as file descriptors supporting the read/write
  1590. syscalls, it's possible to isolate those applications in
  1591. their own address space using seccomp. Once seccomp is
  1592. enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
  1593. and the task is only allowed to execute a few safe syscalls
  1594. defined by each seccomp mode.
  1595. config CC_STACKPROTECTOR
  1596. bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
  1597. depends on EXPERIMENTAL
  1598. help
  1599. This option turns on the -fstack-protector GCC feature. This
  1600. feature puts, at the beginning of functions, a canary value on
  1601. the stack just before the return address, and validates
  1602. the value just before actually returning. Stack based buffer
  1603. overflows (that need to overwrite this return address) now also
  1604. overwrite the canary, which gets detected and the attack is then
  1605. neutralized via a kernel panic.
  1606. This feature requires gcc version 4.2 or above.
  1607. config DEPRECATED_PARAM_STRUCT
  1608. bool "Provide old way to pass kernel parameters"
  1609. help
  1610. This was deprecated in 2001 and announced to live on for 5 years.
  1611. Some old boot loaders still use this way.
  1612. endmenu
  1613. menu "Boot options"
  1614. config USE_OF
  1615. bool "Flattened Device Tree support"
  1616. select OF
  1617. select OF_EARLY_FLATTREE
  1618. select IRQ_DOMAIN
  1619. help
  1620. Include support for flattened device tree machine descriptions.
  1621. # Compressed boot loader in ROM. Yes, we really want to ask about
  1622. # TEXT and BSS so we preserve their values in the config files.
  1623. config ZBOOT_ROM_TEXT
  1624. hex "Compressed ROM boot loader base address"
  1625. default "0"
  1626. help
  1627. The physical address at which the ROM-able zImage is to be
  1628. placed in the target. Platforms which normally make use of
  1629. ROM-able zImage formats normally set this to a suitable
  1630. value in their defconfig file.
  1631. If ZBOOT_ROM is not enabled, this has no effect.
  1632. config ZBOOT_ROM_BSS
  1633. hex "Compressed ROM boot loader BSS address"
  1634. default "0"
  1635. help
  1636. The base address of an area of read/write memory in the target
  1637. for the ROM-able zImage which must be available while the
  1638. decompressor is running. It must be large enough to hold the
  1639. entire decompressed kernel plus an additional 128 KiB.
  1640. Platforms which normally make use of ROM-able zImage formats
  1641. normally set this to a suitable value in their defconfig file.
  1642. If ZBOOT_ROM is not enabled, this has no effect.
  1643. config ZBOOT_ROM
  1644. bool "Compressed boot loader in ROM/flash"
  1645. depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
  1646. help
  1647. Say Y here if you intend to execute your compressed kernel image
  1648. (zImage) directly from ROM or flash. If unsure, say N.
  1649. choice
  1650. prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
  1651. depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
  1652. default ZBOOT_ROM_NONE
  1653. help
  1654. Include experimental SD/MMC loading code in the ROM-able zImage.
  1655. With this enabled it is possible to write the the ROM-able zImage
  1656. kernel image to an MMC or SD card and boot the kernel straight
  1657. from the reset vector. At reset the processor Mask ROM will load
  1658. the first part of the the ROM-able zImage which in turn loads the
  1659. rest the kernel image to RAM.
  1660. config ZBOOT_ROM_NONE
  1661. bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
  1662. help
  1663. Do not load image from SD or MMC
  1664. config ZBOOT_ROM_MMCIF
  1665. bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
  1666. help
  1667. Load image from MMCIF hardware block.
  1668. config ZBOOT_ROM_SH_MOBILE_SDHI
  1669. bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
  1670. help
  1671. Load image from SDHI hardware block
  1672. endchoice
  1673. config ARM_APPENDED_DTB
  1674. bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
  1675. depends on OF && !ZBOOT_ROM && EXPERIMENTAL
  1676. help
  1677. With this option, the boot code will look for a device tree binary
  1678. (DTB) appended to zImage
  1679. (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
  1680. This is meant as a backward compatibility convenience for those
  1681. systems with a bootloader that can't be upgraded to accommodate
  1682. the documented boot protocol using a device tree.
  1683. Beware that there is very little in terms of protection against
  1684. this option being confused by leftover garbage in memory that might
  1685. look like a DTB header after a reboot if no actual DTB is appended
  1686. to zImage. Do not leave this option active in a production kernel
  1687. if you don't intend to always append a DTB. Proper passing of the
  1688. location into r2 of a bootloader provided DTB is always preferable
  1689. to this option.
  1690. config ARM_ATAG_DTB_COMPAT
  1691. bool "Supplement the appended DTB with traditional ATAG information"
  1692. depends on ARM_APPENDED_DTB
  1693. help
  1694. Some old bootloaders can't be updated to a DTB capable one, yet
  1695. they provide ATAGs with memory configuration, the ramdisk address,
  1696. the kernel cmdline string, etc. Such information is dynamically
  1697. provided by the bootloader and can't always be stored in a static
  1698. DTB. To allow a device tree enabled kernel to be used with such
  1699. bootloaders, this option allows zImage to extract the information
  1700. from the ATAG list and store it at run time into the appended DTB.
  1701. config CMDLINE
  1702. string "Default kernel command string"
  1703. default ""
  1704. help
  1705. On some architectures (EBSA110 and CATS), there is currently no way
  1706. for the boot loader to pass arguments to the kernel. For these
  1707. architectures, you should supply some command-line options at build
  1708. time by entering them here. As a minimum, you should specify the
  1709. memory size and the root device (e.g., mem=64M root=/dev/nfs).
  1710. choice
  1711. prompt "Kernel command line type" if CMDLINE != ""
  1712. default CMDLINE_FROM_BOOTLOADER
  1713. config CMDLINE_FROM_BOOTLOADER
  1714. bool "Use bootloader kernel arguments if available"
  1715. help
  1716. Uses the command-line options passed by the boot loader. If
  1717. the boot loader doesn't provide any, the default kernel command
  1718. string provided in CMDLINE will be used.
  1719. config CMDLINE_EXTEND
  1720. bool "Extend bootloader kernel arguments"
  1721. help
  1722. The command-line arguments provided by the boot loader will be
  1723. appended to the default kernel command string.
  1724. config CMDLINE_FORCE
  1725. bool "Always use the default kernel command string"
  1726. help
  1727. Always use the default kernel command string, even if the boot
  1728. loader passes other arguments to the kernel.
  1729. This is useful if you cannot or don't want to change the
  1730. command-line options your boot loader passes to the kernel.
  1731. endchoice
  1732. config XIP_KERNEL
  1733. bool "Kernel Execute-In-Place from ROM"
  1734. depends on !ZBOOT_ROM && !ARM_LPAE
  1735. help
  1736. Execute-In-Place allows the kernel to run from non-volatile storage
  1737. directly addressable by the CPU, such as NOR flash. This saves RAM
  1738. space since the text section of the kernel is not loaded from flash
  1739. to RAM. Read-write sections, such as the data section and stack,
  1740. are still copied to RAM. The XIP kernel is not compressed since
  1741. it has to run directly from flash, so it will take more space to
  1742. store it. The flash address used to link the kernel object files,
  1743. and for storing it, is configuration dependent. Therefore, if you
  1744. say Y here, you must know the proper physical address where to
  1745. store the kernel image depending on your own flash memory usage.
  1746. Also note that the make target becomes "make xipImage" rather than
  1747. "make zImage" or "make Image". The final kernel binary to put in
  1748. ROM memory will be arch/arm/boot/xipImage.
  1749. If unsure, say N.
  1750. config XIP_PHYS_ADDR
  1751. hex "XIP Kernel Physical Location"
  1752. depends on XIP_KERNEL
  1753. default "0x00080000"
  1754. help
  1755. This is the physical address in your flash memory the kernel will
  1756. be linked for and stored to. This address is dependent on your
  1757. own flash usage.
  1758. config KEXEC
  1759. bool "Kexec system call (EXPERIMENTAL)"
  1760. depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
  1761. help
  1762. kexec is a system call that implements the ability to shutdown your
  1763. current kernel, and to start another kernel. It is like a reboot
  1764. but it is independent of the system firmware. And like a reboot
  1765. you can start any kernel with it, not just Linux.
  1766. It is an ongoing process to be certain the hardware in a machine
  1767. is properly shutdown, so do not be surprised if this code does not
  1768. initially work for you. It may help to enable device hotplugging
  1769. support.
  1770. config ATAGS_PROC
  1771. bool "Export atags in procfs"
  1772. depends on KEXEC
  1773. default y
  1774. help
  1775. Should the atags used to boot the kernel be exported in an "atags"
  1776. file in procfs. Useful with kexec.
  1777. config CRASH_DUMP
  1778. bool "Build kdump crash kernel (EXPERIMENTAL)"
  1779. depends on EXPERIMENTAL
  1780. help
  1781. Generate crash dump after being started by kexec. This should
  1782. be normally only set in special crash dump kernels which are
  1783. loaded in the main kernel with kexec-tools into a specially
  1784. reserved region and then later executed after a crash by
  1785. kdump/kexec. The crash dump kernel must be compiled to a
  1786. memory address not used by the main kernel
  1787. For more details see Documentation/kdump/kdump.txt
  1788. config AUTO_ZRELADDR
  1789. bool "Auto calculation of the decompressed kernel image address"
  1790. depends on !ZBOOT_ROM && !ARCH_U300
  1791. help
  1792. ZRELADDR is the physical address where the decompressed kernel
  1793. image will be placed. If AUTO_ZRELADDR is selected, the address
  1794. will be determined at run-time by masking the current IP with
  1795. 0xf8000000. This assumes the zImage being placed in the first 128MB
  1796. from start of memory.
  1797. endmenu
  1798. menu "CPU Power Management"
  1799. if ARCH_HAS_CPUFREQ
  1800. source "drivers/cpufreq/Kconfig"
  1801. config CPU_FREQ_IMX
  1802. tristate "CPUfreq driver for i.MX CPUs"
  1803. depends on ARCH_MXC && CPU_FREQ
  1804. help
  1805. This enables the CPUfreq driver for i.MX CPUs.
  1806. config CPU_FREQ_SA1100
  1807. bool
  1808. config CPU_FREQ_SA1110
  1809. bool
  1810. config CPU_FREQ_INTEGRATOR
  1811. tristate "CPUfreq driver for ARM Integrator CPUs"
  1812. depends on ARCH_INTEGRATOR && CPU_FREQ
  1813. default y
  1814. help
  1815. This enables the CPUfreq driver for ARM Integrator CPUs.
  1816. For details, take a look at <file:Documentation/cpu-freq>.
  1817. If in doubt, say Y.
  1818. config CPU_FREQ_PXA
  1819. bool
  1820. depends on CPU_FREQ && ARCH_PXA && PXA25x
  1821. default y
  1822. select CPU_FREQ_TABLE
  1823. select CPU_FREQ_DEFAULT_GOV_USERSPACE
  1824. config CPU_FREQ_S3C
  1825. bool
  1826. help
  1827. Internal configuration node for common cpufreq on Samsung SoC
  1828. config CPU_FREQ_S3C24XX
  1829. bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
  1830. depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
  1831. select CPU_FREQ_S3C
  1832. help
  1833. This enables the CPUfreq driver for the Samsung S3C24XX family
  1834. of CPUs.
  1835. For details, take a look at <file:Documentation/cpu-freq>.
  1836. If in doubt, say N.
  1837. config CPU_FREQ_S3C24XX_PLL
  1838. bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
  1839. depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
  1840. help
  1841. Compile in support for changing the PLL frequency from the
  1842. S3C24XX series CPUfreq driver. The PLL takes time to settle
  1843. after a frequency change, so by default it is not enabled.
  1844. This also means that the PLL tables for the selected CPU(s) will
  1845. be built which may increase the size of the kernel image.
  1846. config CPU_FREQ_S3C24XX_DEBUG
  1847. bool "Debug CPUfreq Samsung driver core"
  1848. depends on CPU_FREQ_S3C24XX
  1849. help
  1850. Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
  1851. config CPU_FREQ_S3C24XX_IODEBUG
  1852. bool "Debug CPUfreq Samsung driver IO timing"
  1853. depends on CPU_FREQ_S3C24XX
  1854. help
  1855. Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
  1856. config CPU_FREQ_S3C24XX_DEBUGFS
  1857. bool "Export debugfs for CPUFreq"
  1858. depends on CPU_FREQ_S3C24XX && DEBUG_FS
  1859. help
  1860. Export status information via debugfs.
  1861. endif
  1862. source "drivers/cpuidle/Kconfig"
  1863. endmenu
  1864. menu "Floating point emulation"
  1865. comment "At least one emulation must be selected"
  1866. config FPE_NWFPE
  1867. bool "NWFPE math emulation"
  1868. depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
  1869. ---help---
  1870. Say Y to include the NWFPE floating point emulator in the kernel.
  1871. This is necessary to run most binaries. Linux does not currently
  1872. support floating point hardware so you need to say Y here even if
  1873. your machine has an FPA or floating point co-processor podule.
  1874. You may say N here if you are going to load the Acorn FPEmulator
  1875. early in the bootup.
  1876. config FPE_NWFPE_XP
  1877. bool "Support extended precision"
  1878. depends on FPE_NWFPE
  1879. help
  1880. Say Y to include 80-bit support in the kernel floating-point
  1881. emulator. Otherwise, only 32 and 64-bit support is compiled in.
  1882. Note that gcc does not generate 80-bit operations by default,
  1883. so in most cases this option only enlarges the size of the
  1884. floating point emulator without any good reason.
  1885. You almost surely want to say N here.
  1886. config FPE_FASTFPE
  1887. bool "FastFPE math emulation (EXPERIMENTAL)"
  1888. depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
  1889. ---help---
  1890. Say Y here to include the FAST floating point emulator in the kernel.
  1891. This is an experimental much faster emulator which now also has full
  1892. precision for the mantissa. It does not support any exceptions.
  1893. It is very simple, and approximately 3-6 times faster than NWFPE.
  1894. It should be sufficient for most programs. It may be not suitable
  1895. for scientific calculations, but you have to check this for yourself.
  1896. If you do not feel you need a faster FP emulation you should better
  1897. choose NWFPE.
  1898. config VFP
  1899. bool "VFP-format floating point maths"
  1900. depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
  1901. help
  1902. Say Y to include VFP support code in the kernel. This is needed
  1903. if your hardware includes a VFP unit.
  1904. Please see <file:Documentation/arm/VFP/release-notes.txt> for
  1905. release notes and additional status information.
  1906. Say N if your target does not have VFP hardware.
  1907. config VFPv3
  1908. bool
  1909. depends on VFP
  1910. default y if CPU_V7
  1911. config NEON
  1912. bool "Advanced SIMD (NEON) Extension support"
  1913. depends on VFPv3 && CPU_V7
  1914. help
  1915. Say Y to include support code for NEON, the ARMv7 Advanced SIMD
  1916. Extension.
  1917. endmenu
  1918. menu "Userspace binary formats"
  1919. source "fs/Kconfig.binfmt"
  1920. config ARTHUR
  1921. tristate "RISC OS personality"
  1922. depends on !AEABI
  1923. help
  1924. Say Y here to include the kernel code necessary if you want to run
  1925. Acorn RISC OS/Arthur binaries under Linux. This code is still very
  1926. experimental; if this sounds frightening, say N and sleep in peace.
  1927. You can also say M here to compile this support as a module (which
  1928. will be called arthur).
  1929. endmenu
  1930. menu "Power management options"
  1931. source "kernel/power/Kconfig"
  1932. config ARCH_SUSPEND_POSSIBLE
  1933. depends on !ARCH_S5PC100
  1934. depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
  1935. CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
  1936. def_bool y
  1937. config ARM_CPU_SUSPEND
  1938. def_bool PM_SLEEP
  1939. endmenu
  1940. source "net/Kconfig"
  1941. source "drivers/Kconfig"
  1942. source "fs/Kconfig"
  1943. source "arch/arm/Kconfig.debug"
  1944. source "security/Kconfig"
  1945. source "crypto/Kconfig"
  1946. source "lib/Kconfig"