ohci-hcd.c 26 KB

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  1. /*
  2. * OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * [ Initialisation is based on Linus' ]
  8. * [ uhci code and gregs ohci fragments ]
  9. * [ (C) Copyright 1999 Linus Torvalds ]
  10. * [ (C) Copyright 1999 Gregory P. Smith]
  11. *
  12. *
  13. * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  14. * interfaces (though some non-x86 Intel chips use it). It supports
  15. * smarter hardware than UHCI. A download link for the spec available
  16. * through the http://www.usb.org website.
  17. *
  18. * History:
  19. *
  20. * 2004/03/24 LH7A404 support (Durgesh Pattamatta & Marc Singer)
  21. * 2004/02/04 use generic dma_* functions instead of pci_* (dsaxena@plexity.net)
  22. * 2003/02/24 show registers in sysfs (Kevin Brosius)
  23. *
  24. * 2002/09/03 get rid of ed hashtables, rework periodic scheduling and
  25. * bandwidth accounting; if debugging, show schedules in driverfs
  26. * 2002/07/19 fixes to management of ED and schedule state.
  27. * 2002/06/09 SA-1111 support (Christopher Hoover)
  28. * 2002/06/01 remember frame when HC won't see EDs any more; use that info
  29. * to fix urb unlink races caused by interrupt latency assumptions;
  30. * minor ED field and function naming updates
  31. * 2002/01/18 package as a patch for 2.5.3; this should match the
  32. * 2.4.17 kernel modulo some bugs being fixed.
  33. *
  34. * 2001/10/18 merge pmac cleanup (Benjamin Herrenschmidt) and bugfixes
  35. * from post-2.4.5 patches.
  36. * 2001/09/20 URB_ZERO_PACKET support; hcca_dma portability, OPTi warning
  37. * 2001/09/07 match PCI PM changes, errnos from Linus' tree
  38. * 2001/05/05 fork 2.4.5 version into "hcd" framework, cleanup, simplify;
  39. * pbook pci quirks gone (please fix pbook pci sw!) (db)
  40. *
  41. * 2001/04/08 Identify version on module load (gb)
  42. * 2001/03/24 td/ed hashing to remove bus_to_virt (Steve Longerbeam);
  43. pci_map_single (db)
  44. * 2001/03/21 td and dev/ed allocation uses new pci_pool API (db)
  45. * 2001/03/07 hcca allocation uses pci_alloc_consistent (Steve Longerbeam)
  46. *
  47. * 2000/09/26 fixed races in removing the private portion of the urb
  48. * 2000/09/07 disable bulk and control lists when unlinking the last
  49. * endpoint descriptor in order to avoid unrecoverable errors on
  50. * the Lucent chips. (rwc@sgi)
  51. * 2000/08/29 use bandwidth claiming hooks (thanks Randy!), fix some
  52. * urb unlink probs, indentation fixes
  53. * 2000/08/11 various oops fixes mostly affecting iso and cleanup from
  54. * device unplugs.
  55. * 2000/06/28 use PCI hotplug framework, for better power management
  56. * and for Cardbus support (David Brownell)
  57. * 2000/earlier: fixes for NEC/Lucent chips; suspend/resume handling
  58. * when the controller loses power; handle UE; cleanup; ...
  59. *
  60. * v5.2 1999/12/07 URB 3rd preview,
  61. * v5.1 1999/11/30 URB 2nd preview, cpia, (usb-scsi)
  62. * v5.0 1999/11/22 URB Technical preview, Paul Mackerras powerbook susp/resume
  63. * i386: HUB, Keyboard, Mouse, Printer
  64. *
  65. * v4.3 1999/10/27 multiple HCs, bulk_request
  66. * v4.2 1999/09/05 ISO API alpha, new dev alloc, neg Error-codes
  67. * v4.1 1999/08/27 Randy Dunlap's - ISO API first impl.
  68. * v4.0 1999/08/18
  69. * v3.0 1999/06/25
  70. * v2.1 1999/05/09 code clean up
  71. * v2.0 1999/05/04
  72. * v1.0 1999/04/27 initial release
  73. *
  74. * This file is licenced under the GPL.
  75. */
  76. #include <linux/config.h>
  77. #ifdef CONFIG_USB_DEBUG
  78. # define DEBUG
  79. #else
  80. # undef DEBUG
  81. #endif
  82. #include <linux/module.h>
  83. #include <linux/moduleparam.h>
  84. #include <linux/pci.h>
  85. #include <linux/kernel.h>
  86. #include <linux/delay.h>
  87. #include <linux/ioport.h>
  88. #include <linux/sched.h>
  89. #include <linux/slab.h>
  90. #include <linux/smp_lock.h>
  91. #include <linux/errno.h>
  92. #include <linux/init.h>
  93. #include <linux/timer.h>
  94. #include <linux/list.h>
  95. #include <linux/interrupt.h> /* for in_interrupt () */
  96. #include <linux/usb.h>
  97. #include <linux/usb_otg.h>
  98. #include "../core/hcd.h"
  99. #include <linux/dma-mapping.h>
  100. #include <linux/dmapool.h> /* needed by ohci-mem.c when no PCI */
  101. #include <asm/io.h>
  102. #include <asm/irq.h>
  103. #include <asm/system.h>
  104. #include <asm/unaligned.h>
  105. #include <asm/byteorder.h>
  106. #define DRIVER_VERSION "2004 Nov 08"
  107. #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  108. #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  109. /*-------------------------------------------------------------------------*/
  110. // #define OHCI_VERBOSE_DEBUG /* not always helpful */
  111. /* For initializing controller (mask in an HCFS mode too) */
  112. #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
  113. #define OHCI_INTR_INIT \
  114. (OHCI_INTR_MIE | OHCI_INTR_UE | OHCI_INTR_RD | OHCI_INTR_WDH)
  115. #ifdef __hppa__
  116. /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  117. #define IR_DISABLE
  118. #endif
  119. #ifdef CONFIG_ARCH_OMAP
  120. /* OMAP doesn't support IR (no SMM; not needed) */
  121. #define IR_DISABLE
  122. #endif
  123. /*-------------------------------------------------------------------------*/
  124. static const char hcd_name [] = "ohci_hcd";
  125. #include "ohci.h"
  126. static void ohci_dump (struct ohci_hcd *ohci, int verbose);
  127. static int ohci_init (struct ohci_hcd *ohci);
  128. static void ohci_stop (struct usb_hcd *hcd);
  129. #include "ohci-hub.c"
  130. #include "ohci-dbg.c"
  131. #include "ohci-mem.c"
  132. #include "ohci-q.c"
  133. /*
  134. * On architectures with edge-triggered interrupts we must never return
  135. * IRQ_NONE.
  136. */
  137. #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
  138. #define IRQ_NOTMINE IRQ_HANDLED
  139. #else
  140. #define IRQ_NOTMINE IRQ_NONE
  141. #endif
  142. /* Some boards misreport power switching/overcurrent */
  143. static int distrust_firmware = 1;
  144. module_param (distrust_firmware, bool, 0);
  145. MODULE_PARM_DESC (distrust_firmware,
  146. "true to distrust firmware power/overcurrent setup");
  147. /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
  148. static int no_handshake = 0;
  149. module_param (no_handshake, bool, 0);
  150. MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
  151. /*-------------------------------------------------------------------------*/
  152. /*
  153. * queue up an urb for anything except the root hub
  154. */
  155. static int ohci_urb_enqueue (
  156. struct usb_hcd *hcd,
  157. struct usb_host_endpoint *ep,
  158. struct urb *urb,
  159. int mem_flags
  160. ) {
  161. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  162. struct ed *ed;
  163. urb_priv_t *urb_priv;
  164. unsigned int pipe = urb->pipe;
  165. int i, size = 0;
  166. unsigned long flags;
  167. int retval = 0;
  168. #ifdef OHCI_VERBOSE_DEBUG
  169. urb_print (urb, "SUB", usb_pipein (pipe));
  170. #endif
  171. /* every endpoint has a ed, locate and maybe (re)initialize it */
  172. if (! (ed = ed_get (ohci, ep, urb->dev, pipe, urb->interval)))
  173. return -ENOMEM;
  174. /* for the private part of the URB we need the number of TDs (size) */
  175. switch (ed->type) {
  176. case PIPE_CONTROL:
  177. /* td_submit_urb() doesn't yet handle these */
  178. if (urb->transfer_buffer_length > 4096)
  179. return -EMSGSIZE;
  180. /* 1 TD for setup, 1 for ACK, plus ... */
  181. size = 2;
  182. /* FALLTHROUGH */
  183. // case PIPE_INTERRUPT:
  184. // case PIPE_BULK:
  185. default:
  186. /* one TD for every 4096 Bytes (can be upto 8K) */
  187. size += urb->transfer_buffer_length / 4096;
  188. /* ... and for any remaining bytes ... */
  189. if ((urb->transfer_buffer_length % 4096) != 0)
  190. size++;
  191. /* ... and maybe a zero length packet to wrap it up */
  192. if (size == 0)
  193. size++;
  194. else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
  195. && (urb->transfer_buffer_length
  196. % usb_maxpacket (urb->dev, pipe,
  197. usb_pipeout (pipe))) == 0)
  198. size++;
  199. break;
  200. case PIPE_ISOCHRONOUS: /* number of packets from URB */
  201. size = urb->number_of_packets;
  202. break;
  203. }
  204. /* allocate the private part of the URB */
  205. urb_priv = kmalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
  206. mem_flags);
  207. if (!urb_priv)
  208. return -ENOMEM;
  209. memset (urb_priv, 0, sizeof (urb_priv_t) + size * sizeof (struct td *));
  210. INIT_LIST_HEAD (&urb_priv->pending);
  211. urb_priv->length = size;
  212. urb_priv->ed = ed;
  213. /* allocate the TDs (deferring hash chain updates) */
  214. for (i = 0; i < size; i++) {
  215. urb_priv->td [i] = td_alloc (ohci, mem_flags);
  216. if (!urb_priv->td [i]) {
  217. urb_priv->length = i;
  218. urb_free_priv (ohci, urb_priv);
  219. return -ENOMEM;
  220. }
  221. }
  222. spin_lock_irqsave (&ohci->lock, flags);
  223. /* don't submit to a dead HC */
  224. if (!HC_IS_RUNNING(hcd->state)) {
  225. retval = -ENODEV;
  226. goto fail;
  227. }
  228. /* in case of unlink-during-submit */
  229. spin_lock (&urb->lock);
  230. if (urb->status != -EINPROGRESS) {
  231. spin_unlock (&urb->lock);
  232. urb->hcpriv = urb_priv;
  233. finish_urb (ohci, urb, NULL);
  234. retval = 0;
  235. goto fail;
  236. }
  237. /* schedule the ed if needed */
  238. if (ed->state == ED_IDLE) {
  239. retval = ed_schedule (ohci, ed);
  240. if (retval < 0)
  241. goto fail0;
  242. if (ed->type == PIPE_ISOCHRONOUS) {
  243. u16 frame = ohci_frame_no(ohci);
  244. /* delay a few frames before the first TD */
  245. frame += max_t (u16, 8, ed->interval);
  246. frame &= ~(ed->interval - 1);
  247. frame |= ed->branch;
  248. urb->start_frame = frame;
  249. /* yes, only URB_ISO_ASAP is supported, and
  250. * urb->start_frame is never used as input.
  251. */
  252. }
  253. } else if (ed->type == PIPE_ISOCHRONOUS)
  254. urb->start_frame = ed->last_iso + ed->interval;
  255. /* fill the TDs and link them to the ed; and
  256. * enable that part of the schedule, if needed
  257. * and update count of queued periodic urbs
  258. */
  259. urb->hcpriv = urb_priv;
  260. td_submit_urb (ohci, urb);
  261. fail0:
  262. spin_unlock (&urb->lock);
  263. fail:
  264. if (retval)
  265. urb_free_priv (ohci, urb_priv);
  266. spin_unlock_irqrestore (&ohci->lock, flags);
  267. return retval;
  268. }
  269. /*
  270. * decouple the URB from the HC queues (TDs, urb_priv); it's
  271. * already marked using urb->status. reporting is always done
  272. * asynchronously, and we might be dealing with an urb that's
  273. * partially transferred, or an ED with other urbs being unlinked.
  274. */
  275. static int ohci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
  276. {
  277. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  278. unsigned long flags;
  279. #ifdef OHCI_VERBOSE_DEBUG
  280. urb_print (urb, "UNLINK", 1);
  281. #endif
  282. spin_lock_irqsave (&ohci->lock, flags);
  283. if (HC_IS_RUNNING(hcd->state)) {
  284. urb_priv_t *urb_priv;
  285. /* Unless an IRQ completed the unlink while it was being
  286. * handed to us, flag it for unlink and giveback, and force
  287. * some upcoming INTR_SF to call finish_unlinks()
  288. */
  289. urb_priv = urb->hcpriv;
  290. if (urb_priv) {
  291. if (urb_priv->ed->state == ED_OPER)
  292. start_ed_unlink (ohci, urb_priv->ed);
  293. }
  294. } else {
  295. /*
  296. * with HC dead, we won't respect hc queue pointers
  297. * any more ... just clean up every urb's memory.
  298. */
  299. if (urb->hcpriv)
  300. finish_urb (ohci, urb, NULL);
  301. }
  302. spin_unlock_irqrestore (&ohci->lock, flags);
  303. return 0;
  304. }
  305. /*-------------------------------------------------------------------------*/
  306. /* frees config/altsetting state for endpoints,
  307. * including ED memory, dummy TD, and bulk/intr data toggle
  308. */
  309. static void
  310. ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
  311. {
  312. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  313. unsigned long flags;
  314. struct ed *ed = ep->hcpriv;
  315. unsigned limit = 1000;
  316. /* ASSERT: any requests/urbs are being unlinked */
  317. /* ASSERT: nobody can be submitting urbs for this any more */
  318. if (!ed)
  319. return;
  320. rescan:
  321. spin_lock_irqsave (&ohci->lock, flags);
  322. if (!HC_IS_RUNNING (hcd->state)) {
  323. sanitize:
  324. ed->state = ED_IDLE;
  325. finish_unlinks (ohci, 0, NULL);
  326. }
  327. switch (ed->state) {
  328. case ED_UNLINK: /* wait for hw to finish? */
  329. /* major IRQ delivery trouble loses INTR_SF too... */
  330. if (limit-- == 0) {
  331. ohci_warn (ohci, "IRQ INTR_SF lossage\n");
  332. goto sanitize;
  333. }
  334. spin_unlock_irqrestore (&ohci->lock, flags);
  335. set_current_state (TASK_UNINTERRUPTIBLE);
  336. schedule_timeout (1);
  337. goto rescan;
  338. case ED_IDLE: /* fully unlinked */
  339. if (list_empty (&ed->td_list)) {
  340. td_free (ohci, ed->dummy);
  341. ed_free (ohci, ed);
  342. break;
  343. }
  344. /* else FALL THROUGH */
  345. default:
  346. /* caller was supposed to have unlinked any requests;
  347. * that's not our job. can't recover; must leak ed.
  348. */
  349. ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
  350. ed, ep->desc.bEndpointAddress, ed->state,
  351. list_empty (&ed->td_list) ? "" : " (has tds)");
  352. td_free (ohci, ed->dummy);
  353. break;
  354. }
  355. ep->hcpriv = NULL;
  356. spin_unlock_irqrestore (&ohci->lock, flags);
  357. return;
  358. }
  359. static int ohci_get_frame (struct usb_hcd *hcd)
  360. {
  361. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  362. return ohci_frame_no(ohci);
  363. }
  364. static void ohci_usb_reset (struct ohci_hcd *ohci)
  365. {
  366. ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
  367. ohci->hc_control &= OHCI_CTRL_RWC;
  368. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  369. }
  370. /*-------------------------------------------------------------------------*
  371. * HC functions
  372. *-------------------------------------------------------------------------*/
  373. /* init memory, and kick BIOS/SMM off */
  374. static int ohci_init (struct ohci_hcd *ohci)
  375. {
  376. int ret;
  377. disable (ohci);
  378. ohci->regs = ohci_to_hcd(ohci)->regs;
  379. ohci->next_statechange = jiffies;
  380. #ifndef IR_DISABLE
  381. /* SMM owns the HC? not for long! */
  382. if (!no_handshake && ohci_readl (ohci,
  383. &ohci->regs->control) & OHCI_CTRL_IR) {
  384. u32 temp;
  385. ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
  386. /* this timeout is arbitrary. we make it long, so systems
  387. * depending on usb keyboards may be usable even if the
  388. * BIOS/SMM code seems pretty broken.
  389. */
  390. temp = 500; /* arbitrary: five seconds */
  391. ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
  392. ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
  393. while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
  394. msleep (10);
  395. if (--temp == 0) {
  396. ohci_err (ohci, "USB HC takeover failed!"
  397. " (BIOS/SMM bug)\n");
  398. return -EBUSY;
  399. }
  400. }
  401. ohci_usb_reset (ohci);
  402. }
  403. #endif
  404. /* Disable HC interrupts */
  405. ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  406. // flush the writes
  407. (void) ohci_readl (ohci, &ohci->regs->control);
  408. if (ohci->hcca)
  409. return 0;
  410. ohci->hcca = dma_alloc_coherent (ohci_to_hcd(ohci)->self.controller,
  411. sizeof *ohci->hcca, &ohci->hcca_dma, 0);
  412. if (!ohci->hcca)
  413. return -ENOMEM;
  414. if ((ret = ohci_mem_init (ohci)) < 0)
  415. ohci_stop (ohci_to_hcd(ohci));
  416. return ret;
  417. }
  418. /*-------------------------------------------------------------------------*/
  419. /* Start an OHCI controller, set the BUS operational
  420. * resets USB and controller
  421. * enable interrupts
  422. * connect the virtual root hub
  423. */
  424. static int ohci_run (struct ohci_hcd *ohci)
  425. {
  426. u32 mask, temp;
  427. struct usb_device *udev;
  428. struct usb_bus *bus;
  429. int first = ohci->fminterval == 0;
  430. disable (ohci);
  431. /* boot firmware should have set this up (5.1.1.3.1) */
  432. if (first) {
  433. temp = ohci_readl (ohci, &ohci->regs->fminterval);
  434. ohci->fminterval = temp & 0x3fff;
  435. if (ohci->fminterval != FI)
  436. ohci_dbg (ohci, "fminterval delta %d\n",
  437. ohci->fminterval - FI);
  438. ohci->fminterval |= FSMP (ohci->fminterval) << 16;
  439. /* also: power/overcurrent flags in roothub.a */
  440. }
  441. /* Reset USB nearly "by the book". RemoteWakeupConnected
  442. * saved if boot firmware (BIOS/SMM/...) told us it's connected
  443. * (for OHCI integrated on mainboard, it normally is)
  444. */
  445. ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
  446. ohci_dbg (ohci, "resetting from state '%s', control = 0x%x\n",
  447. hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS),
  448. ohci->hc_control);
  449. if (ohci->hc_control & OHCI_CTRL_RWC
  450. && !(ohci->flags & OHCI_QUIRK_AMD756))
  451. ohci_to_hcd(ohci)->can_wakeup = 1;
  452. switch (ohci->hc_control & OHCI_CTRL_HCFS) {
  453. case OHCI_USB_OPER:
  454. temp = 0;
  455. break;
  456. case OHCI_USB_SUSPEND:
  457. case OHCI_USB_RESUME:
  458. ohci->hc_control &= OHCI_CTRL_RWC;
  459. ohci->hc_control |= OHCI_USB_RESUME;
  460. temp = 10 /* msec wait */;
  461. break;
  462. // case OHCI_USB_RESET:
  463. default:
  464. ohci->hc_control &= OHCI_CTRL_RWC;
  465. ohci->hc_control |= OHCI_USB_RESET;
  466. temp = 50 /* msec wait */;
  467. break;
  468. }
  469. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  470. // flush the writes
  471. (void) ohci_readl (ohci, &ohci->regs->control);
  472. msleep(temp);
  473. temp = roothub_a (ohci);
  474. if (!(temp & RH_A_NPS)) {
  475. unsigned ports = temp & RH_A_NDP;
  476. /* power down each port */
  477. for (temp = 0; temp < ports; temp++)
  478. ohci_writel (ohci, RH_PS_LSDA,
  479. &ohci->regs->roothub.portstatus [temp]);
  480. }
  481. // flush those writes
  482. (void) ohci_readl (ohci, &ohci->regs->control);
  483. memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
  484. /* 2msec timelimit here means no irqs/preempt */
  485. spin_lock_irq (&ohci->lock);
  486. retry:
  487. /* HC Reset requires max 10 us delay */
  488. ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
  489. temp = 30; /* ... allow extra time */
  490. while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  491. if (--temp == 0) {
  492. spin_unlock_irq (&ohci->lock);
  493. ohci_err (ohci, "USB HC reset timed out!\n");
  494. return -1;
  495. }
  496. udelay (1);
  497. }
  498. /* now we're in the SUSPEND state ... must go OPERATIONAL
  499. * within 2msec else HC enters RESUME
  500. *
  501. * ... but some hardware won't init fmInterval "by the book"
  502. * (SiS, OPTi ...), so reset again instead. SiS doesn't need
  503. * this if we write fmInterval after we're OPERATIONAL.
  504. * Unclear about ALi, ServerWorks, and others ... this could
  505. * easily be a longstanding bug in chip init on Linux.
  506. */
  507. if (ohci->flags & OHCI_QUIRK_INITRESET) {
  508. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  509. // flush those writes
  510. (void) ohci_readl (ohci, &ohci->regs->control);
  511. }
  512. /* Tell the controller where the control and bulk lists are
  513. * The lists are empty now. */
  514. ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
  515. ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
  516. /* a reset clears this */
  517. ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
  518. periodic_reinit (ohci);
  519. /* some OHCI implementations are finicky about how they init.
  520. * bogus values here mean not even enumeration could work.
  521. */
  522. if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
  523. || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
  524. if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
  525. ohci->flags |= OHCI_QUIRK_INITRESET;
  526. ohci_dbg (ohci, "enabling initreset quirk\n");
  527. goto retry;
  528. }
  529. spin_unlock_irq (&ohci->lock);
  530. ohci_err (ohci, "init err (%08x %04x)\n",
  531. ohci_readl (ohci, &ohci->regs->fminterval),
  532. ohci_readl (ohci, &ohci->regs->periodicstart));
  533. return -EOVERFLOW;
  534. }
  535. /* start controller operations */
  536. ohci->hc_control &= OHCI_CTRL_RWC;
  537. ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
  538. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  539. ohci_to_hcd(ohci)->state = HC_STATE_RUNNING;
  540. /* wake on ConnectStatusChange, matching external hubs */
  541. ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
  542. /* Choose the interrupts we care about now, others later on demand */
  543. mask = OHCI_INTR_INIT;
  544. ohci_writel (ohci, mask, &ohci->regs->intrstatus);
  545. ohci_writel (ohci, mask, &ohci->regs->intrenable);
  546. /* handle root hub init quirks ... */
  547. temp = roothub_a (ohci);
  548. temp &= ~(RH_A_PSM | RH_A_OCPM);
  549. if (ohci->flags & OHCI_QUIRK_SUPERIO) {
  550. /* NSC 87560 and maybe others */
  551. temp |= RH_A_NOCP;
  552. temp &= ~(RH_A_POTPGT | RH_A_NPS);
  553. ohci_writel (ohci, temp, &ohci->regs->roothub.a);
  554. } else if ((ohci->flags & OHCI_QUIRK_AMD756) || distrust_firmware) {
  555. /* hub power always on; required for AMD-756 and some
  556. * Mac platforms. ganged overcurrent reporting, if any.
  557. */
  558. temp |= RH_A_NPS;
  559. ohci_writel (ohci, temp, &ohci->regs->roothub.a);
  560. }
  561. ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
  562. ohci_writel (ohci, (temp & RH_A_NPS) ? 0 : RH_B_PPCM,
  563. &ohci->regs->roothub.b);
  564. // flush those writes
  565. (void) ohci_readl (ohci, &ohci->regs->control);
  566. spin_unlock_irq (&ohci->lock);
  567. // POTPGT delay is bits 24-31, in 2 ms units.
  568. mdelay ((temp >> 23) & 0x1fe);
  569. bus = &ohci_to_hcd(ohci)->self;
  570. ohci_to_hcd(ohci)->state = HC_STATE_RUNNING;
  571. ohci_dump (ohci, 1);
  572. udev = bus->root_hub;
  573. if (udev) {
  574. return 0;
  575. }
  576. /* connect the virtual root hub */
  577. udev = usb_alloc_dev (NULL, bus, 0);
  578. if (!udev) {
  579. disable (ohci);
  580. ohci->hc_control &= ~OHCI_CTRL_HCFS;
  581. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  582. return -ENOMEM;
  583. }
  584. udev->speed = USB_SPEED_FULL;
  585. if (usb_hcd_register_root_hub (udev, ohci_to_hcd(ohci)) != 0) {
  586. usb_put_dev (udev);
  587. disable (ohci);
  588. ohci->hc_control &= ~OHCI_CTRL_HCFS;
  589. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  590. return -ENODEV;
  591. }
  592. if (ohci->power_budget)
  593. hub_set_power_budget(udev, ohci->power_budget);
  594. create_debug_files (ohci);
  595. return 0;
  596. }
  597. /*-------------------------------------------------------------------------*/
  598. /* an interrupt happens */
  599. static irqreturn_t ohci_irq (struct usb_hcd *hcd, struct pt_regs *ptregs)
  600. {
  601. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  602. struct ohci_regs __iomem *regs = ohci->regs;
  603. int ints;
  604. /* we can eliminate a (slow) ohci_readl()
  605. if _only_ WDH caused this irq */
  606. if ((ohci->hcca->done_head != 0)
  607. && ! (hc32_to_cpup (ohci, &ohci->hcca->done_head)
  608. & 0x01)) {
  609. ints = OHCI_INTR_WDH;
  610. /* cardbus/... hardware gone before remove() */
  611. } else if ((ints = ohci_readl (ohci, &regs->intrstatus)) == ~(u32)0) {
  612. disable (ohci);
  613. ohci_dbg (ohci, "device removed!\n");
  614. return IRQ_HANDLED;
  615. /* interrupt for some other device? */
  616. } else if ((ints &= ohci_readl (ohci, &regs->intrenable)) == 0) {
  617. return IRQ_NOTMINE;
  618. }
  619. if (ints & OHCI_INTR_UE) {
  620. disable (ohci);
  621. ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
  622. // e.g. due to PCI Master/Target Abort
  623. ohci_dump (ohci, 1);
  624. ohci_usb_reset (ohci);
  625. }
  626. if (ints & OHCI_INTR_RD) {
  627. ohci_vdbg (ohci, "resume detect\n");
  628. if (hcd->state != HC_STATE_QUIESCING)
  629. schedule_work(&ohci->rh_resume);
  630. }
  631. if (ints & OHCI_INTR_WDH) {
  632. if (HC_IS_RUNNING(hcd->state))
  633. ohci_writel (ohci, OHCI_INTR_WDH, &regs->intrdisable);
  634. spin_lock (&ohci->lock);
  635. dl_done_list (ohci, ptregs);
  636. spin_unlock (&ohci->lock);
  637. if (HC_IS_RUNNING(hcd->state))
  638. ohci_writel (ohci, OHCI_INTR_WDH, &regs->intrenable);
  639. }
  640. /* could track INTR_SO to reduce available PCI/... bandwidth */
  641. /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
  642. * when there's still unlinking to be done (next frame).
  643. */
  644. spin_lock (&ohci->lock);
  645. if (ohci->ed_rm_list)
  646. finish_unlinks (ohci, ohci_frame_no(ohci), ptregs);
  647. if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
  648. && HC_IS_RUNNING(hcd->state))
  649. ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
  650. spin_unlock (&ohci->lock);
  651. if (HC_IS_RUNNING(hcd->state)) {
  652. ohci_writel (ohci, ints, &regs->intrstatus);
  653. ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
  654. // flush those writes
  655. (void) ohci_readl (ohci, &ohci->regs->control);
  656. }
  657. return IRQ_HANDLED;
  658. }
  659. /*-------------------------------------------------------------------------*/
  660. static void ohci_stop (struct usb_hcd *hcd)
  661. {
  662. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  663. ohci_dbg (ohci, "stop %s controller (state 0x%02x)\n",
  664. hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS),
  665. hcd->state);
  666. ohci_dump (ohci, 1);
  667. flush_scheduled_work();
  668. ohci_usb_reset (ohci);
  669. ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  670. remove_debug_files (ohci);
  671. ohci_mem_cleanup (ohci);
  672. if (ohci->hcca) {
  673. dma_free_coherent (hcd->self.controller,
  674. sizeof *ohci->hcca,
  675. ohci->hcca, ohci->hcca_dma);
  676. ohci->hcca = NULL;
  677. ohci->hcca_dma = 0;
  678. }
  679. }
  680. /*-------------------------------------------------------------------------*/
  681. /* must not be called from interrupt context */
  682. #if defined(CONFIG_USB_SUSPEND) || defined(CONFIG_PM)
  683. static int ohci_restart (struct ohci_hcd *ohci)
  684. {
  685. int temp;
  686. int i;
  687. struct urb_priv *priv;
  688. struct usb_device *root = ohci_to_hcd(ohci)->self.root_hub;
  689. /* mark any devices gone, so they do nothing till khubd disconnects.
  690. * recycle any "live" eds/tds (and urbs) right away.
  691. * later, khubd disconnect processing will recycle the other state,
  692. * (either as disconnect/reconnect, or maybe someday as a reset).
  693. */
  694. spin_lock_irq(&ohci->lock);
  695. disable (ohci);
  696. for (i = 0; i < root->maxchild; i++) {
  697. if (root->children [i])
  698. usb_set_device_state (root->children[i],
  699. USB_STATE_NOTATTACHED);
  700. }
  701. if (!list_empty (&ohci->pending))
  702. ohci_dbg(ohci, "abort schedule...\n");
  703. list_for_each_entry (priv, &ohci->pending, pending) {
  704. struct urb *urb = priv->td[0]->urb;
  705. struct ed *ed = priv->ed;
  706. switch (ed->state) {
  707. case ED_OPER:
  708. ed->state = ED_UNLINK;
  709. ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
  710. ed_deschedule (ohci, ed);
  711. ed->ed_next = ohci->ed_rm_list;
  712. ed->ed_prev = NULL;
  713. ohci->ed_rm_list = ed;
  714. /* FALLTHROUGH */
  715. case ED_UNLINK:
  716. break;
  717. default:
  718. ohci_dbg(ohci, "bogus ed %p state %d\n",
  719. ed, ed->state);
  720. }
  721. spin_lock (&urb->lock);
  722. urb->status = -ESHUTDOWN;
  723. spin_unlock (&urb->lock);
  724. }
  725. finish_unlinks (ohci, 0, NULL);
  726. spin_unlock_irq(&ohci->lock);
  727. /* paranoia, in case that didn't work: */
  728. /* empty the interrupt branches */
  729. for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
  730. for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
  731. /* no EDs to remove */
  732. ohci->ed_rm_list = NULL;
  733. /* empty control and bulk lists */
  734. ohci->ed_controltail = NULL;
  735. ohci->ed_bulktail = NULL;
  736. if ((temp = ohci_run (ohci)) < 0) {
  737. ohci_err (ohci, "can't restart, %d\n", temp);
  738. return temp;
  739. } else {
  740. /* here we "know" root ports should always stay powered,
  741. * and that if we try to turn them back on the root hub
  742. * will respond to CSC processing.
  743. */
  744. i = roothub_a (ohci) & RH_A_NDP;
  745. while (i--)
  746. ohci_writel (ohci, RH_PS_PSS,
  747. &ohci->regs->roothub.portstatus [temp]);
  748. ohci_dbg (ohci, "restart complete\n");
  749. }
  750. return 0;
  751. }
  752. #endif
  753. /*-------------------------------------------------------------------------*/
  754. #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
  755. MODULE_AUTHOR (DRIVER_AUTHOR);
  756. MODULE_DESCRIPTION (DRIVER_INFO);
  757. MODULE_LICENSE ("GPL");
  758. #ifdef CONFIG_PCI
  759. #include "ohci-pci.c"
  760. #endif
  761. #ifdef CONFIG_SA1111
  762. #include "ohci-sa1111.c"
  763. #endif
  764. #ifdef CONFIG_ARCH_OMAP
  765. #include "ohci-omap.c"
  766. #endif
  767. #ifdef CONFIG_ARCH_LH7A404
  768. #include "ohci-lh7a404.c"
  769. #endif
  770. #ifdef CONFIG_PXA27x
  771. #include "ohci-pxa27x.c"
  772. #endif
  773. #ifdef CONFIG_SOC_AU1X00
  774. #include "ohci-au1xxx.c"
  775. #endif
  776. #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
  777. #include "ohci-ppc-soc.c"
  778. #endif
  779. #if !(defined(CONFIG_PCI) \
  780. || defined(CONFIG_SA1111) \
  781. || defined(CONFIG_ARCH_OMAP) \
  782. || defined (CONFIG_ARCH_LH7A404) \
  783. || defined (CONFIG_PXA27x) \
  784. || defined (CONFIG_SOC_AU1X00) \
  785. || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \
  786. )
  787. #error "missing bus glue for ohci-hcd"
  788. #endif