rx.c 17 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2011 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/socket.h>
  11. #include <linux/in.h>
  12. #include <linux/slab.h>
  13. #include <linux/ip.h>
  14. #include <linux/tcp.h>
  15. #include <linux/udp.h>
  16. #include <linux/prefetch.h>
  17. #include <linux/moduleparam.h>
  18. #include <net/ip.h>
  19. #include <net/checksum.h>
  20. #include "net_driver.h"
  21. #include "efx.h"
  22. #include "nic.h"
  23. #include "selftest.h"
  24. #include "workarounds.h"
  25. /* Number of RX descriptors pushed at once. */
  26. #define EFX_RX_BATCH 8
  27. /* Maximum length for an RX descriptor sharing a page */
  28. #define EFX_RX_HALF_PAGE ((PAGE_SIZE >> 1) - sizeof(struct efx_rx_page_state) \
  29. - EFX_PAGE_IP_ALIGN)
  30. /* Size of buffer allocated for skb header area. */
  31. #define EFX_SKB_HEADERS 64u
  32. /* This is the percentage fill level below which new RX descriptors
  33. * will be added to the RX descriptor ring.
  34. */
  35. static unsigned int rx_refill_threshold;
  36. /*
  37. * RX maximum head room required.
  38. *
  39. * This must be at least 1 to prevent overflow and at least 2 to allow
  40. * pipelined receives.
  41. */
  42. #define EFX_RXD_HEAD_ROOM 2
  43. /* Offset of ethernet header within page */
  44. static inline unsigned int efx_rx_buf_offset(struct efx_nic *efx,
  45. struct efx_rx_buffer *buf)
  46. {
  47. return buf->page_offset + efx->type->rx_buffer_hash_size;
  48. }
  49. static u8 *efx_rx_buf_eh(struct efx_nic *efx, struct efx_rx_buffer *buf)
  50. {
  51. return page_address(buf->page) + efx_rx_buf_offset(efx, buf);
  52. }
  53. static inline u32 efx_rx_buf_hash(const u8 *eh)
  54. {
  55. /* The ethernet header is always directly after any hash. */
  56. #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) || NET_IP_ALIGN % 4 == 0
  57. return __le32_to_cpup((const __le32 *)(eh - 4));
  58. #else
  59. const u8 *data = eh - 4;
  60. return (u32)data[0] |
  61. (u32)data[1] << 8 |
  62. (u32)data[2] << 16 |
  63. (u32)data[3] << 24;
  64. #endif
  65. }
  66. /**
  67. * efx_init_rx_buffers - create EFX_RX_BATCH page-based RX buffers
  68. *
  69. * @rx_queue: Efx RX queue
  70. *
  71. * This allocates memory for EFX_RX_BATCH receive buffers, maps them for DMA,
  72. * and populates struct efx_rx_buffers for each one. Return a negative error
  73. * code or 0 on success. If a single page can be split between two buffers,
  74. * then the page will either be inserted fully, or not at at all.
  75. */
  76. static int efx_init_rx_buffers(struct efx_rx_queue *rx_queue)
  77. {
  78. struct efx_nic *efx = rx_queue->efx;
  79. struct efx_rx_buffer *rx_buf;
  80. struct page *page;
  81. unsigned int page_offset;
  82. struct efx_rx_page_state *state;
  83. dma_addr_t dma_addr;
  84. unsigned index, count;
  85. /* We can split a page between two buffers */
  86. BUILD_BUG_ON(EFX_RX_BATCH & 1);
  87. for (count = 0; count < EFX_RX_BATCH; ++count) {
  88. page = alloc_pages(__GFP_COLD | __GFP_COMP | GFP_ATOMIC,
  89. efx->rx_buffer_order);
  90. if (unlikely(page == NULL))
  91. return -ENOMEM;
  92. dma_addr = dma_map_page(&efx->pci_dev->dev, page, 0,
  93. PAGE_SIZE << efx->rx_buffer_order,
  94. DMA_FROM_DEVICE);
  95. if (unlikely(dma_mapping_error(&efx->pci_dev->dev, dma_addr))) {
  96. __free_pages(page, efx->rx_buffer_order);
  97. return -EIO;
  98. }
  99. state = page_address(page);
  100. state->refcnt = 0;
  101. state->dma_addr = dma_addr;
  102. dma_addr += sizeof(struct efx_rx_page_state);
  103. page_offset = sizeof(struct efx_rx_page_state);
  104. split:
  105. index = rx_queue->added_count & rx_queue->ptr_mask;
  106. rx_buf = efx_rx_buffer(rx_queue, index);
  107. rx_buf->dma_addr = dma_addr + EFX_PAGE_IP_ALIGN;
  108. rx_buf->page = page;
  109. rx_buf->page_offset = page_offset + EFX_PAGE_IP_ALIGN;
  110. rx_buf->len = efx->rx_dma_len;
  111. rx_buf->flags = 0;
  112. ++rx_queue->added_count;
  113. ++state->refcnt;
  114. if ((~count & 1) && (efx->rx_dma_len <= EFX_RX_HALF_PAGE)) {
  115. /* Use the second half of the page */
  116. get_page(page);
  117. dma_addr += (PAGE_SIZE >> 1);
  118. page_offset += (PAGE_SIZE >> 1);
  119. ++count;
  120. goto split;
  121. }
  122. }
  123. return 0;
  124. }
  125. static void efx_unmap_rx_buffer(struct efx_nic *efx,
  126. struct efx_rx_buffer *rx_buf,
  127. unsigned int used_len)
  128. {
  129. if (rx_buf->page) {
  130. struct efx_rx_page_state *state;
  131. state = page_address(rx_buf->page);
  132. if (--state->refcnt == 0) {
  133. dma_unmap_page(&efx->pci_dev->dev,
  134. state->dma_addr,
  135. PAGE_SIZE << efx->rx_buffer_order,
  136. DMA_FROM_DEVICE);
  137. } else if (used_len) {
  138. dma_sync_single_for_cpu(&efx->pci_dev->dev,
  139. rx_buf->dma_addr, used_len,
  140. DMA_FROM_DEVICE);
  141. }
  142. }
  143. }
  144. static void efx_free_rx_buffer(struct efx_nic *efx,
  145. struct efx_rx_buffer *rx_buf)
  146. {
  147. if (rx_buf->page) {
  148. __free_pages(rx_buf->page, efx->rx_buffer_order);
  149. rx_buf->page = NULL;
  150. }
  151. }
  152. static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
  153. struct efx_rx_buffer *rx_buf)
  154. {
  155. efx_unmap_rx_buffer(rx_queue->efx, rx_buf, 0);
  156. efx_free_rx_buffer(rx_queue->efx, rx_buf);
  157. }
  158. /* Attempt to resurrect the other receive buffer that used to share this page,
  159. * which had previously been passed up to the kernel and freed. */
  160. static void efx_resurrect_rx_buffer(struct efx_rx_queue *rx_queue,
  161. struct efx_rx_buffer *rx_buf)
  162. {
  163. struct efx_rx_page_state *state = page_address(rx_buf->page);
  164. struct efx_rx_buffer *new_buf;
  165. unsigned fill_level, index;
  166. /* +1 because efx_rx_packet() incremented removed_count. +1 because
  167. * we'd like to insert an additional descriptor whilst leaving
  168. * EFX_RXD_HEAD_ROOM for the non-recycle path */
  169. fill_level = (rx_queue->added_count - rx_queue->removed_count + 2);
  170. if (unlikely(fill_level > rx_queue->max_fill)) {
  171. /* We could place "state" on a list, and drain the list in
  172. * efx_fast_push_rx_descriptors(). For now, this will do. */
  173. return;
  174. }
  175. ++state->refcnt;
  176. get_page(rx_buf->page);
  177. index = rx_queue->added_count & rx_queue->ptr_mask;
  178. new_buf = efx_rx_buffer(rx_queue, index);
  179. new_buf->dma_addr = rx_buf->dma_addr ^ (PAGE_SIZE >> 1);
  180. new_buf->page = rx_buf->page;
  181. new_buf->len = rx_buf->len;
  182. ++rx_queue->added_count;
  183. }
  184. /* Recycle the given rx buffer directly back into the rx_queue. There is
  185. * always room to add this buffer, because we've just popped a buffer. */
  186. static void efx_recycle_rx_buffer(struct efx_channel *channel,
  187. struct efx_rx_buffer *rx_buf)
  188. {
  189. struct efx_nic *efx = channel->efx;
  190. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  191. struct efx_rx_buffer *new_buf;
  192. unsigned index;
  193. rx_buf->flags = 0;
  194. if (efx->rx_dma_len <= EFX_RX_HALF_PAGE &&
  195. page_count(rx_buf->page) == 1)
  196. efx_resurrect_rx_buffer(rx_queue, rx_buf);
  197. index = rx_queue->added_count & rx_queue->ptr_mask;
  198. new_buf = efx_rx_buffer(rx_queue, index);
  199. memcpy(new_buf, rx_buf, sizeof(*new_buf));
  200. rx_buf->page = NULL;
  201. ++rx_queue->added_count;
  202. }
  203. /**
  204. * efx_fast_push_rx_descriptors - push new RX descriptors quickly
  205. * @rx_queue: RX descriptor queue
  206. *
  207. * This will aim to fill the RX descriptor queue up to
  208. * @rx_queue->@max_fill. If there is insufficient atomic
  209. * memory to do so, a slow fill will be scheduled.
  210. *
  211. * The caller must provide serialisation (none is used here). In practise,
  212. * this means this function must run from the NAPI handler, or be called
  213. * when NAPI is disabled.
  214. */
  215. void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue)
  216. {
  217. unsigned fill_level;
  218. int space, rc = 0;
  219. /* Calculate current fill level, and exit if we don't need to fill */
  220. fill_level = (rx_queue->added_count - rx_queue->removed_count);
  221. EFX_BUG_ON_PARANOID(fill_level > rx_queue->efx->rxq_entries);
  222. if (fill_level >= rx_queue->fast_fill_trigger)
  223. goto out;
  224. /* Record minimum fill level */
  225. if (unlikely(fill_level < rx_queue->min_fill)) {
  226. if (fill_level)
  227. rx_queue->min_fill = fill_level;
  228. }
  229. space = rx_queue->max_fill - fill_level;
  230. EFX_BUG_ON_PARANOID(space < EFX_RX_BATCH);
  231. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  232. "RX queue %d fast-filling descriptor ring from"
  233. " level %d to level %d\n",
  234. efx_rx_queue_index(rx_queue), fill_level,
  235. rx_queue->max_fill);
  236. do {
  237. rc = efx_init_rx_buffers(rx_queue);
  238. if (unlikely(rc)) {
  239. /* Ensure that we don't leave the rx queue empty */
  240. if (rx_queue->added_count == rx_queue->removed_count)
  241. efx_schedule_slow_fill(rx_queue);
  242. goto out;
  243. }
  244. } while ((space -= EFX_RX_BATCH) >= EFX_RX_BATCH);
  245. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  246. "RX queue %d fast-filled descriptor ring "
  247. "to level %d\n", efx_rx_queue_index(rx_queue),
  248. rx_queue->added_count - rx_queue->removed_count);
  249. out:
  250. if (rx_queue->notified_count != rx_queue->added_count)
  251. efx_nic_notify_rx_desc(rx_queue);
  252. }
  253. void efx_rx_slow_fill(unsigned long context)
  254. {
  255. struct efx_rx_queue *rx_queue = (struct efx_rx_queue *)context;
  256. /* Post an event to cause NAPI to run and refill the queue */
  257. efx_nic_generate_fill_event(rx_queue);
  258. ++rx_queue->slow_fill_count;
  259. }
  260. static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue,
  261. struct efx_rx_buffer *rx_buf,
  262. int len)
  263. {
  264. struct efx_nic *efx = rx_queue->efx;
  265. unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding;
  266. if (likely(len <= max_len))
  267. return;
  268. /* The packet must be discarded, but this is only a fatal error
  269. * if the caller indicated it was
  270. */
  271. rx_buf->flags |= EFX_RX_PKT_DISCARD;
  272. if ((len > rx_buf->len) && EFX_WORKAROUND_8071(efx)) {
  273. if (net_ratelimit())
  274. netif_err(efx, rx_err, efx->net_dev,
  275. " RX queue %d seriously overlength "
  276. "RX event (0x%x > 0x%x+0x%x). Leaking\n",
  277. efx_rx_queue_index(rx_queue), len, max_len,
  278. efx->type->rx_buffer_padding);
  279. efx_schedule_reset(efx, RESET_TYPE_RX_RECOVERY);
  280. } else {
  281. if (net_ratelimit())
  282. netif_err(efx, rx_err, efx->net_dev,
  283. " RX queue %d overlength RX event "
  284. "(0x%x > 0x%x)\n",
  285. efx_rx_queue_index(rx_queue), len, max_len);
  286. }
  287. efx_rx_queue_channel(rx_queue)->n_rx_overlength++;
  288. }
  289. /* Pass a received packet up through GRO. GRO can handle pages
  290. * regardless of checksum state and skbs with a good checksum.
  291. */
  292. static void efx_rx_packet_gro(struct efx_channel *channel,
  293. struct efx_rx_buffer *rx_buf,
  294. const u8 *eh)
  295. {
  296. struct napi_struct *napi = &channel->napi_str;
  297. gro_result_t gro_result;
  298. struct efx_nic *efx = channel->efx;
  299. struct page *page = rx_buf->page;
  300. struct sk_buff *skb;
  301. rx_buf->page = NULL;
  302. skb = napi_get_frags(napi);
  303. if (!skb) {
  304. put_page(page);
  305. return;
  306. }
  307. if (efx->net_dev->features & NETIF_F_RXHASH)
  308. skb->rxhash = efx_rx_buf_hash(eh);
  309. skb_fill_page_desc(skb, 0, page,
  310. efx_rx_buf_offset(efx, rx_buf), rx_buf->len);
  311. skb->len = rx_buf->len;
  312. skb->data_len = rx_buf->len;
  313. skb->truesize += rx_buf->len;
  314. skb->ip_summed = ((rx_buf->flags & EFX_RX_PKT_CSUMMED) ?
  315. CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
  316. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  317. gro_result = napi_gro_frags(napi);
  318. if (gro_result != GRO_DROP)
  319. channel->irq_mod_score += 2;
  320. }
  321. /* Allocate and construct an SKB around a struct page.*/
  322. static struct sk_buff *efx_rx_mk_skb(struct efx_channel *channel,
  323. struct efx_rx_buffer *rx_buf,
  324. u8 *eh, int hdr_len)
  325. {
  326. struct efx_nic *efx = channel->efx;
  327. struct sk_buff *skb;
  328. /* Allocate an SKB to store the headers */
  329. skb = netdev_alloc_skb(efx->net_dev, hdr_len + EFX_PAGE_SKB_ALIGN);
  330. if (unlikely(skb == NULL))
  331. return NULL;
  332. EFX_BUG_ON_PARANOID(rx_buf->len < hdr_len);
  333. skb_reserve(skb, EFX_PAGE_SKB_ALIGN);
  334. skb->len = rx_buf->len;
  335. skb->truesize = rx_buf->len + sizeof(struct sk_buff);
  336. memcpy(skb->data, eh, hdr_len);
  337. skb->tail += hdr_len;
  338. /* Append the remaining page onto the frag list */
  339. if (rx_buf->len > hdr_len) {
  340. skb->data_len = skb->len - hdr_len;
  341. skb_fill_page_desc(skb, 0, rx_buf->page,
  342. efx_rx_buf_offset(efx, rx_buf) + hdr_len,
  343. skb->data_len);
  344. } else {
  345. __free_pages(rx_buf->page, efx->rx_buffer_order);
  346. skb->data_len = 0;
  347. }
  348. /* Ownership has transferred from the rx_buf to skb */
  349. rx_buf->page = NULL;
  350. /* Move past the ethernet header */
  351. skb->protocol = eth_type_trans(skb, efx->net_dev);
  352. return skb;
  353. }
  354. void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index,
  355. unsigned int len, u16 flags)
  356. {
  357. struct efx_nic *efx = rx_queue->efx;
  358. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  359. struct efx_rx_buffer *rx_buf;
  360. rx_buf = efx_rx_buffer(rx_queue, index);
  361. rx_buf->flags |= flags;
  362. /* This allows the refill path to post another buffer.
  363. * EFX_RXD_HEAD_ROOM ensures that the slot we are using
  364. * isn't overwritten yet.
  365. */
  366. rx_queue->removed_count++;
  367. /* Validate the length encoded in the event vs the descriptor pushed */
  368. efx_rx_packet__check_len(rx_queue, rx_buf, len);
  369. netif_vdbg(efx, rx_status, efx->net_dev,
  370. "RX queue %d received id %x at %llx+%x %s%s\n",
  371. efx_rx_queue_index(rx_queue), index,
  372. (unsigned long long)rx_buf->dma_addr, len,
  373. (rx_buf->flags & EFX_RX_PKT_CSUMMED) ? " [SUMMED]" : "",
  374. (rx_buf->flags & EFX_RX_PKT_DISCARD) ? " [DISCARD]" : "");
  375. /* Discard packet, if instructed to do so */
  376. if (unlikely(rx_buf->flags & EFX_RX_PKT_DISCARD)) {
  377. efx_recycle_rx_buffer(channel, rx_buf);
  378. /* Don't hold off the previous receive */
  379. rx_buf = NULL;
  380. goto out;
  381. }
  382. /* Release and/or sync DMA mapping - assumes all RX buffers
  383. * consumed in-order per RX queue
  384. */
  385. efx_unmap_rx_buffer(efx, rx_buf, len);
  386. /* Prefetch nice and early so data will (hopefully) be in cache by
  387. * the time we look at it.
  388. */
  389. prefetch(efx_rx_buf_eh(efx, rx_buf));
  390. /* Pipeline receives so that we give time for packet headers to be
  391. * prefetched into cache.
  392. */
  393. rx_buf->len = len - efx->type->rx_buffer_hash_size;
  394. out:
  395. efx_rx_flush_packet(channel);
  396. channel->rx_pkt = rx_buf;
  397. }
  398. static void efx_rx_deliver(struct efx_channel *channel, u8 *eh,
  399. struct efx_rx_buffer *rx_buf)
  400. {
  401. struct sk_buff *skb;
  402. u16 hdr_len = min_t(u16, rx_buf->len, EFX_SKB_HEADERS);
  403. skb = efx_rx_mk_skb(channel, rx_buf, eh, hdr_len);
  404. if (unlikely(skb == NULL)) {
  405. efx_free_rx_buffer(channel->efx, rx_buf);
  406. return;
  407. }
  408. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  409. /* Set the SKB flags */
  410. skb_checksum_none_assert(skb);
  411. if (channel->type->receive_skb)
  412. if (channel->type->receive_skb(channel, skb))
  413. return;
  414. /* Pass the packet up */
  415. netif_receive_skb(skb);
  416. }
  417. /* Handle a received packet. Second half: Touches packet payload. */
  418. void __efx_rx_packet(struct efx_channel *channel, struct efx_rx_buffer *rx_buf)
  419. {
  420. struct efx_nic *efx = channel->efx;
  421. u8 *eh = efx_rx_buf_eh(efx, rx_buf);
  422. /* If we're in loopback test, then pass the packet directly to the
  423. * loopback layer, and free the rx_buf here
  424. */
  425. if (unlikely(efx->loopback_selftest)) {
  426. efx_loopback_rx_packet(efx, eh, rx_buf->len);
  427. efx_free_rx_buffer(efx, rx_buf);
  428. return;
  429. }
  430. if (unlikely(!(efx->net_dev->features & NETIF_F_RXCSUM)))
  431. rx_buf->flags &= ~EFX_RX_PKT_CSUMMED;
  432. if (!channel->type->receive_skb)
  433. efx_rx_packet_gro(channel, rx_buf, eh);
  434. else
  435. efx_rx_deliver(channel, eh, rx_buf);
  436. }
  437. int efx_probe_rx_queue(struct efx_rx_queue *rx_queue)
  438. {
  439. struct efx_nic *efx = rx_queue->efx;
  440. unsigned int entries;
  441. int rc;
  442. /* Create the smallest power-of-two aligned ring */
  443. entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
  444. EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  445. rx_queue->ptr_mask = entries - 1;
  446. netif_dbg(efx, probe, efx->net_dev,
  447. "creating RX queue %d size %#x mask %#x\n",
  448. efx_rx_queue_index(rx_queue), efx->rxq_entries,
  449. rx_queue->ptr_mask);
  450. /* Allocate RX buffers */
  451. rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer),
  452. GFP_KERNEL);
  453. if (!rx_queue->buffer)
  454. return -ENOMEM;
  455. rc = efx_nic_probe_rx(rx_queue);
  456. if (rc) {
  457. kfree(rx_queue->buffer);
  458. rx_queue->buffer = NULL;
  459. }
  460. return rc;
  461. }
  462. void efx_init_rx_queue(struct efx_rx_queue *rx_queue)
  463. {
  464. struct efx_nic *efx = rx_queue->efx;
  465. unsigned int max_fill, trigger, max_trigger;
  466. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  467. "initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
  468. /* Initialise ptr fields */
  469. rx_queue->added_count = 0;
  470. rx_queue->notified_count = 0;
  471. rx_queue->removed_count = 0;
  472. rx_queue->min_fill = -1U;
  473. /* Initialise limit fields */
  474. max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
  475. max_trigger = max_fill - EFX_RX_BATCH;
  476. if (rx_refill_threshold != 0) {
  477. trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
  478. if (trigger > max_trigger)
  479. trigger = max_trigger;
  480. } else {
  481. trigger = max_trigger;
  482. }
  483. rx_queue->max_fill = max_fill;
  484. rx_queue->fast_fill_trigger = trigger;
  485. /* Set up RX descriptor ring */
  486. rx_queue->enabled = true;
  487. efx_nic_init_rx(rx_queue);
  488. }
  489. void efx_fini_rx_queue(struct efx_rx_queue *rx_queue)
  490. {
  491. int i;
  492. struct efx_rx_buffer *rx_buf;
  493. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  494. "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
  495. /* A flush failure might have left rx_queue->enabled */
  496. rx_queue->enabled = false;
  497. del_timer_sync(&rx_queue->slow_fill);
  498. efx_nic_fini_rx(rx_queue);
  499. /* Release RX buffers NB start at index 0 not current HW ptr */
  500. if (rx_queue->buffer) {
  501. for (i = 0; i <= rx_queue->ptr_mask; i++) {
  502. rx_buf = efx_rx_buffer(rx_queue, i);
  503. efx_fini_rx_buffer(rx_queue, rx_buf);
  504. }
  505. }
  506. }
  507. void efx_remove_rx_queue(struct efx_rx_queue *rx_queue)
  508. {
  509. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  510. "destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
  511. efx_nic_remove_rx(rx_queue);
  512. kfree(rx_queue->buffer);
  513. rx_queue->buffer = NULL;
  514. }
  515. module_param(rx_refill_threshold, uint, 0444);
  516. MODULE_PARM_DESC(rx_refill_threshold,
  517. "RX descriptor ring refill threshold (%)");