omap3.dtsi 11 KB

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  1. /*
  2. * Device Tree Source for OMAP3 SoC
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "ti,omap3430", "ti,omap3";
  13. interrupt-parent = <&intc>;
  14. aliases {
  15. serial0 = &uart1;
  16. serial1 = &uart2;
  17. serial2 = &uart3;
  18. };
  19. cpus {
  20. cpu@0 {
  21. compatible = "arm,cortex-a8";
  22. };
  23. };
  24. pmu {
  25. compatible = "arm,cortex-a8-pmu";
  26. interrupts = <3>;
  27. ti,hwmods = "debugss";
  28. };
  29. /*
  30. * The soc node represents the soc top level view. It is uses for IPs
  31. * that are not memory mapped in the MPU view or for the MPU itself.
  32. */
  33. soc {
  34. compatible = "ti,omap-infra";
  35. mpu {
  36. compatible = "ti,omap3-mpu";
  37. ti,hwmods = "mpu";
  38. };
  39. iva {
  40. compatible = "ti,iva2.2";
  41. ti,hwmods = "iva";
  42. dsp {
  43. compatible = "ti,omap3-c64";
  44. };
  45. };
  46. };
  47. /*
  48. * XXX: Use a flat representation of the OMAP3 interconnect.
  49. * The real OMAP interconnect network is quite complex.
  50. * Since that will not bring real advantage to represent that in DT for
  51. * the moment, just use a fake OCP bus entry to represent the whole bus
  52. * hierarchy.
  53. */
  54. ocp {
  55. compatible = "simple-bus";
  56. #address-cells = <1>;
  57. #size-cells = <1>;
  58. ranges;
  59. ti,hwmods = "l3_main";
  60. counter32k: counter@48320000 {
  61. compatible = "ti,omap-counter32k";
  62. reg = <0x48320000 0x20>;
  63. ti,hwmods = "counter_32k";
  64. };
  65. intc: interrupt-controller@48200000 {
  66. compatible = "ti,omap2-intc";
  67. interrupt-controller;
  68. #interrupt-cells = <1>;
  69. ti,intc-size = <96>;
  70. reg = <0x48200000 0x1000>;
  71. };
  72. sdma: dma-controller@48056000 {
  73. compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
  74. reg = <0x48056000 0x1000>;
  75. interrupts = <12>,
  76. <13>,
  77. <14>,
  78. <15>;
  79. #dma-cells = <1>;
  80. #dma-channels = <32>;
  81. #dma-requests = <96>;
  82. };
  83. omap3_pmx_core: pinmux@48002030 {
  84. compatible = "ti,omap3-padconf", "pinctrl-single";
  85. reg = <0x48002030 0x05cc>;
  86. #address-cells = <1>;
  87. #size-cells = <0>;
  88. pinctrl-single,register-width = <16>;
  89. pinctrl-single,function-mask = <0x7fff>;
  90. };
  91. omap3_pmx_wkup: pinmux@0x48002a58 {
  92. compatible = "ti,omap3-padconf", "pinctrl-single";
  93. reg = <0x48002a58 0x5c>;
  94. #address-cells = <1>;
  95. #size-cells = <0>;
  96. pinctrl-single,register-width = <16>;
  97. pinctrl-single,function-mask = <0x7fff>;
  98. };
  99. gpio1: gpio@48310000 {
  100. compatible = "ti,omap3-gpio";
  101. ti,hwmods = "gpio1";
  102. gpio-controller;
  103. #gpio-cells = <2>;
  104. interrupt-controller;
  105. #interrupt-cells = <2>;
  106. };
  107. gpio2: gpio@49050000 {
  108. compatible = "ti,omap3-gpio";
  109. ti,hwmods = "gpio2";
  110. gpio-controller;
  111. #gpio-cells = <2>;
  112. interrupt-controller;
  113. #interrupt-cells = <2>;
  114. };
  115. gpio3: gpio@49052000 {
  116. compatible = "ti,omap3-gpio";
  117. ti,hwmods = "gpio3";
  118. gpio-controller;
  119. #gpio-cells = <2>;
  120. interrupt-controller;
  121. #interrupt-cells = <2>;
  122. };
  123. gpio4: gpio@49054000 {
  124. compatible = "ti,omap3-gpio";
  125. ti,hwmods = "gpio4";
  126. gpio-controller;
  127. #gpio-cells = <2>;
  128. interrupt-controller;
  129. #interrupt-cells = <2>;
  130. };
  131. gpio5: gpio@49056000 {
  132. compatible = "ti,omap3-gpio";
  133. ti,hwmods = "gpio5";
  134. gpio-controller;
  135. #gpio-cells = <2>;
  136. interrupt-controller;
  137. #interrupt-cells = <2>;
  138. };
  139. gpio6: gpio@49058000 {
  140. compatible = "ti,omap3-gpio";
  141. ti,hwmods = "gpio6";
  142. gpio-controller;
  143. #gpio-cells = <2>;
  144. interrupt-controller;
  145. #interrupt-cells = <2>;
  146. };
  147. uart1: serial@4806a000 {
  148. compatible = "ti,omap3-uart";
  149. ti,hwmods = "uart1";
  150. clock-frequency = <48000000>;
  151. };
  152. uart2: serial@4806c000 {
  153. compatible = "ti,omap3-uart";
  154. ti,hwmods = "uart2";
  155. clock-frequency = <48000000>;
  156. };
  157. uart3: serial@49020000 {
  158. compatible = "ti,omap3-uart";
  159. ti,hwmods = "uart3";
  160. clock-frequency = <48000000>;
  161. };
  162. i2c1: i2c@48070000 {
  163. compatible = "ti,omap3-i2c";
  164. #address-cells = <1>;
  165. #size-cells = <0>;
  166. ti,hwmods = "i2c1";
  167. };
  168. i2c2: i2c@48072000 {
  169. compatible = "ti,omap3-i2c";
  170. #address-cells = <1>;
  171. #size-cells = <0>;
  172. ti,hwmods = "i2c2";
  173. };
  174. i2c3: i2c@48060000 {
  175. compatible = "ti,omap3-i2c";
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. ti,hwmods = "i2c3";
  179. };
  180. mcspi1: spi@48098000 {
  181. compatible = "ti,omap2-mcspi";
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. ti,hwmods = "mcspi1";
  185. ti,spi-num-cs = <4>;
  186. dmas = <&sdma 35>,
  187. <&sdma 36>,
  188. <&sdma 37>,
  189. <&sdma 38>,
  190. <&sdma 39>,
  191. <&sdma 40>,
  192. <&sdma 41>,
  193. <&sdma 42>;
  194. dma-names = "tx0", "rx0", "tx1", "rx1",
  195. "tx2", "rx2", "tx3", "rx3";
  196. };
  197. mcspi2: spi@4809a000 {
  198. compatible = "ti,omap2-mcspi";
  199. #address-cells = <1>;
  200. #size-cells = <0>;
  201. ti,hwmods = "mcspi2";
  202. ti,spi-num-cs = <2>;
  203. dmas = <&sdma 43>,
  204. <&sdma 44>,
  205. <&sdma 45>,
  206. <&sdma 46>;
  207. dma-names = "tx0", "rx0", "tx1", "rx1";
  208. };
  209. mcspi3: spi@480b8000 {
  210. compatible = "ti,omap2-mcspi";
  211. #address-cells = <1>;
  212. #size-cells = <0>;
  213. ti,hwmods = "mcspi3";
  214. ti,spi-num-cs = <2>;
  215. dmas = <&sdma 15>,
  216. <&sdma 16>,
  217. <&sdma 23>,
  218. <&sdma 24>;
  219. dma-names = "tx0", "rx0", "tx1", "rx1";
  220. };
  221. mcspi4: spi@480ba000 {
  222. compatible = "ti,omap2-mcspi";
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. ti,hwmods = "mcspi4";
  226. ti,spi-num-cs = <1>;
  227. dmas = <&sdma 70>, <&sdma 71>;
  228. dma-names = "tx0", "rx0";
  229. };
  230. mmc1: mmc@4809c000 {
  231. compatible = "ti,omap3-hsmmc";
  232. ti,hwmods = "mmc1";
  233. ti,dual-volt;
  234. dmas = <&sdma 61>, <&sdma 62>;
  235. dma-names = "tx", "rx";
  236. };
  237. mmc2: mmc@480b4000 {
  238. compatible = "ti,omap3-hsmmc";
  239. ti,hwmods = "mmc2";
  240. dmas = <&sdma 47>, <&sdma 48>;
  241. dma-names = "tx", "rx";
  242. };
  243. mmc3: mmc@480ad000 {
  244. compatible = "ti,omap3-hsmmc";
  245. ti,hwmods = "mmc3";
  246. dmas = <&sdma 77>, <&sdma 78>;
  247. dma-names = "tx", "rx";
  248. };
  249. wdt2: wdt@48314000 {
  250. compatible = "ti,omap3-wdt";
  251. ti,hwmods = "wd_timer2";
  252. };
  253. mcbsp1: mcbsp@48074000 {
  254. compatible = "ti,omap3-mcbsp";
  255. reg = <0x48074000 0xff>;
  256. reg-names = "mpu";
  257. interrupts = <16>, /* OCP compliant interrupt */
  258. <59>, /* TX interrupt */
  259. <60>; /* RX interrupt */
  260. interrupt-names = "common", "tx", "rx";
  261. ti,buffer-size = <128>;
  262. ti,hwmods = "mcbsp1";
  263. };
  264. mcbsp2: mcbsp@49022000 {
  265. compatible = "ti,omap3-mcbsp";
  266. reg = <0x49022000 0xff>,
  267. <0x49028000 0xff>;
  268. reg-names = "mpu", "sidetone";
  269. interrupts = <17>, /* OCP compliant interrupt */
  270. <62>, /* TX interrupt */
  271. <63>, /* RX interrupt */
  272. <4>; /* Sidetone */
  273. interrupt-names = "common", "tx", "rx", "sidetone";
  274. ti,buffer-size = <1280>;
  275. ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
  276. };
  277. mcbsp3: mcbsp@49024000 {
  278. compatible = "ti,omap3-mcbsp";
  279. reg = <0x49024000 0xff>,
  280. <0x4902a000 0xff>;
  281. reg-names = "mpu", "sidetone";
  282. interrupts = <22>, /* OCP compliant interrupt */
  283. <89>, /* TX interrupt */
  284. <90>, /* RX interrupt */
  285. <5>; /* Sidetone */
  286. interrupt-names = "common", "tx", "rx", "sidetone";
  287. ti,buffer-size = <128>;
  288. ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
  289. };
  290. mcbsp4: mcbsp@49026000 {
  291. compatible = "ti,omap3-mcbsp";
  292. reg = <0x49026000 0xff>;
  293. reg-names = "mpu";
  294. interrupts = <23>, /* OCP compliant interrupt */
  295. <54>, /* TX interrupt */
  296. <55>; /* RX interrupt */
  297. interrupt-names = "common", "tx", "rx";
  298. ti,buffer-size = <128>;
  299. ti,hwmods = "mcbsp4";
  300. };
  301. mcbsp5: mcbsp@48096000 {
  302. compatible = "ti,omap3-mcbsp";
  303. reg = <0x48096000 0xff>;
  304. reg-names = "mpu";
  305. interrupts = <27>, /* OCP compliant interrupt */
  306. <81>, /* TX interrupt */
  307. <82>; /* RX interrupt */
  308. interrupt-names = "common", "tx", "rx";
  309. ti,buffer-size = <128>;
  310. ti,hwmods = "mcbsp5";
  311. };
  312. timer1: timer@48318000 {
  313. compatible = "ti,omap2-timer";
  314. reg = <0x48318000 0x400>;
  315. interrupts = <37>;
  316. ti,hwmods = "timer1";
  317. ti,timer-alwon;
  318. };
  319. timer2: timer@49032000 {
  320. compatible = "ti,omap2-timer";
  321. reg = <0x49032000 0x400>;
  322. interrupts = <38>;
  323. ti,hwmods = "timer2";
  324. };
  325. timer3: timer@49034000 {
  326. compatible = "ti,omap2-timer";
  327. reg = <0x49034000 0x400>;
  328. interrupts = <39>;
  329. ti,hwmods = "timer3";
  330. };
  331. timer4: timer@49036000 {
  332. compatible = "ti,omap2-timer";
  333. reg = <0x49036000 0x400>;
  334. interrupts = <40>;
  335. ti,hwmods = "timer4";
  336. };
  337. timer5: timer@49038000 {
  338. compatible = "ti,omap2-timer";
  339. reg = <0x49038000 0x400>;
  340. interrupts = <41>;
  341. ti,hwmods = "timer5";
  342. ti,timer-dsp;
  343. };
  344. timer6: timer@4903a000 {
  345. compatible = "ti,omap2-timer";
  346. reg = <0x4903a000 0x400>;
  347. interrupts = <42>;
  348. ti,hwmods = "timer6";
  349. ti,timer-dsp;
  350. };
  351. timer7: timer@4903c000 {
  352. compatible = "ti,omap2-timer";
  353. reg = <0x4903c000 0x400>;
  354. interrupts = <43>;
  355. ti,hwmods = "timer7";
  356. ti,timer-dsp;
  357. };
  358. timer8: timer@4903e000 {
  359. compatible = "ti,omap2-timer";
  360. reg = <0x4903e000 0x400>;
  361. interrupts = <44>;
  362. ti,hwmods = "timer8";
  363. ti,timer-pwm;
  364. ti,timer-dsp;
  365. };
  366. timer9: timer@49040000 {
  367. compatible = "ti,omap2-timer";
  368. reg = <0x49040000 0x400>;
  369. interrupts = <45>;
  370. ti,hwmods = "timer9";
  371. ti,timer-pwm;
  372. };
  373. timer10: timer@48086000 {
  374. compatible = "ti,omap2-timer";
  375. reg = <0x48086000 0x400>;
  376. interrupts = <46>;
  377. ti,hwmods = "timer10";
  378. ti,timer-pwm;
  379. };
  380. timer11: timer@48088000 {
  381. compatible = "ti,omap2-timer";
  382. reg = <0x48088000 0x400>;
  383. interrupts = <47>;
  384. ti,hwmods = "timer11";
  385. ti,timer-pwm;
  386. };
  387. timer12: timer@48304000 {
  388. compatible = "ti,omap2-timer";
  389. reg = <0x48304000 0x400>;
  390. interrupts = <95>;
  391. ti,hwmods = "timer12";
  392. ti,timer-alwon;
  393. ti,timer-secure;
  394. };
  395. usbhstll: usbhstll@48062000 {
  396. compatible = "ti,usbhs-tll";
  397. reg = <0x48062000 0x1000>;
  398. interrupts = <78>;
  399. ti,hwmods = "usb_tll_hs";
  400. };
  401. usbhshost: usbhshost@48064000 {
  402. compatible = "ti,usbhs-host";
  403. reg = <0x48064000 0x400>;
  404. ti,hwmods = "usb_host_hs";
  405. #address-cells = <1>;
  406. #size-cells = <1>;
  407. ranges;
  408. usbhsohci: ohci@48064400 {
  409. compatible = "ti,ohci-omap3", "usb-ohci";
  410. reg = <0x48064400 0x400>;
  411. interrupt-parent = <&intc>;
  412. interrupts = <76>;
  413. };
  414. usbhsehci: ehci@48064800 {
  415. compatible = "ti,ehci-omap", "usb-ehci";
  416. reg = <0x48064800 0x400>;
  417. interrupt-parent = <&intc>;
  418. interrupts = <77>;
  419. };
  420. };
  421. gpmc: gpmc@6e000000 {
  422. compatible = "ti,omap3430-gpmc";
  423. ti,hwmods = "gpmc";
  424. reg = <0x6e000000 0x02d0>;
  425. interrupts = <20>;
  426. gpmc,num-cs = <8>;
  427. gpmc,num-waitpins = <4>;
  428. #address-cells = <2>;
  429. #size-cells = <1>;
  430. };
  431. usb_otg_hs: usb_otg_hs@480ab000 {
  432. compatible = "ti,omap3-musb";
  433. reg = <0x480ab000 0x1000>;
  434. interrupts = <0 92 0x4>, <0 93 0x4>;
  435. interrupt-names = "mc", "dma";
  436. ti,hwmods = "usb_otg_hs";
  437. usb-phy = <&usb2_phy>;
  438. multipoint = <1>;
  439. num-eps = <16>;
  440. ram-bits = <12>;
  441. };
  442. };
  443. };