mt9t112.c 27 KB

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  1. /*
  2. * mt9t112 Camera Driver
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on ov772x driver, mt9m111 driver,
  8. *
  9. * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
  10. * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
  11. * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  12. * Copyright (C) 2008 Magnus Damm
  13. * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License version 2 as
  17. * published by the Free Software Foundation.
  18. */
  19. #include <linux/delay.h>
  20. #include <linux/i2c.h>
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/slab.h>
  24. #include <linux/videodev2.h>
  25. #include <media/mt9t112.h>
  26. #include <media/soc_camera.h>
  27. #include <media/soc_mediabus.h>
  28. #include <media/v4l2-chip-ident.h>
  29. #include <media/v4l2-common.h>
  30. /* you can check PLL/clock info */
  31. /* #define EXT_CLOCK 24000000 */
  32. /************************************************************************
  33. macro
  34. ************************************************************************/
  35. /*
  36. * frame size
  37. */
  38. #define MAX_WIDTH 2048
  39. #define MAX_HEIGHT 1536
  40. #define VGA_WIDTH 640
  41. #define VGA_HEIGHT 480
  42. /*
  43. * macro of read/write
  44. */
  45. #define ECHECKER(ret, x) \
  46. do { \
  47. (ret) = (x); \
  48. if ((ret) < 0) \
  49. return (ret); \
  50. } while (0)
  51. #define mt9t112_reg_write(ret, client, a, b) \
  52. ECHECKER(ret, __mt9t112_reg_write(client, a, b))
  53. #define mt9t112_mcu_write(ret, client, a, b) \
  54. ECHECKER(ret, __mt9t112_mcu_write(client, a, b))
  55. #define mt9t112_reg_mask_set(ret, client, a, b, c) \
  56. ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c))
  57. #define mt9t112_mcu_mask_set(ret, client, a, b, c) \
  58. ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c))
  59. #define mt9t112_reg_read(ret, client, a) \
  60. ECHECKER(ret, __mt9t112_reg_read(client, a))
  61. /*
  62. * Logical address
  63. */
  64. #define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff))
  65. #define VAR(id, offset) _VAR(id, offset, 0x0000)
  66. #define VAR8(id, offset) _VAR(id, offset, 0x8000)
  67. /************************************************************************
  68. struct
  69. ************************************************************************/
  70. struct mt9t112_frame_size {
  71. u16 width;
  72. u16 height;
  73. };
  74. struct mt9t112_format {
  75. enum v4l2_mbus_pixelcode code;
  76. enum v4l2_colorspace colorspace;
  77. u16 fmt;
  78. u16 order;
  79. };
  80. struct mt9t112_priv {
  81. struct v4l2_subdev subdev;
  82. struct mt9t112_camera_info *info;
  83. struct i2c_client *client;
  84. struct soc_camera_device icd;
  85. struct mt9t112_frame_size frame;
  86. const struct mt9t112_format *format;
  87. int model;
  88. u32 flags;
  89. /* for flags */
  90. #define INIT_DONE (1 << 0)
  91. #define PCLK_RISING (1 << 1)
  92. };
  93. /************************************************************************
  94. supported format
  95. ************************************************************************/
  96. static const struct mt9t112_format mt9t112_cfmts[] = {
  97. {
  98. .code = V4L2_MBUS_FMT_UYVY8_2X8,
  99. .colorspace = V4L2_COLORSPACE_JPEG,
  100. .fmt = 1,
  101. .order = 0,
  102. }, {
  103. .code = V4L2_MBUS_FMT_VYUY8_2X8,
  104. .colorspace = V4L2_COLORSPACE_JPEG,
  105. .fmt = 1,
  106. .order = 1,
  107. }, {
  108. .code = V4L2_MBUS_FMT_YUYV8_2X8,
  109. .colorspace = V4L2_COLORSPACE_JPEG,
  110. .fmt = 1,
  111. .order = 2,
  112. }, {
  113. .code = V4L2_MBUS_FMT_YVYU8_2X8,
  114. .colorspace = V4L2_COLORSPACE_JPEG,
  115. .fmt = 1,
  116. .order = 3,
  117. }, {
  118. .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
  119. .colorspace = V4L2_COLORSPACE_SRGB,
  120. .fmt = 8,
  121. .order = 2,
  122. }, {
  123. .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
  124. .colorspace = V4L2_COLORSPACE_SRGB,
  125. .fmt = 4,
  126. .order = 2,
  127. },
  128. };
  129. /************************************************************************
  130. general function
  131. ************************************************************************/
  132. static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client)
  133. {
  134. return container_of(i2c_get_clientdata(client),
  135. struct mt9t112_priv,
  136. subdev);
  137. }
  138. static int __mt9t112_reg_read(const struct i2c_client *client, u16 command)
  139. {
  140. struct i2c_msg msg[2];
  141. u8 buf[2];
  142. int ret;
  143. command = swab16(command);
  144. msg[0].addr = client->addr;
  145. msg[0].flags = 0;
  146. msg[0].len = 2;
  147. msg[0].buf = (u8 *)&command;
  148. msg[1].addr = client->addr;
  149. msg[1].flags = I2C_M_RD;
  150. msg[1].len = 2;
  151. msg[1].buf = buf;
  152. /*
  153. * if return value of this function is < 0,
  154. * it mean error.
  155. * else, under 16bit is valid data.
  156. */
  157. ret = i2c_transfer(client->adapter, msg, 2);
  158. if (ret < 0)
  159. return ret;
  160. memcpy(&ret, buf, 2);
  161. return swab16(ret);
  162. }
  163. static int __mt9t112_reg_write(const struct i2c_client *client,
  164. u16 command, u16 data)
  165. {
  166. struct i2c_msg msg;
  167. u8 buf[4];
  168. int ret;
  169. command = swab16(command);
  170. data = swab16(data);
  171. memcpy(buf + 0, &command, 2);
  172. memcpy(buf + 2, &data, 2);
  173. msg.addr = client->addr;
  174. msg.flags = 0;
  175. msg.len = 4;
  176. msg.buf = buf;
  177. /*
  178. * i2c_transfer return message length,
  179. * but this function should return 0 if correct case
  180. */
  181. ret = i2c_transfer(client->adapter, &msg, 1);
  182. if (ret >= 0)
  183. ret = 0;
  184. return ret;
  185. }
  186. static int __mt9t112_reg_mask_set(const struct i2c_client *client,
  187. u16 command,
  188. u16 mask,
  189. u16 set)
  190. {
  191. int val = __mt9t112_reg_read(client, command);
  192. if (val < 0)
  193. return val;
  194. val &= ~mask;
  195. val |= set & mask;
  196. return __mt9t112_reg_write(client, command, val);
  197. }
  198. /* mcu access */
  199. static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command)
  200. {
  201. int ret;
  202. ret = __mt9t112_reg_write(client, 0x098E, command);
  203. if (ret < 0)
  204. return ret;
  205. return __mt9t112_reg_read(client, 0x0990);
  206. }
  207. static int __mt9t112_mcu_write(const struct i2c_client *client,
  208. u16 command, u16 data)
  209. {
  210. int ret;
  211. ret = __mt9t112_reg_write(client, 0x098E, command);
  212. if (ret < 0)
  213. return ret;
  214. return __mt9t112_reg_write(client, 0x0990, data);
  215. }
  216. static int __mt9t112_mcu_mask_set(const struct i2c_client *client,
  217. u16 command,
  218. u16 mask,
  219. u16 set)
  220. {
  221. int val = __mt9t112_mcu_read(client, command);
  222. if (val < 0)
  223. return val;
  224. val &= ~mask;
  225. val |= set & mask;
  226. return __mt9t112_mcu_write(client, command, val);
  227. }
  228. static int mt9t112_reset(const struct i2c_client *client)
  229. {
  230. int ret;
  231. mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001);
  232. msleep(1);
  233. mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000);
  234. return ret;
  235. }
  236. #ifndef EXT_CLOCK
  237. #define CLOCK_INFO(a, b)
  238. #else
  239. #define CLOCK_INFO(a, b) mt9t112_clock_info(a, b)
  240. static int mt9t112_clock_info(const struct i2c_client *client, u32 ext)
  241. {
  242. int m, n, p1, p2, p3, p4, p5, p6, p7;
  243. u32 vco, clk;
  244. char *enable;
  245. ext /= 1000; /* kbyte order */
  246. mt9t112_reg_read(n, client, 0x0012);
  247. p1 = n & 0x000f;
  248. n = n >> 4;
  249. p2 = n & 0x000f;
  250. n = n >> 4;
  251. p3 = n & 0x000f;
  252. mt9t112_reg_read(n, client, 0x002a);
  253. p4 = n & 0x000f;
  254. n = n >> 4;
  255. p5 = n & 0x000f;
  256. n = n >> 4;
  257. p6 = n & 0x000f;
  258. mt9t112_reg_read(n, client, 0x002c);
  259. p7 = n & 0x000f;
  260. mt9t112_reg_read(n, client, 0x0010);
  261. m = n & 0x00ff;
  262. n = (n >> 8) & 0x003f;
  263. enable = ((6000 > ext) || (54000 < ext)) ? "X" : "";
  264. dev_info(&client->dev, "EXTCLK : %10u K %s\n", ext, enable);
  265. vco = 2 * m * ext / (n+1);
  266. enable = ((384000 > vco) || (768000 < vco)) ? "X" : "";
  267. dev_info(&client->dev, "VCO : %10u K %s\n", vco, enable);
  268. clk = vco / (p1+1) / (p2+1);
  269. enable = (96000 < clk) ? "X" : "";
  270. dev_info(&client->dev, "PIXCLK : %10u K %s\n", clk, enable);
  271. clk = vco / (p3+1);
  272. enable = (768000 < clk) ? "X" : "";
  273. dev_info(&client->dev, "MIPICLK : %10u K %s\n", clk, enable);
  274. clk = vco / (p6+1);
  275. enable = (96000 < clk) ? "X" : "";
  276. dev_info(&client->dev, "MCU CLK : %10u K %s\n", clk, enable);
  277. clk = vco / (p5+1);
  278. enable = (54000 < clk) ? "X" : "";
  279. dev_info(&client->dev, "SOC CLK : %10u K %s\n", clk, enable);
  280. clk = vco / (p4+1);
  281. enable = (70000 < clk) ? "X" : "";
  282. dev_info(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable);
  283. clk = vco / (p7+1);
  284. dev_info(&client->dev, "External sensor : %10u K\n", clk);
  285. clk = ext / (n+1);
  286. enable = ((2000 > clk) || (24000 < clk)) ? "X" : "";
  287. dev_info(&client->dev, "PFD : %10u K %s\n", clk, enable);
  288. return 0;
  289. }
  290. #endif
  291. static void mt9t112_frame_check(u32 *width, u32 *height)
  292. {
  293. if (*width > MAX_WIDTH)
  294. *width = MAX_WIDTH;
  295. if (*height > MAX_HEIGHT)
  296. *height = MAX_HEIGHT;
  297. }
  298. static int mt9t112_set_a_frame_size(const struct i2c_client *client,
  299. u16 width,
  300. u16 height)
  301. {
  302. int ret;
  303. u16 wstart = (MAX_WIDTH - width) / 2;
  304. u16 hstart = (MAX_HEIGHT - height) / 2;
  305. /* (Context A) Image Width/Height */
  306. mt9t112_mcu_write(ret, client, VAR(26, 0), width);
  307. mt9t112_mcu_write(ret, client, VAR(26, 2), height);
  308. /* (Context A) Output Width/Height */
  309. mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width);
  310. mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height);
  311. /* (Context A) Start Row/Column */
  312. mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart);
  313. mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart);
  314. /* (Context A) End Row/Column */
  315. mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart);
  316. mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart);
  317. mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
  318. return ret;
  319. }
  320. static int mt9t112_set_pll_dividers(const struct i2c_client *client,
  321. u8 m, u8 n,
  322. u8 p1, u8 p2, u8 p3,
  323. u8 p4, u8 p5, u8 p6,
  324. u8 p7)
  325. {
  326. int ret;
  327. u16 val;
  328. /* N/M */
  329. val = (n << 8) |
  330. (m << 0);
  331. mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val);
  332. /* P1/P2/P3 */
  333. val = ((p3 & 0x0F) << 8) |
  334. ((p2 & 0x0F) << 4) |
  335. ((p1 & 0x0F) << 0);
  336. mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val);
  337. /* P4/P5/P6 */
  338. val = (0x7 << 12) |
  339. ((p6 & 0x0F) << 8) |
  340. ((p5 & 0x0F) << 4) |
  341. ((p4 & 0x0F) << 0);
  342. mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val);
  343. /* P7 */
  344. val = (0x1 << 12) |
  345. ((p7 & 0x0F) << 0);
  346. mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val);
  347. return ret;
  348. }
  349. static int mt9t112_init_pll(const struct i2c_client *client)
  350. {
  351. struct mt9t112_priv *priv = to_mt9t112(client);
  352. int data, i, ret;
  353. mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001);
  354. /* PLL control: BYPASS PLL = 8517 */
  355. mt9t112_reg_write(ret, client, 0x0014, 0x2145);
  356. /* Replace these registers when new timing parameters are generated */
  357. mt9t112_set_pll_dividers(client,
  358. priv->info->divider.m,
  359. priv->info->divider.n,
  360. priv->info->divider.p1,
  361. priv->info->divider.p2,
  362. priv->info->divider.p3,
  363. priv->info->divider.p4,
  364. priv->info->divider.p5,
  365. priv->info->divider.p6,
  366. priv->info->divider.p7);
  367. /*
  368. * TEST_BYPASS on
  369. * PLL_ENABLE on
  370. * SEL_LOCK_DET on
  371. * TEST_BYPASS off
  372. */
  373. mt9t112_reg_write(ret, client, 0x0014, 0x2525);
  374. mt9t112_reg_write(ret, client, 0x0014, 0x2527);
  375. mt9t112_reg_write(ret, client, 0x0014, 0x3427);
  376. mt9t112_reg_write(ret, client, 0x0014, 0x3027);
  377. mdelay(10);
  378. /*
  379. * PLL_BYPASS off
  380. * Reference clock count
  381. * I2C Master Clock Divider
  382. */
  383. mt9t112_reg_write(ret, client, 0x0014, 0x3046);
  384. mt9t112_reg_write(ret, client, 0x0022, 0x0190);
  385. mt9t112_reg_write(ret, client, 0x3B84, 0x0212);
  386. /* External sensor clock is PLL bypass */
  387. mt9t112_reg_write(ret, client, 0x002E, 0x0500);
  388. mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002);
  389. mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004);
  390. /* MCU disabled */
  391. mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004);
  392. /* out of standby */
  393. mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0);
  394. mdelay(50);
  395. /*
  396. * Standby Workaround
  397. * Disable Secondary I2C Pads
  398. */
  399. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  400. mdelay(1);
  401. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  402. mdelay(1);
  403. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  404. mdelay(1);
  405. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  406. mdelay(1);
  407. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  408. mdelay(1);
  409. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  410. mdelay(1);
  411. /* poll to verify out of standby. Must Poll this bit */
  412. for (i = 0; i < 100; i++) {
  413. mt9t112_reg_read(data, client, 0x0018);
  414. if (!(0x4000 & data))
  415. break;
  416. mdelay(10);
  417. }
  418. return ret;
  419. }
  420. static int mt9t112_init_setting(const struct i2c_client *client)
  421. {
  422. int ret;
  423. /* Adaptive Output Clock (A) */
  424. mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000);
  425. /* Read Mode (A) */
  426. mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024);
  427. /* Fine Correction (A) */
  428. mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC);
  429. /* Fine IT Min (A) */
  430. mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1);
  431. /* Fine IT Max Margin (A) */
  432. mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF);
  433. /* Base Frame Lines (A) */
  434. mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D);
  435. /* Min Line Length (A) */
  436. mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a);
  437. /* Line Length (A) */
  438. mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0);
  439. /* Adaptive Output Clock (B) */
  440. mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000);
  441. /* Row Start (B) */
  442. mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004);
  443. /* Column Start (B) */
  444. mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004);
  445. /* Row End (B) */
  446. mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B);
  447. /* Column End (B) */
  448. mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B);
  449. /* Fine Correction (B) */
  450. mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C);
  451. /* Fine IT Min (B) */
  452. mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1);
  453. /* Fine IT Max Margin (B) */
  454. mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF);
  455. /* Base Frame Lines (B) */
  456. mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668);
  457. /* Min Line Length (B) */
  458. mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0);
  459. /* Line Length (B) */
  460. mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0);
  461. /*
  462. * Flicker Dectection registers
  463. * This section should be replaced whenever new Timing file is generated
  464. * All the following registers need to be replaced
  465. * Following registers are generated from Register Wizard but user can
  466. * modify them. For detail see auto flicker detection tuning
  467. */
  468. /* FD_FDPERIOD_SELECT */
  469. mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01);
  470. /* PRI_B_CONFIG_FD_ALGO_RUN */
  471. mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003);
  472. /* PRI_A_CONFIG_FD_ALGO_RUN */
  473. mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003);
  474. /*
  475. * AFD range detection tuning registers
  476. */
  477. /* search_f1_50 */
  478. mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25);
  479. /* search_f2_50 */
  480. mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28);
  481. /* search_f1_60 */
  482. mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C);
  483. /* search_f2_60 */
  484. mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F);
  485. /* period_50Hz (A) */
  486. mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA);
  487. /* secret register by aptina */
  488. /* period_50Hz (A MSB) */
  489. mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00);
  490. /* period_60Hz (A) */
  491. mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B);
  492. /* secret register by aptina */
  493. /* period_60Hz (A MSB) */
  494. mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00);
  495. /* period_50Hz (B) */
  496. mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82);
  497. /* secret register by aptina */
  498. /* period_50Hz (B) MSB */
  499. mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00);
  500. /* period_60Hz (B) */
  501. mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D);
  502. /* secret register by aptina */
  503. /* period_60Hz (B) MSB */
  504. mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00);
  505. /* FD Mode */
  506. mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10);
  507. /* Stat_min */
  508. mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02);
  509. /* Stat_max */
  510. mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03);
  511. /* Min_amplitude */
  512. mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A);
  513. /* RX FIFO Watermark (A) */
  514. mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014);
  515. /* RX FIFO Watermark (B) */
  516. mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014);
  517. /* MCLK: 16MHz
  518. * PCLK: 73MHz
  519. * CorePixCLK: 36.5 MHz
  520. */
  521. mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133);
  522. mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110);
  523. mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130);
  524. mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108);
  525. mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27);
  526. mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30);
  527. mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32);
  528. mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35);
  529. return ret;
  530. }
  531. static int mt9t112_auto_focus_setting(const struct i2c_client *client)
  532. {
  533. int ret;
  534. mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F);
  535. mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F);
  536. mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
  537. mt9t112_reg_write(ret, client, 0x0614, 0x0000);
  538. mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
  539. mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02);
  540. mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002);
  541. mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001);
  542. mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025);
  543. mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193);
  544. mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18);
  545. mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
  546. return ret;
  547. }
  548. static int mt9t112_auto_focus_trigger(const struct i2c_client *client)
  549. {
  550. int ret;
  551. mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01);
  552. return ret;
  553. }
  554. static int mt9t112_init_camera(const struct i2c_client *client)
  555. {
  556. int ret;
  557. ECHECKER(ret, mt9t112_reset(client));
  558. ECHECKER(ret, mt9t112_init_pll(client));
  559. ECHECKER(ret, mt9t112_init_setting(client));
  560. ECHECKER(ret, mt9t112_auto_focus_setting(client));
  561. mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0);
  562. /* Analog setting B */
  563. mt9t112_reg_write(ret, client, 0x3084, 0x2409);
  564. mt9t112_reg_write(ret, client, 0x3092, 0x0A49);
  565. mt9t112_reg_write(ret, client, 0x3094, 0x4949);
  566. mt9t112_reg_write(ret, client, 0x3096, 0x4950);
  567. /*
  568. * Disable adaptive clock
  569. * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR
  570. * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
  571. */
  572. mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E);
  573. mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E);
  574. /* Configure STatus in Status_before_length Format and enable header */
  575. /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
  576. mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4);
  577. /* Enable JPEG in context B */
  578. /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
  579. mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01);
  580. /* Disable Dac_TXLO */
  581. mt9t112_reg_write(ret, client, 0x316C, 0x350F);
  582. /* Set max slew rates */
  583. mt9t112_reg_write(ret, client, 0x1E, 0x777);
  584. return ret;
  585. }
  586. /************************************************************************
  587. v4l2_subdev_core_ops
  588. ************************************************************************/
  589. static int mt9t112_g_chip_ident(struct v4l2_subdev *sd,
  590. struct v4l2_dbg_chip_ident *id)
  591. {
  592. struct i2c_client *client = v4l2_get_subdevdata(sd);
  593. struct mt9t112_priv *priv = to_mt9t112(client);
  594. id->ident = priv->model;
  595. id->revision = 0;
  596. return 0;
  597. }
  598. #ifdef CONFIG_VIDEO_ADV_DEBUG
  599. static int mt9t112_g_register(struct v4l2_subdev *sd,
  600. struct v4l2_dbg_register *reg)
  601. {
  602. struct i2c_client *client = v4l2_get_subdevdata(sd);
  603. int ret;
  604. reg->size = 2;
  605. mt9t112_reg_read(ret, client, reg->reg);
  606. reg->val = (__u64)ret;
  607. return 0;
  608. }
  609. static int mt9t112_s_register(struct v4l2_subdev *sd,
  610. struct v4l2_dbg_register *reg)
  611. {
  612. struct i2c_client *client = v4l2_get_subdevdata(sd);
  613. int ret;
  614. mt9t112_reg_write(ret, client, reg->reg, reg->val);
  615. return ret;
  616. }
  617. #endif
  618. static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = {
  619. .g_chip_ident = mt9t112_g_chip_ident,
  620. #ifdef CONFIG_VIDEO_ADV_DEBUG
  621. .g_register = mt9t112_g_register,
  622. .s_register = mt9t112_s_register,
  623. #endif
  624. };
  625. /************************************************************************
  626. v4l2_subdev_video_ops
  627. ************************************************************************/
  628. static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable)
  629. {
  630. struct i2c_client *client = v4l2_get_subdevdata(sd);
  631. struct mt9t112_priv *priv = to_mt9t112(client);
  632. int ret = 0;
  633. if (!enable) {
  634. /* FIXME
  635. *
  636. * If user selected large output size,
  637. * and used it long time,
  638. * mt9t112 camera will be very warm.
  639. *
  640. * But current driver can not stop mt9t112 camera.
  641. * So, set small size here to solve this problem.
  642. */
  643. mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT);
  644. return ret;
  645. }
  646. if (!(priv->flags & INIT_DONE)) {
  647. u16 param = PCLK_RISING & priv->flags ? 0x0001 : 0x0000;
  648. ECHECKER(ret, mt9t112_init_camera(client));
  649. /* Invert PCLK (Data sampled on falling edge of pixclk) */
  650. mt9t112_reg_write(ret, client, 0x3C20, param);
  651. mdelay(5);
  652. priv->flags |= INIT_DONE;
  653. }
  654. mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt);
  655. mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order);
  656. mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
  657. mt9t112_set_a_frame_size(client,
  658. priv->frame.width,
  659. priv->frame.height);
  660. ECHECKER(ret, mt9t112_auto_focus_trigger(client));
  661. dev_dbg(&client->dev, "format : %d\n", priv->format->code);
  662. dev_dbg(&client->dev, "size : %d x %d\n",
  663. priv->frame.width,
  664. priv->frame.height);
  665. CLOCK_INFO(client, EXT_CLOCK);
  666. return ret;
  667. }
  668. static int mt9t112_set_params(struct i2c_client *client, u32 width, u32 height,
  669. enum v4l2_mbus_pixelcode code)
  670. {
  671. struct mt9t112_priv *priv = to_mt9t112(client);
  672. int i;
  673. priv->format = NULL;
  674. /*
  675. * frame size check
  676. */
  677. mt9t112_frame_check(&width, &height);
  678. /*
  679. * get color format
  680. */
  681. for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++)
  682. if (mt9t112_cfmts[i].code == code)
  683. break;
  684. if (i == ARRAY_SIZE(mt9t112_cfmts))
  685. return -EINVAL;
  686. priv->frame.width = (u16)width;
  687. priv->frame.height = (u16)height;
  688. priv->format = mt9t112_cfmts + i;
  689. return 0;
  690. }
  691. static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
  692. {
  693. a->bounds.left = 0;
  694. a->bounds.top = 0;
  695. a->bounds.width = VGA_WIDTH;
  696. a->bounds.height = VGA_HEIGHT;
  697. a->defrect = a->bounds;
  698. a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  699. a->pixelaspect.numerator = 1;
  700. a->pixelaspect.denominator = 1;
  701. return 0;
  702. }
  703. static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
  704. {
  705. a->c.left = 0;
  706. a->c.top = 0;
  707. a->c.width = VGA_WIDTH;
  708. a->c.height = VGA_HEIGHT;
  709. a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  710. return 0;
  711. }
  712. static int mt9t112_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
  713. {
  714. struct i2c_client *client = v4l2_get_subdevdata(sd);
  715. struct v4l2_rect *rect = &a->c;
  716. return mt9t112_set_params(client, rect->width, rect->height,
  717. V4L2_MBUS_FMT_UYVY8_2X8);
  718. }
  719. static int mt9t112_g_fmt(struct v4l2_subdev *sd,
  720. struct v4l2_mbus_framefmt *mf)
  721. {
  722. struct i2c_client *client = v4l2_get_subdevdata(sd);
  723. struct mt9t112_priv *priv = to_mt9t112(client);
  724. if (!priv->format) {
  725. int ret = mt9t112_set_params(client, VGA_WIDTH, VGA_HEIGHT,
  726. V4L2_MBUS_FMT_UYVY8_2X8);
  727. if (ret < 0)
  728. return ret;
  729. }
  730. mf->width = priv->frame.width;
  731. mf->height = priv->frame.height;
  732. /* TODO: set colorspace */
  733. mf->code = priv->format->code;
  734. mf->field = V4L2_FIELD_NONE;
  735. return 0;
  736. }
  737. static int mt9t112_s_fmt(struct v4l2_subdev *sd,
  738. struct v4l2_mbus_framefmt *mf)
  739. {
  740. struct i2c_client *client = v4l2_get_subdevdata(sd);
  741. /* TODO: set colorspace */
  742. return mt9t112_set_params(client, mf->width, mf->height, mf->code);
  743. }
  744. static int mt9t112_try_fmt(struct v4l2_subdev *sd,
  745. struct v4l2_mbus_framefmt *mf)
  746. {
  747. mt9t112_frame_check(&mf->width, &mf->height);
  748. /* TODO: set colorspace */
  749. mf->field = V4L2_FIELD_NONE;
  750. return 0;
  751. }
  752. static int mt9t112_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
  753. enum v4l2_mbus_pixelcode *code)
  754. {
  755. if (index >= ARRAY_SIZE(mt9t112_cfmts))
  756. return -EINVAL;
  757. *code = mt9t112_cfmts[index].code;
  758. return 0;
  759. }
  760. static int mt9t112_g_mbus_config(struct v4l2_subdev *sd,
  761. struct v4l2_mbus_config *cfg)
  762. {
  763. struct i2c_client *client = v4l2_get_subdevdata(sd);
  764. struct soc_camera_device *icd = client->dev.platform_data;
  765. struct soc_camera_link *icl = to_soc_camera_link(icd);
  766. cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
  767. V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_DATA_ACTIVE_HIGH |
  768. V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING;
  769. cfg->type = V4L2_MBUS_PARALLEL;
  770. cfg->flags = soc_camera_apply_board_flags(icl, cfg);
  771. return 0;
  772. }
  773. static int mt9t112_s_mbus_config(struct v4l2_subdev *sd,
  774. const struct v4l2_mbus_config *cfg)
  775. {
  776. struct i2c_client *client = v4l2_get_subdevdata(sd);
  777. struct soc_camera_device *icd = client->dev.platform_data;
  778. struct soc_camera_link *icl = to_soc_camera_link(icd);
  779. struct mt9t112_priv *priv = to_mt9t112(client);
  780. if (soc_camera_apply_board_flags(icl, cfg) & V4L2_MBUS_PCLK_SAMPLE_RISING)
  781. priv->flags |= PCLK_RISING;
  782. return 0;
  783. }
  784. static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = {
  785. .s_stream = mt9t112_s_stream,
  786. .g_mbus_fmt = mt9t112_g_fmt,
  787. .s_mbus_fmt = mt9t112_s_fmt,
  788. .try_mbus_fmt = mt9t112_try_fmt,
  789. .cropcap = mt9t112_cropcap,
  790. .g_crop = mt9t112_g_crop,
  791. .s_crop = mt9t112_s_crop,
  792. .enum_mbus_fmt = mt9t112_enum_fmt,
  793. .g_mbus_config = mt9t112_g_mbus_config,
  794. .s_mbus_config = mt9t112_s_mbus_config,
  795. };
  796. /************************************************************************
  797. i2c driver
  798. ************************************************************************/
  799. static struct v4l2_subdev_ops mt9t112_subdev_ops = {
  800. .core = &mt9t112_subdev_core_ops,
  801. .video = &mt9t112_subdev_video_ops,
  802. };
  803. static int mt9t112_camera_probe(struct soc_camera_device *icd,
  804. struct i2c_client *client)
  805. {
  806. struct mt9t112_priv *priv = to_mt9t112(client);
  807. const char *devname;
  808. int chipid;
  809. /* We must have a parent by now. And it cannot be a wrong one. */
  810. BUG_ON(!icd->parent ||
  811. to_soc_camera_host(icd->parent)->nr != icd->iface);
  812. /*
  813. * check and show chip ID
  814. */
  815. mt9t112_reg_read(chipid, client, 0x0000);
  816. switch (chipid) {
  817. case 0x2680:
  818. devname = "mt9t111";
  819. priv->model = V4L2_IDENT_MT9T111;
  820. break;
  821. case 0x2682:
  822. devname = "mt9t112";
  823. priv->model = V4L2_IDENT_MT9T112;
  824. break;
  825. default:
  826. dev_err(&client->dev, "Product ID error %04x\n", chipid);
  827. return -ENODEV;
  828. }
  829. dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid);
  830. return 0;
  831. }
  832. static int mt9t112_probe(struct i2c_client *client,
  833. const struct i2c_device_id *did)
  834. {
  835. struct mt9t112_priv *priv;
  836. struct soc_camera_device *icd = client->dev.platform_data;
  837. struct soc_camera_link *icl;
  838. int ret;
  839. if (!icd) {
  840. dev_err(&client->dev, "mt9t112: missing soc-camera data!\n");
  841. return -EINVAL;
  842. }
  843. icl = to_soc_camera_link(icd);
  844. if (!icl || !icl->priv)
  845. return -EINVAL;
  846. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  847. if (!priv)
  848. return -ENOMEM;
  849. priv->info = icl->priv;
  850. v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops);
  851. icd->ops = NULL;
  852. ret = mt9t112_camera_probe(icd, client);
  853. if (ret)
  854. kfree(priv);
  855. return ret;
  856. }
  857. static int mt9t112_remove(struct i2c_client *client)
  858. {
  859. struct mt9t112_priv *priv = to_mt9t112(client);
  860. kfree(priv);
  861. return 0;
  862. }
  863. static const struct i2c_device_id mt9t112_id[] = {
  864. { "mt9t112", 0 },
  865. { }
  866. };
  867. MODULE_DEVICE_TABLE(i2c, mt9t112_id);
  868. static struct i2c_driver mt9t112_i2c_driver = {
  869. .driver = {
  870. .name = "mt9t112",
  871. },
  872. .probe = mt9t112_probe,
  873. .remove = mt9t112_remove,
  874. .id_table = mt9t112_id,
  875. };
  876. /************************************************************************
  877. module function
  878. ************************************************************************/
  879. static int __init mt9t112_module_init(void)
  880. {
  881. return i2c_add_driver(&mt9t112_i2c_driver);
  882. }
  883. static void __exit mt9t112_module_exit(void)
  884. {
  885. i2c_del_driver(&mt9t112_i2c_driver);
  886. }
  887. module_init(mt9t112_module_init);
  888. module_exit(mt9t112_module_exit);
  889. MODULE_DESCRIPTION("SoC Camera driver for mt9t112");
  890. MODULE_AUTHOR("Kuninori Morimoto");
  891. MODULE_LICENSE("GPL v2");