cnic.c 146 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #include "cnic_if.h"
  40. #include "bnx2.h"
  41. #include "bnx2x/bnx2x_reg.h"
  42. #include "bnx2x/bnx2x_fw_defs.h"
  43. #include "bnx2x/bnx2x_hsi.h"
  44. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  45. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  46. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  47. #include "cnic.h"
  48. #include "cnic_defs.h"
  49. #define DRV_MODULE_NAME "cnic"
  50. static char version[] __devinitdata =
  51. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  52. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  53. "Chen (zongxi@broadcom.com");
  54. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  55. MODULE_LICENSE("GPL");
  56. MODULE_VERSION(CNIC_MODULE_VERSION);
  57. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  58. static LIST_HEAD(cnic_dev_list);
  59. static LIST_HEAD(cnic_udev_list);
  60. static DEFINE_RWLOCK(cnic_dev_lock);
  61. static DEFINE_MUTEX(cnic_lock);
  62. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  63. /* helper function, assuming cnic_lock is held */
  64. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  65. {
  66. return rcu_dereference_protected(cnic_ulp_tbl[type],
  67. lockdep_is_held(&cnic_lock));
  68. }
  69. static int cnic_service_bnx2(void *, void *);
  70. static int cnic_service_bnx2x(void *, void *);
  71. static int cnic_ctl(void *, struct cnic_ctl_info *);
  72. static struct cnic_ops cnic_bnx2_ops = {
  73. .cnic_owner = THIS_MODULE,
  74. .cnic_handler = cnic_service_bnx2,
  75. .cnic_ctl = cnic_ctl,
  76. };
  77. static struct cnic_ops cnic_bnx2x_ops = {
  78. .cnic_owner = THIS_MODULE,
  79. .cnic_handler = cnic_service_bnx2x,
  80. .cnic_ctl = cnic_ctl,
  81. };
  82. static struct workqueue_struct *cnic_wq;
  83. static void cnic_shutdown_rings(struct cnic_dev *);
  84. static void cnic_init_rings(struct cnic_dev *);
  85. static int cnic_cm_set_pg(struct cnic_sock *);
  86. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  87. {
  88. struct cnic_uio_dev *udev = uinfo->priv;
  89. struct cnic_dev *dev;
  90. if (!capable(CAP_NET_ADMIN))
  91. return -EPERM;
  92. if (udev->uio_dev != -1)
  93. return -EBUSY;
  94. rtnl_lock();
  95. dev = udev->dev;
  96. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  97. rtnl_unlock();
  98. return -ENODEV;
  99. }
  100. udev->uio_dev = iminor(inode);
  101. cnic_shutdown_rings(dev);
  102. cnic_init_rings(dev);
  103. rtnl_unlock();
  104. return 0;
  105. }
  106. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  107. {
  108. struct cnic_uio_dev *udev = uinfo->priv;
  109. udev->uio_dev = -1;
  110. return 0;
  111. }
  112. static inline void cnic_hold(struct cnic_dev *dev)
  113. {
  114. atomic_inc(&dev->ref_count);
  115. }
  116. static inline void cnic_put(struct cnic_dev *dev)
  117. {
  118. atomic_dec(&dev->ref_count);
  119. }
  120. static inline void csk_hold(struct cnic_sock *csk)
  121. {
  122. atomic_inc(&csk->ref_count);
  123. }
  124. static inline void csk_put(struct cnic_sock *csk)
  125. {
  126. atomic_dec(&csk->ref_count);
  127. }
  128. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  129. {
  130. struct cnic_dev *cdev;
  131. read_lock(&cnic_dev_lock);
  132. list_for_each_entry(cdev, &cnic_dev_list, list) {
  133. if (netdev == cdev->netdev) {
  134. cnic_hold(cdev);
  135. read_unlock(&cnic_dev_lock);
  136. return cdev;
  137. }
  138. }
  139. read_unlock(&cnic_dev_lock);
  140. return NULL;
  141. }
  142. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  143. {
  144. atomic_inc(&ulp_ops->ref_count);
  145. }
  146. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  147. {
  148. atomic_dec(&ulp_ops->ref_count);
  149. }
  150. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTX_WR_CMD;
  157. io->cid_addr = cid_addr;
  158. io->offset = off;
  159. io->data = val;
  160. ethdev->drv_ctl(dev->netdev, &info);
  161. }
  162. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  163. {
  164. struct cnic_local *cp = dev->cnic_priv;
  165. struct cnic_eth_dev *ethdev = cp->ethdev;
  166. struct drv_ctl_info info;
  167. struct drv_ctl_io *io = &info.data.io;
  168. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  169. io->offset = off;
  170. io->dma_addr = addr;
  171. ethdev->drv_ctl(dev->netdev, &info);
  172. }
  173. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  174. {
  175. struct cnic_local *cp = dev->cnic_priv;
  176. struct cnic_eth_dev *ethdev = cp->ethdev;
  177. struct drv_ctl_info info;
  178. struct drv_ctl_l2_ring *ring = &info.data.ring;
  179. if (start)
  180. info.cmd = DRV_CTL_START_L2_CMD;
  181. else
  182. info.cmd = DRV_CTL_STOP_L2_CMD;
  183. ring->cid = cid;
  184. ring->client_id = cl_id;
  185. ethdev->drv_ctl(dev->netdev, &info);
  186. }
  187. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  188. {
  189. struct cnic_local *cp = dev->cnic_priv;
  190. struct cnic_eth_dev *ethdev = cp->ethdev;
  191. struct drv_ctl_info info;
  192. struct drv_ctl_io *io = &info.data.io;
  193. info.cmd = DRV_CTL_IO_WR_CMD;
  194. io->offset = off;
  195. io->data = val;
  196. ethdev->drv_ctl(dev->netdev, &info);
  197. }
  198. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  199. {
  200. struct cnic_local *cp = dev->cnic_priv;
  201. struct cnic_eth_dev *ethdev = cp->ethdev;
  202. struct drv_ctl_info info;
  203. struct drv_ctl_io *io = &info.data.io;
  204. info.cmd = DRV_CTL_IO_RD_CMD;
  205. io->offset = off;
  206. ethdev->drv_ctl(dev->netdev, &info);
  207. return io->data;
  208. }
  209. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  210. {
  211. struct cnic_local *cp = dev->cnic_priv;
  212. struct cnic_eth_dev *ethdev = cp->ethdev;
  213. struct drv_ctl_info info;
  214. struct fcoe_capabilities *fcoe_cap =
  215. &info.data.register_data.fcoe_features;
  216. if (reg) {
  217. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  218. if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
  219. memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
  220. } else {
  221. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  222. }
  223. info.data.ulp_type = ulp_type;
  224. ethdev->drv_ctl(dev->netdev, &info);
  225. }
  226. static int cnic_in_use(struct cnic_sock *csk)
  227. {
  228. return test_bit(SK_F_INUSE, &csk->flags);
  229. }
  230. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  231. {
  232. struct cnic_local *cp = dev->cnic_priv;
  233. struct cnic_eth_dev *ethdev = cp->ethdev;
  234. struct drv_ctl_info info;
  235. info.cmd = cmd;
  236. info.data.credit.credit_count = count;
  237. ethdev->drv_ctl(dev->netdev, &info);
  238. }
  239. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  240. {
  241. u32 i;
  242. if (!cp->ctx_tbl)
  243. return -EINVAL;
  244. for (i = 0; i < cp->max_cid_space; i++) {
  245. if (cp->ctx_tbl[i].cid == cid) {
  246. *l5_cid = i;
  247. return 0;
  248. }
  249. }
  250. return -EINVAL;
  251. }
  252. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  253. struct cnic_sock *csk)
  254. {
  255. struct iscsi_path path_req;
  256. char *buf = NULL;
  257. u16 len = 0;
  258. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  259. struct cnic_ulp_ops *ulp_ops;
  260. struct cnic_uio_dev *udev = cp->udev;
  261. int rc = 0, retry = 0;
  262. if (!udev || udev->uio_dev == -1)
  263. return -ENODEV;
  264. if (csk) {
  265. len = sizeof(path_req);
  266. buf = (char *) &path_req;
  267. memset(&path_req, 0, len);
  268. msg_type = ISCSI_KEVENT_PATH_REQ;
  269. path_req.handle = (u64) csk->l5_cid;
  270. if (test_bit(SK_F_IPV6, &csk->flags)) {
  271. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  272. sizeof(struct in6_addr));
  273. path_req.ip_addr_len = 16;
  274. } else {
  275. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  276. sizeof(struct in_addr));
  277. path_req.ip_addr_len = 4;
  278. }
  279. path_req.vlan_id = csk->vlan_id;
  280. path_req.pmtu = csk->mtu;
  281. }
  282. while (retry < 3) {
  283. rc = 0;
  284. rcu_read_lock();
  285. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  286. if (ulp_ops)
  287. rc = ulp_ops->iscsi_nl_send_msg(
  288. cp->ulp_handle[CNIC_ULP_ISCSI],
  289. msg_type, buf, len);
  290. rcu_read_unlock();
  291. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  292. break;
  293. msleep(100);
  294. retry++;
  295. }
  296. return rc;
  297. }
  298. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  299. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  300. char *buf, u16 len)
  301. {
  302. int rc = -EINVAL;
  303. switch (msg_type) {
  304. case ISCSI_UEVENT_PATH_UPDATE: {
  305. struct cnic_local *cp;
  306. u32 l5_cid;
  307. struct cnic_sock *csk;
  308. struct iscsi_path *path_resp;
  309. if (len < sizeof(*path_resp))
  310. break;
  311. path_resp = (struct iscsi_path *) buf;
  312. cp = dev->cnic_priv;
  313. l5_cid = (u32) path_resp->handle;
  314. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  315. break;
  316. rcu_read_lock();
  317. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  318. rc = -ENODEV;
  319. rcu_read_unlock();
  320. break;
  321. }
  322. csk = &cp->csk_tbl[l5_cid];
  323. csk_hold(csk);
  324. if (cnic_in_use(csk) &&
  325. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  326. csk->vlan_id = path_resp->vlan_id;
  327. memcpy(csk->ha, path_resp->mac_addr, 6);
  328. if (test_bit(SK_F_IPV6, &csk->flags))
  329. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  330. sizeof(struct in6_addr));
  331. else
  332. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  333. sizeof(struct in_addr));
  334. if (is_valid_ether_addr(csk->ha)) {
  335. cnic_cm_set_pg(csk);
  336. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  337. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  338. cnic_cm_upcall(cp, csk,
  339. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  340. clear_bit(SK_F_CONNECT_START, &csk->flags);
  341. }
  342. }
  343. csk_put(csk);
  344. rcu_read_unlock();
  345. rc = 0;
  346. }
  347. }
  348. return rc;
  349. }
  350. static int cnic_offld_prep(struct cnic_sock *csk)
  351. {
  352. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  353. return 0;
  354. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  355. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  356. return 0;
  357. }
  358. return 1;
  359. }
  360. static int cnic_close_prep(struct cnic_sock *csk)
  361. {
  362. clear_bit(SK_F_CONNECT_START, &csk->flags);
  363. smp_mb__after_clear_bit();
  364. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  365. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  366. msleep(1);
  367. return 1;
  368. }
  369. return 0;
  370. }
  371. static int cnic_abort_prep(struct cnic_sock *csk)
  372. {
  373. clear_bit(SK_F_CONNECT_START, &csk->flags);
  374. smp_mb__after_clear_bit();
  375. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  376. msleep(1);
  377. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  378. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  379. return 1;
  380. }
  381. return 0;
  382. }
  383. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  384. {
  385. struct cnic_dev *dev;
  386. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  387. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  388. return -EINVAL;
  389. }
  390. mutex_lock(&cnic_lock);
  391. if (cnic_ulp_tbl_prot(ulp_type)) {
  392. pr_err("%s: Type %d has already been registered\n",
  393. __func__, ulp_type);
  394. mutex_unlock(&cnic_lock);
  395. return -EBUSY;
  396. }
  397. read_lock(&cnic_dev_lock);
  398. list_for_each_entry(dev, &cnic_dev_list, list) {
  399. struct cnic_local *cp = dev->cnic_priv;
  400. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  401. }
  402. read_unlock(&cnic_dev_lock);
  403. atomic_set(&ulp_ops->ref_count, 0);
  404. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  405. mutex_unlock(&cnic_lock);
  406. /* Prevent race conditions with netdev_event */
  407. rtnl_lock();
  408. list_for_each_entry(dev, &cnic_dev_list, list) {
  409. struct cnic_local *cp = dev->cnic_priv;
  410. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  411. ulp_ops->cnic_init(dev);
  412. }
  413. rtnl_unlock();
  414. return 0;
  415. }
  416. int cnic_unregister_driver(int ulp_type)
  417. {
  418. struct cnic_dev *dev;
  419. struct cnic_ulp_ops *ulp_ops;
  420. int i = 0;
  421. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  422. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  423. return -EINVAL;
  424. }
  425. mutex_lock(&cnic_lock);
  426. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  427. if (!ulp_ops) {
  428. pr_err("%s: Type %d has not been registered\n",
  429. __func__, ulp_type);
  430. goto out_unlock;
  431. }
  432. read_lock(&cnic_dev_lock);
  433. list_for_each_entry(dev, &cnic_dev_list, list) {
  434. struct cnic_local *cp = dev->cnic_priv;
  435. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  436. pr_err("%s: Type %d still has devices registered\n",
  437. __func__, ulp_type);
  438. read_unlock(&cnic_dev_lock);
  439. goto out_unlock;
  440. }
  441. }
  442. read_unlock(&cnic_dev_lock);
  443. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  444. mutex_unlock(&cnic_lock);
  445. synchronize_rcu();
  446. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  447. msleep(100);
  448. i++;
  449. }
  450. if (atomic_read(&ulp_ops->ref_count) != 0)
  451. pr_warn("%s: Failed waiting for ref count to go to zero\n",
  452. __func__);
  453. return 0;
  454. out_unlock:
  455. mutex_unlock(&cnic_lock);
  456. return -EINVAL;
  457. }
  458. static int cnic_start_hw(struct cnic_dev *);
  459. static void cnic_stop_hw(struct cnic_dev *);
  460. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  461. void *ulp_ctx)
  462. {
  463. struct cnic_local *cp = dev->cnic_priv;
  464. struct cnic_ulp_ops *ulp_ops;
  465. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  466. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  467. return -EINVAL;
  468. }
  469. mutex_lock(&cnic_lock);
  470. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  471. pr_err("%s: Driver with type %d has not been registered\n",
  472. __func__, ulp_type);
  473. mutex_unlock(&cnic_lock);
  474. return -EAGAIN;
  475. }
  476. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  477. pr_err("%s: Type %d has already been registered to this device\n",
  478. __func__, ulp_type);
  479. mutex_unlock(&cnic_lock);
  480. return -EBUSY;
  481. }
  482. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  483. cp->ulp_handle[ulp_type] = ulp_ctx;
  484. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  485. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  486. cnic_hold(dev);
  487. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  488. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  489. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  490. mutex_unlock(&cnic_lock);
  491. cnic_ulp_ctl(dev, ulp_type, true);
  492. return 0;
  493. }
  494. EXPORT_SYMBOL(cnic_register_driver);
  495. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  496. {
  497. struct cnic_local *cp = dev->cnic_priv;
  498. int i = 0;
  499. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  500. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  501. return -EINVAL;
  502. }
  503. mutex_lock(&cnic_lock);
  504. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  505. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  506. cnic_put(dev);
  507. } else {
  508. pr_err("%s: device not registered to this ulp type %d\n",
  509. __func__, ulp_type);
  510. mutex_unlock(&cnic_lock);
  511. return -EINVAL;
  512. }
  513. mutex_unlock(&cnic_lock);
  514. if (ulp_type == CNIC_ULP_ISCSI)
  515. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  516. else if (ulp_type == CNIC_ULP_FCOE)
  517. dev->fcoe_cap = NULL;
  518. synchronize_rcu();
  519. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  520. i < 20) {
  521. msleep(100);
  522. i++;
  523. }
  524. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  525. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  526. cnic_ulp_ctl(dev, ulp_type, false);
  527. return 0;
  528. }
  529. EXPORT_SYMBOL(cnic_unregister_driver);
  530. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  531. u32 next)
  532. {
  533. id_tbl->start = start_id;
  534. id_tbl->max = size;
  535. id_tbl->next = next;
  536. spin_lock_init(&id_tbl->lock);
  537. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  538. if (!id_tbl->table)
  539. return -ENOMEM;
  540. return 0;
  541. }
  542. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  543. {
  544. kfree(id_tbl->table);
  545. id_tbl->table = NULL;
  546. }
  547. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  548. {
  549. int ret = -1;
  550. id -= id_tbl->start;
  551. if (id >= id_tbl->max)
  552. return ret;
  553. spin_lock(&id_tbl->lock);
  554. if (!test_bit(id, id_tbl->table)) {
  555. set_bit(id, id_tbl->table);
  556. ret = 0;
  557. }
  558. spin_unlock(&id_tbl->lock);
  559. return ret;
  560. }
  561. /* Returns -1 if not successful */
  562. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  563. {
  564. u32 id;
  565. spin_lock(&id_tbl->lock);
  566. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  567. if (id >= id_tbl->max) {
  568. id = -1;
  569. if (id_tbl->next != 0) {
  570. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  571. if (id >= id_tbl->next)
  572. id = -1;
  573. }
  574. }
  575. if (id < id_tbl->max) {
  576. set_bit(id, id_tbl->table);
  577. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  578. id += id_tbl->start;
  579. }
  580. spin_unlock(&id_tbl->lock);
  581. return id;
  582. }
  583. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  584. {
  585. if (id == -1)
  586. return;
  587. id -= id_tbl->start;
  588. if (id >= id_tbl->max)
  589. return;
  590. clear_bit(id, id_tbl->table);
  591. }
  592. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  593. {
  594. int i;
  595. if (!dma->pg_arr)
  596. return;
  597. for (i = 0; i < dma->num_pages; i++) {
  598. if (dma->pg_arr[i]) {
  599. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  600. dma->pg_arr[i], dma->pg_map_arr[i]);
  601. dma->pg_arr[i] = NULL;
  602. }
  603. }
  604. if (dma->pgtbl) {
  605. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  606. dma->pgtbl, dma->pgtbl_map);
  607. dma->pgtbl = NULL;
  608. }
  609. kfree(dma->pg_arr);
  610. dma->pg_arr = NULL;
  611. dma->num_pages = 0;
  612. }
  613. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  614. {
  615. int i;
  616. __le32 *page_table = (__le32 *) dma->pgtbl;
  617. for (i = 0; i < dma->num_pages; i++) {
  618. /* Each entry needs to be in big endian format. */
  619. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  620. page_table++;
  621. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  622. page_table++;
  623. }
  624. }
  625. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  626. {
  627. int i;
  628. __le32 *page_table = (__le32 *) dma->pgtbl;
  629. for (i = 0; i < dma->num_pages; i++) {
  630. /* Each entry needs to be in little endian format. */
  631. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  632. page_table++;
  633. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  634. page_table++;
  635. }
  636. }
  637. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  638. int pages, int use_pg_tbl)
  639. {
  640. int i, size;
  641. struct cnic_local *cp = dev->cnic_priv;
  642. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  643. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  644. if (dma->pg_arr == NULL)
  645. return -ENOMEM;
  646. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  647. dma->num_pages = pages;
  648. for (i = 0; i < pages; i++) {
  649. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  650. BCM_PAGE_SIZE,
  651. &dma->pg_map_arr[i],
  652. GFP_ATOMIC);
  653. if (dma->pg_arr[i] == NULL)
  654. goto error;
  655. }
  656. if (!use_pg_tbl)
  657. return 0;
  658. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  659. ~(BCM_PAGE_SIZE - 1);
  660. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  661. &dma->pgtbl_map, GFP_ATOMIC);
  662. if (dma->pgtbl == NULL)
  663. goto error;
  664. cp->setup_pgtbl(dev, dma);
  665. return 0;
  666. error:
  667. cnic_free_dma(dev, dma);
  668. return -ENOMEM;
  669. }
  670. static void cnic_free_context(struct cnic_dev *dev)
  671. {
  672. struct cnic_local *cp = dev->cnic_priv;
  673. int i;
  674. for (i = 0; i < cp->ctx_blks; i++) {
  675. if (cp->ctx_arr[i].ctx) {
  676. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  677. cp->ctx_arr[i].ctx,
  678. cp->ctx_arr[i].mapping);
  679. cp->ctx_arr[i].ctx = NULL;
  680. }
  681. }
  682. }
  683. static void __cnic_free_uio_rings(struct cnic_uio_dev *udev)
  684. {
  685. if (udev->l2_buf) {
  686. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  687. udev->l2_buf, udev->l2_buf_map);
  688. udev->l2_buf = NULL;
  689. }
  690. if (udev->l2_ring) {
  691. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  692. udev->l2_ring, udev->l2_ring_map);
  693. udev->l2_ring = NULL;
  694. }
  695. }
  696. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  697. {
  698. uio_unregister_device(&udev->cnic_uinfo);
  699. __cnic_free_uio_rings(udev);
  700. pci_dev_put(udev->pdev);
  701. kfree(udev);
  702. }
  703. static void cnic_free_uio(struct cnic_uio_dev *udev)
  704. {
  705. if (!udev)
  706. return;
  707. write_lock(&cnic_dev_lock);
  708. list_del_init(&udev->list);
  709. write_unlock(&cnic_dev_lock);
  710. __cnic_free_uio(udev);
  711. }
  712. static void cnic_free_resc(struct cnic_dev *dev)
  713. {
  714. struct cnic_local *cp = dev->cnic_priv;
  715. struct cnic_uio_dev *udev = cp->udev;
  716. if (udev) {
  717. udev->dev = NULL;
  718. cp->udev = NULL;
  719. if (udev->uio_dev == -1)
  720. __cnic_free_uio_rings(udev);
  721. }
  722. cnic_free_context(dev);
  723. kfree(cp->ctx_arr);
  724. cp->ctx_arr = NULL;
  725. cp->ctx_blks = 0;
  726. cnic_free_dma(dev, &cp->gbl_buf_info);
  727. cnic_free_dma(dev, &cp->kwq_info);
  728. cnic_free_dma(dev, &cp->kwq_16_data_info);
  729. cnic_free_dma(dev, &cp->kcq2.dma);
  730. cnic_free_dma(dev, &cp->kcq1.dma);
  731. kfree(cp->iscsi_tbl);
  732. cp->iscsi_tbl = NULL;
  733. kfree(cp->ctx_tbl);
  734. cp->ctx_tbl = NULL;
  735. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  736. cnic_free_id_tbl(&cp->cid_tbl);
  737. }
  738. static int cnic_alloc_context(struct cnic_dev *dev)
  739. {
  740. struct cnic_local *cp = dev->cnic_priv;
  741. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  742. int i, k, arr_size;
  743. cp->ctx_blk_size = BCM_PAGE_SIZE;
  744. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  745. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  746. sizeof(struct cnic_ctx);
  747. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  748. if (cp->ctx_arr == NULL)
  749. return -ENOMEM;
  750. k = 0;
  751. for (i = 0; i < 2; i++) {
  752. u32 j, reg, off, lo, hi;
  753. if (i == 0)
  754. off = BNX2_PG_CTX_MAP;
  755. else
  756. off = BNX2_ISCSI_CTX_MAP;
  757. reg = cnic_reg_rd_ind(dev, off);
  758. lo = reg >> 16;
  759. hi = reg & 0xffff;
  760. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  761. cp->ctx_arr[k].cid = j;
  762. }
  763. cp->ctx_blks = k;
  764. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  765. cp->ctx_blks = 0;
  766. return -ENOMEM;
  767. }
  768. for (i = 0; i < cp->ctx_blks; i++) {
  769. cp->ctx_arr[i].ctx =
  770. dma_alloc_coherent(&dev->pcidev->dev,
  771. BCM_PAGE_SIZE,
  772. &cp->ctx_arr[i].mapping,
  773. GFP_KERNEL);
  774. if (cp->ctx_arr[i].ctx == NULL)
  775. return -ENOMEM;
  776. }
  777. }
  778. return 0;
  779. }
  780. static u16 cnic_bnx2_next_idx(u16 idx)
  781. {
  782. return idx + 1;
  783. }
  784. static u16 cnic_bnx2_hw_idx(u16 idx)
  785. {
  786. return idx;
  787. }
  788. static u16 cnic_bnx2x_next_idx(u16 idx)
  789. {
  790. idx++;
  791. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  792. idx++;
  793. return idx;
  794. }
  795. static u16 cnic_bnx2x_hw_idx(u16 idx)
  796. {
  797. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  798. idx++;
  799. return idx;
  800. }
  801. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  802. bool use_pg_tbl)
  803. {
  804. int err, i, use_page_tbl = 0;
  805. struct kcqe **kcq;
  806. if (use_pg_tbl)
  807. use_page_tbl = 1;
  808. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  809. if (err)
  810. return err;
  811. kcq = (struct kcqe **) info->dma.pg_arr;
  812. info->kcq = kcq;
  813. info->next_idx = cnic_bnx2_next_idx;
  814. info->hw_idx = cnic_bnx2_hw_idx;
  815. if (use_pg_tbl)
  816. return 0;
  817. info->next_idx = cnic_bnx2x_next_idx;
  818. info->hw_idx = cnic_bnx2x_hw_idx;
  819. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  820. struct bnx2x_bd_chain_next *next =
  821. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  822. int j = i + 1;
  823. if (j >= KCQ_PAGE_CNT)
  824. j = 0;
  825. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  826. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  827. }
  828. return 0;
  829. }
  830. static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages)
  831. {
  832. struct cnic_local *cp = udev->dev->cnic_priv;
  833. if (udev->l2_ring)
  834. return 0;
  835. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  836. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  837. &udev->l2_ring_map,
  838. GFP_KERNEL | __GFP_COMP);
  839. if (!udev->l2_ring)
  840. return -ENOMEM;
  841. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  842. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  843. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  844. &udev->l2_buf_map,
  845. GFP_KERNEL | __GFP_COMP);
  846. if (!udev->l2_buf) {
  847. __cnic_free_uio_rings(udev);
  848. return -ENOMEM;
  849. }
  850. return 0;
  851. }
  852. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  853. {
  854. struct cnic_local *cp = dev->cnic_priv;
  855. struct cnic_uio_dev *udev;
  856. read_lock(&cnic_dev_lock);
  857. list_for_each_entry(udev, &cnic_udev_list, list) {
  858. if (udev->pdev == dev->pcidev) {
  859. udev->dev = dev;
  860. if (__cnic_alloc_uio_rings(udev, pages)) {
  861. udev->dev = NULL;
  862. read_unlock(&cnic_dev_lock);
  863. return -ENOMEM;
  864. }
  865. cp->udev = udev;
  866. read_unlock(&cnic_dev_lock);
  867. return 0;
  868. }
  869. }
  870. read_unlock(&cnic_dev_lock);
  871. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  872. if (!udev)
  873. return -ENOMEM;
  874. udev->uio_dev = -1;
  875. udev->dev = dev;
  876. udev->pdev = dev->pcidev;
  877. if (__cnic_alloc_uio_rings(udev, pages))
  878. goto err_udev;
  879. write_lock(&cnic_dev_lock);
  880. list_add(&udev->list, &cnic_udev_list);
  881. write_unlock(&cnic_dev_lock);
  882. pci_dev_get(udev->pdev);
  883. cp->udev = udev;
  884. return 0;
  885. err_udev:
  886. kfree(udev);
  887. return -ENOMEM;
  888. }
  889. static int cnic_init_uio(struct cnic_dev *dev)
  890. {
  891. struct cnic_local *cp = dev->cnic_priv;
  892. struct cnic_uio_dev *udev = cp->udev;
  893. struct uio_info *uinfo;
  894. int ret = 0;
  895. if (!udev)
  896. return -ENOMEM;
  897. uinfo = &udev->cnic_uinfo;
  898. uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
  899. uinfo->mem[0].internal_addr = dev->regview;
  900. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  901. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  902. uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
  903. TX_MAX_TSS_RINGS + 1);
  904. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  905. PAGE_MASK;
  906. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  907. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  908. else
  909. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  910. uinfo->name = "bnx2_cnic";
  911. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  912. uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
  913. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  914. PAGE_MASK;
  915. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  916. uinfo->name = "bnx2x_cnic";
  917. }
  918. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  919. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  920. uinfo->mem[2].size = udev->l2_ring_size;
  921. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  922. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  923. uinfo->mem[3].size = udev->l2_buf_size;
  924. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  925. uinfo->version = CNIC_MODULE_VERSION;
  926. uinfo->irq = UIO_IRQ_CUSTOM;
  927. uinfo->open = cnic_uio_open;
  928. uinfo->release = cnic_uio_close;
  929. if (udev->uio_dev == -1) {
  930. if (!uinfo->priv) {
  931. uinfo->priv = udev;
  932. ret = uio_register_device(&udev->pdev->dev, uinfo);
  933. }
  934. } else {
  935. cnic_init_rings(dev);
  936. }
  937. return ret;
  938. }
  939. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  940. {
  941. struct cnic_local *cp = dev->cnic_priv;
  942. int ret;
  943. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  944. if (ret)
  945. goto error;
  946. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  947. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  948. if (ret)
  949. goto error;
  950. ret = cnic_alloc_context(dev);
  951. if (ret)
  952. goto error;
  953. ret = cnic_alloc_uio_rings(dev, 2);
  954. if (ret)
  955. goto error;
  956. ret = cnic_init_uio(dev);
  957. if (ret)
  958. goto error;
  959. return 0;
  960. error:
  961. cnic_free_resc(dev);
  962. return ret;
  963. }
  964. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  965. {
  966. struct cnic_local *cp = dev->cnic_priv;
  967. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  968. int total_mem, blks, i;
  969. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  970. blks = total_mem / ctx_blk_size;
  971. if (total_mem % ctx_blk_size)
  972. blks++;
  973. if (blks > cp->ethdev->ctx_tbl_len)
  974. return -ENOMEM;
  975. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  976. if (cp->ctx_arr == NULL)
  977. return -ENOMEM;
  978. cp->ctx_blks = blks;
  979. cp->ctx_blk_size = ctx_blk_size;
  980. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  981. cp->ctx_align = 0;
  982. else
  983. cp->ctx_align = ctx_blk_size;
  984. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  985. for (i = 0; i < blks; i++) {
  986. cp->ctx_arr[i].ctx =
  987. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  988. &cp->ctx_arr[i].mapping,
  989. GFP_KERNEL);
  990. if (cp->ctx_arr[i].ctx == NULL)
  991. return -ENOMEM;
  992. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  993. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  994. cnic_free_context(dev);
  995. cp->ctx_blk_size += cp->ctx_align;
  996. i = -1;
  997. continue;
  998. }
  999. }
  1000. }
  1001. return 0;
  1002. }
  1003. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  1004. {
  1005. struct cnic_local *cp = dev->cnic_priv;
  1006. struct cnic_eth_dev *ethdev = cp->ethdev;
  1007. u32 start_cid = ethdev->starting_cid;
  1008. int i, j, n, ret, pages;
  1009. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  1010. cp->iro_arr = ethdev->iro_arr;
  1011. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  1012. cp->iscsi_start_cid = start_cid;
  1013. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  1014. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1015. cp->max_cid_space += dev->max_fcoe_conn;
  1016. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  1017. if (!cp->fcoe_init_cid)
  1018. cp->fcoe_init_cid = 0x10;
  1019. }
  1020. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  1021. GFP_KERNEL);
  1022. if (!cp->iscsi_tbl)
  1023. goto error;
  1024. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  1025. cp->max_cid_space, GFP_KERNEL);
  1026. if (!cp->ctx_tbl)
  1027. goto error;
  1028. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1029. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1030. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1031. }
  1032. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1033. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1034. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1035. PAGE_SIZE;
  1036. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1037. if (ret)
  1038. return -ENOMEM;
  1039. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1040. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1041. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1042. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1043. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1044. off;
  1045. if ((i % n) == (n - 1))
  1046. j++;
  1047. }
  1048. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1049. if (ret)
  1050. goto error;
  1051. if (CNIC_SUPPORTS_FCOE(cp)) {
  1052. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1053. if (ret)
  1054. goto error;
  1055. }
  1056. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1057. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1058. if (ret)
  1059. goto error;
  1060. ret = cnic_alloc_bnx2x_context(dev);
  1061. if (ret)
  1062. goto error;
  1063. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  1064. return 0;
  1065. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1066. cp->l2_rx_ring_size = 15;
  1067. ret = cnic_alloc_uio_rings(dev, 4);
  1068. if (ret)
  1069. goto error;
  1070. ret = cnic_init_uio(dev);
  1071. if (ret)
  1072. goto error;
  1073. return 0;
  1074. error:
  1075. cnic_free_resc(dev);
  1076. return -ENOMEM;
  1077. }
  1078. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1079. {
  1080. return cp->max_kwq_idx -
  1081. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1082. }
  1083. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1084. u32 num_wqes)
  1085. {
  1086. struct cnic_local *cp = dev->cnic_priv;
  1087. struct kwqe *prod_qe;
  1088. u16 prod, sw_prod, i;
  1089. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1090. return -EAGAIN; /* bnx2 is down */
  1091. spin_lock_bh(&cp->cnic_ulp_lock);
  1092. if (num_wqes > cnic_kwq_avail(cp) &&
  1093. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1094. spin_unlock_bh(&cp->cnic_ulp_lock);
  1095. return -EAGAIN;
  1096. }
  1097. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1098. prod = cp->kwq_prod_idx;
  1099. sw_prod = prod & MAX_KWQ_IDX;
  1100. for (i = 0; i < num_wqes; i++) {
  1101. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1102. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1103. prod++;
  1104. sw_prod = prod & MAX_KWQ_IDX;
  1105. }
  1106. cp->kwq_prod_idx = prod;
  1107. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1108. spin_unlock_bh(&cp->cnic_ulp_lock);
  1109. return 0;
  1110. }
  1111. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1112. union l5cm_specific_data *l5_data)
  1113. {
  1114. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1115. dma_addr_t map;
  1116. map = ctx->kwqe_data_mapping;
  1117. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1118. l5_data->phy_address.hi = (u64) map >> 32;
  1119. return ctx->kwqe_data;
  1120. }
  1121. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1122. u32 type, union l5cm_specific_data *l5_data)
  1123. {
  1124. struct cnic_local *cp = dev->cnic_priv;
  1125. struct l5cm_spe kwqe;
  1126. struct kwqe_16 *kwq[1];
  1127. u16 type_16;
  1128. int ret;
  1129. kwqe.hdr.conn_and_cmd_data =
  1130. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1131. BNX2X_HW_CID(cp, cid)));
  1132. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1133. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1134. SPE_HDR_FUNCTION_ID;
  1135. kwqe.hdr.type = cpu_to_le16(type_16);
  1136. kwqe.hdr.reserved1 = 0;
  1137. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1138. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1139. kwq[0] = (struct kwqe_16 *) &kwqe;
  1140. spin_lock_bh(&cp->cnic_ulp_lock);
  1141. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1142. spin_unlock_bh(&cp->cnic_ulp_lock);
  1143. if (ret == 1)
  1144. return 0;
  1145. return ret;
  1146. }
  1147. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1148. struct kcqe *cqes[], u32 num_cqes)
  1149. {
  1150. struct cnic_local *cp = dev->cnic_priv;
  1151. struct cnic_ulp_ops *ulp_ops;
  1152. rcu_read_lock();
  1153. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1154. if (likely(ulp_ops)) {
  1155. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1156. cqes, num_cqes);
  1157. }
  1158. rcu_read_unlock();
  1159. }
  1160. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1161. {
  1162. struct cnic_local *cp = dev->cnic_priv;
  1163. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1164. int hq_bds, pages;
  1165. u32 pfid = cp->pfid;
  1166. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1167. cp->num_ccells = req1->num_ccells_per_conn;
  1168. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1169. cp->num_iscsi_tasks;
  1170. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1171. BNX2X_ISCSI_R2TQE_SIZE;
  1172. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1173. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1174. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1175. cp->num_cqs = req1->num_cqs;
  1176. if (!dev->max_iscsi_conn)
  1177. return 0;
  1178. /* init Tstorm RAM */
  1179. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1180. req1->rq_num_wqes);
  1181. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1182. PAGE_SIZE);
  1183. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1184. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1185. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1186. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1187. req1->num_tasks_per_conn);
  1188. /* init Ustorm RAM */
  1189. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1190. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1191. req1->rq_buffer_size);
  1192. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1193. PAGE_SIZE);
  1194. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1195. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1196. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1197. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1198. req1->num_tasks_per_conn);
  1199. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1200. req1->rq_num_wqes);
  1201. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1202. req1->cq_num_wqes);
  1203. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1204. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1205. /* init Xstorm RAM */
  1206. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1207. PAGE_SIZE);
  1208. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1209. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1210. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1211. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1212. req1->num_tasks_per_conn);
  1213. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1214. hq_bds);
  1215. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1216. req1->num_tasks_per_conn);
  1217. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1218. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1219. /* init Cstorm RAM */
  1220. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1221. PAGE_SIZE);
  1222. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1223. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1224. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1225. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1226. req1->num_tasks_per_conn);
  1227. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1228. req1->cq_num_wqes);
  1229. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1230. hq_bds);
  1231. return 0;
  1232. }
  1233. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1234. {
  1235. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1236. struct cnic_local *cp = dev->cnic_priv;
  1237. u32 pfid = cp->pfid;
  1238. struct iscsi_kcqe kcqe;
  1239. struct kcqe *cqes[1];
  1240. memset(&kcqe, 0, sizeof(kcqe));
  1241. if (!dev->max_iscsi_conn) {
  1242. kcqe.completion_status =
  1243. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1244. goto done;
  1245. }
  1246. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1247. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1248. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1249. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1250. req2->error_bit_map[1]);
  1251. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1252. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1253. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1254. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1255. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1256. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1257. req2->error_bit_map[1]);
  1258. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1259. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1260. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1261. done:
  1262. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1263. cqes[0] = (struct kcqe *) &kcqe;
  1264. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1265. return 0;
  1266. }
  1267. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1268. {
  1269. struct cnic_local *cp = dev->cnic_priv;
  1270. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1271. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1272. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1273. cnic_free_dma(dev, &iscsi->hq_info);
  1274. cnic_free_dma(dev, &iscsi->r2tq_info);
  1275. cnic_free_dma(dev, &iscsi->task_array_info);
  1276. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1277. } else {
  1278. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1279. }
  1280. ctx->cid = 0;
  1281. }
  1282. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1283. {
  1284. u32 cid;
  1285. int ret, pages;
  1286. struct cnic_local *cp = dev->cnic_priv;
  1287. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1288. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1289. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1290. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1291. if (cid == -1) {
  1292. ret = -ENOMEM;
  1293. goto error;
  1294. }
  1295. ctx->cid = cid;
  1296. return 0;
  1297. }
  1298. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1299. if (cid == -1) {
  1300. ret = -ENOMEM;
  1301. goto error;
  1302. }
  1303. ctx->cid = cid;
  1304. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1305. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1306. if (ret)
  1307. goto error;
  1308. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1309. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1310. if (ret)
  1311. goto error;
  1312. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1313. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1314. if (ret)
  1315. goto error;
  1316. return 0;
  1317. error:
  1318. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1319. return ret;
  1320. }
  1321. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1322. struct regpair *ctx_addr)
  1323. {
  1324. struct cnic_local *cp = dev->cnic_priv;
  1325. struct cnic_eth_dev *ethdev = cp->ethdev;
  1326. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1327. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1328. unsigned long align_off = 0;
  1329. dma_addr_t ctx_map;
  1330. void *ctx;
  1331. if (cp->ctx_align) {
  1332. unsigned long mask = cp->ctx_align - 1;
  1333. if (cp->ctx_arr[blk].mapping & mask)
  1334. align_off = cp->ctx_align -
  1335. (cp->ctx_arr[blk].mapping & mask);
  1336. }
  1337. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1338. (off * BNX2X_CONTEXT_MEM_SIZE);
  1339. ctx = cp->ctx_arr[blk].ctx + align_off +
  1340. (off * BNX2X_CONTEXT_MEM_SIZE);
  1341. if (init)
  1342. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1343. ctx_addr->lo = ctx_map & 0xffffffff;
  1344. ctx_addr->hi = (u64) ctx_map >> 32;
  1345. return ctx;
  1346. }
  1347. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1348. u32 num)
  1349. {
  1350. struct cnic_local *cp = dev->cnic_priv;
  1351. struct iscsi_kwqe_conn_offload1 *req1 =
  1352. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1353. struct iscsi_kwqe_conn_offload2 *req2 =
  1354. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1355. struct iscsi_kwqe_conn_offload3 *req3;
  1356. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1357. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1358. u32 cid = ctx->cid;
  1359. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1360. struct iscsi_context *ictx;
  1361. struct regpair context_addr;
  1362. int i, j, n = 2, n_max;
  1363. u8 port = CNIC_PORT(cp);
  1364. ctx->ctx_flags = 0;
  1365. if (!req2->num_additional_wqes)
  1366. return -EINVAL;
  1367. n_max = req2->num_additional_wqes + 2;
  1368. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1369. if (ictx == NULL)
  1370. return -ENOMEM;
  1371. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1372. ictx->xstorm_ag_context.hq_prod = 1;
  1373. ictx->xstorm_st_context.iscsi.first_burst_length =
  1374. ISCSI_DEF_FIRST_BURST_LEN;
  1375. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1376. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1377. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1378. req1->sq_page_table_addr_lo;
  1379. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1380. req1->sq_page_table_addr_hi;
  1381. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1382. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1383. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1384. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1385. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1386. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1387. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1388. iscsi->hq_info.pgtbl[0];
  1389. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1390. iscsi->hq_info.pgtbl[1];
  1391. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1392. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1393. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1394. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1395. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1396. iscsi->r2tq_info.pgtbl[0];
  1397. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1398. iscsi->r2tq_info.pgtbl[1];
  1399. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1400. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1401. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1402. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1403. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1404. BNX2X_ISCSI_PBL_NOT_CACHED;
  1405. ictx->xstorm_st_context.iscsi.flags.flags |=
  1406. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1407. ictx->xstorm_st_context.iscsi.flags.flags |=
  1408. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1409. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1410. ETH_P_8021Q;
  1411. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1412. cp->port_mode == CHIP_2_PORT_MODE) {
  1413. port = 0;
  1414. }
  1415. ictx->xstorm_st_context.common.flags =
  1416. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1417. ictx->xstorm_st_context.common.flags =
  1418. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1419. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1420. /* TSTORM requires the base address of RQ DB & not PTE */
  1421. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1422. req2->rq_page_table_addr_lo & PAGE_MASK;
  1423. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1424. req2->rq_page_table_addr_hi;
  1425. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1426. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1427. ictx->tstorm_st_context.tcp.flags2 |=
  1428. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1429. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1430. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1431. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1432. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1433. req2->rq_page_table_addr_lo;
  1434. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1435. req2->rq_page_table_addr_hi;
  1436. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1437. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1438. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1439. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1440. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1441. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1442. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1443. iscsi->r2tq_info.pgtbl[0];
  1444. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1445. iscsi->r2tq_info.pgtbl[1];
  1446. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1447. req1->cq_page_table_addr_lo;
  1448. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1449. req1->cq_page_table_addr_hi;
  1450. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1451. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1452. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1453. ictx->ustorm_st_context.task_pbe_cache_index =
  1454. BNX2X_ISCSI_PBL_NOT_CACHED;
  1455. ictx->ustorm_st_context.task_pdu_cache_index =
  1456. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1457. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1458. if (j == 3) {
  1459. if (n >= n_max)
  1460. break;
  1461. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1462. j = 0;
  1463. }
  1464. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1465. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1466. req3->qp_first_pte[j].hi;
  1467. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1468. req3->qp_first_pte[j].lo;
  1469. }
  1470. ictx->ustorm_st_context.task_pbl_base.lo =
  1471. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1472. ictx->ustorm_st_context.task_pbl_base.hi =
  1473. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1474. ictx->ustorm_st_context.tce_phy_addr.lo =
  1475. iscsi->task_array_info.pgtbl[0];
  1476. ictx->ustorm_st_context.tce_phy_addr.hi =
  1477. iscsi->task_array_info.pgtbl[1];
  1478. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1479. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1480. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1481. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1482. ISCSI_DEF_MAX_BURST_LEN;
  1483. ictx->ustorm_st_context.negotiated_rx |=
  1484. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1485. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1486. ictx->cstorm_st_context.hq_pbl_base.lo =
  1487. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1488. ictx->cstorm_st_context.hq_pbl_base.hi =
  1489. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1490. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1491. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1492. ictx->cstorm_st_context.task_pbl_base.lo =
  1493. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1494. ictx->cstorm_st_context.task_pbl_base.hi =
  1495. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1496. /* CSTORM and USTORM initialization is different, CSTORM requires
  1497. * CQ DB base & not PTE addr */
  1498. ictx->cstorm_st_context.cq_db_base.lo =
  1499. req1->cq_page_table_addr_lo & PAGE_MASK;
  1500. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1501. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1502. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1503. for (i = 0; i < cp->num_cqs; i++) {
  1504. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1505. ISCSI_INITIAL_SN;
  1506. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1507. ISCSI_INITIAL_SN;
  1508. }
  1509. ictx->xstorm_ag_context.cdu_reserved =
  1510. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1511. ISCSI_CONNECTION_TYPE);
  1512. ictx->ustorm_ag_context.cdu_usage =
  1513. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1514. ISCSI_CONNECTION_TYPE);
  1515. return 0;
  1516. }
  1517. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1518. u32 num, int *work)
  1519. {
  1520. struct iscsi_kwqe_conn_offload1 *req1;
  1521. struct iscsi_kwqe_conn_offload2 *req2;
  1522. struct cnic_local *cp = dev->cnic_priv;
  1523. struct cnic_context *ctx;
  1524. struct iscsi_kcqe kcqe;
  1525. struct kcqe *cqes[1];
  1526. u32 l5_cid;
  1527. int ret = 0;
  1528. if (num < 2) {
  1529. *work = num;
  1530. return -EINVAL;
  1531. }
  1532. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1533. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1534. if ((num - 2) < req2->num_additional_wqes) {
  1535. *work = num;
  1536. return -EINVAL;
  1537. }
  1538. *work = 2 + req2->num_additional_wqes;
  1539. l5_cid = req1->iscsi_conn_id;
  1540. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1541. return -EINVAL;
  1542. memset(&kcqe, 0, sizeof(kcqe));
  1543. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1544. kcqe.iscsi_conn_id = l5_cid;
  1545. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1546. ctx = &cp->ctx_tbl[l5_cid];
  1547. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1548. kcqe.completion_status =
  1549. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1550. goto done;
  1551. }
  1552. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1553. atomic_dec(&cp->iscsi_conn);
  1554. goto done;
  1555. }
  1556. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1557. if (ret) {
  1558. atomic_dec(&cp->iscsi_conn);
  1559. ret = 0;
  1560. goto done;
  1561. }
  1562. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1563. if (ret < 0) {
  1564. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1565. atomic_dec(&cp->iscsi_conn);
  1566. goto done;
  1567. }
  1568. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1569. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1570. done:
  1571. cqes[0] = (struct kcqe *) &kcqe;
  1572. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1573. return 0;
  1574. }
  1575. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1576. {
  1577. struct cnic_local *cp = dev->cnic_priv;
  1578. struct iscsi_kwqe_conn_update *req =
  1579. (struct iscsi_kwqe_conn_update *) kwqe;
  1580. void *data;
  1581. union l5cm_specific_data l5_data;
  1582. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1583. int ret;
  1584. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1585. return -EINVAL;
  1586. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1587. if (!data)
  1588. return -ENOMEM;
  1589. memcpy(data, kwqe, sizeof(struct kwqe));
  1590. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1591. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1592. return ret;
  1593. }
  1594. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1595. {
  1596. struct cnic_local *cp = dev->cnic_priv;
  1597. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1598. union l5cm_specific_data l5_data;
  1599. int ret;
  1600. u32 hw_cid;
  1601. init_waitqueue_head(&ctx->waitq);
  1602. ctx->wait_cond = 0;
  1603. memset(&l5_data, 0, sizeof(l5_data));
  1604. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1605. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1606. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1607. if (ret == 0) {
  1608. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1609. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1610. return -EBUSY;
  1611. }
  1612. return 0;
  1613. }
  1614. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1615. {
  1616. struct cnic_local *cp = dev->cnic_priv;
  1617. struct iscsi_kwqe_conn_destroy *req =
  1618. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1619. u32 l5_cid = req->reserved0;
  1620. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1621. int ret = 0;
  1622. struct iscsi_kcqe kcqe;
  1623. struct kcqe *cqes[1];
  1624. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1625. goto skip_cfc_delete;
  1626. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1627. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1628. if (delta > (2 * HZ))
  1629. delta = 0;
  1630. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1631. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1632. goto destroy_reply;
  1633. }
  1634. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1635. skip_cfc_delete:
  1636. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1637. if (!ret) {
  1638. atomic_dec(&cp->iscsi_conn);
  1639. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1640. }
  1641. destroy_reply:
  1642. memset(&kcqe, 0, sizeof(kcqe));
  1643. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1644. kcqe.iscsi_conn_id = l5_cid;
  1645. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1646. kcqe.iscsi_conn_context_id = req->context_id;
  1647. cqes[0] = (struct kcqe *) &kcqe;
  1648. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1649. return 0;
  1650. }
  1651. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1652. struct l4_kwq_connect_req1 *kwqe1,
  1653. struct l4_kwq_connect_req3 *kwqe3,
  1654. struct l5cm_active_conn_buffer *conn_buf)
  1655. {
  1656. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1657. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1658. &conn_buf->xstorm_conn_buffer;
  1659. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1660. &conn_buf->tstorm_conn_buffer;
  1661. struct regpair context_addr;
  1662. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1663. struct in6_addr src_ip, dst_ip;
  1664. int i;
  1665. u32 *addrp;
  1666. addrp = (u32 *) &conn_addr->local_ip_addr;
  1667. for (i = 0; i < 4; i++, addrp++)
  1668. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1669. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1670. for (i = 0; i < 4; i++, addrp++)
  1671. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1672. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1673. xstorm_buf->context_addr.hi = context_addr.hi;
  1674. xstorm_buf->context_addr.lo = context_addr.lo;
  1675. xstorm_buf->mss = 0xffff;
  1676. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1677. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1678. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1679. xstorm_buf->pseudo_header_checksum =
  1680. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1681. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1682. tstorm_buf->params |=
  1683. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1684. if (kwqe3->ka_timeout) {
  1685. tstorm_buf->ka_enable = 1;
  1686. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1687. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1688. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1689. }
  1690. tstorm_buf->max_rt_time = 0xffffffff;
  1691. }
  1692. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1693. {
  1694. struct cnic_local *cp = dev->cnic_priv;
  1695. u32 pfid = cp->pfid;
  1696. u8 *mac = dev->mac_addr;
  1697. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1698. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1699. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1700. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1701. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1702. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1703. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1704. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1705. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1706. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1707. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1708. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1709. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1710. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1711. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1712. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1713. mac[4]);
  1714. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1715. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1716. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1717. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1718. mac[2]);
  1719. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1720. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1721. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1722. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1723. mac[0]);
  1724. }
  1725. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1726. {
  1727. struct cnic_local *cp = dev->cnic_priv;
  1728. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1729. u16 tstorm_flags = 0;
  1730. if (tcp_ts) {
  1731. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1732. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1733. }
  1734. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1735. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1736. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1737. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1738. }
  1739. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1740. u32 num, int *work)
  1741. {
  1742. struct cnic_local *cp = dev->cnic_priv;
  1743. struct l4_kwq_connect_req1 *kwqe1 =
  1744. (struct l4_kwq_connect_req1 *) wqes[0];
  1745. struct l4_kwq_connect_req3 *kwqe3;
  1746. struct l5cm_active_conn_buffer *conn_buf;
  1747. struct l5cm_conn_addr_params *conn_addr;
  1748. union l5cm_specific_data l5_data;
  1749. u32 l5_cid = kwqe1->pg_cid;
  1750. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1751. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1752. int ret;
  1753. if (num < 2) {
  1754. *work = num;
  1755. return -EINVAL;
  1756. }
  1757. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1758. *work = 3;
  1759. else
  1760. *work = 2;
  1761. if (num < *work) {
  1762. *work = num;
  1763. return -EINVAL;
  1764. }
  1765. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1766. netdev_err(dev->netdev, "conn_buf size too big\n");
  1767. return -ENOMEM;
  1768. }
  1769. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1770. if (!conn_buf)
  1771. return -ENOMEM;
  1772. memset(conn_buf, 0, sizeof(*conn_buf));
  1773. conn_addr = &conn_buf->conn_addr_buf;
  1774. conn_addr->remote_addr_0 = csk->ha[0];
  1775. conn_addr->remote_addr_1 = csk->ha[1];
  1776. conn_addr->remote_addr_2 = csk->ha[2];
  1777. conn_addr->remote_addr_3 = csk->ha[3];
  1778. conn_addr->remote_addr_4 = csk->ha[4];
  1779. conn_addr->remote_addr_5 = csk->ha[5];
  1780. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1781. struct l4_kwq_connect_req2 *kwqe2 =
  1782. (struct l4_kwq_connect_req2 *) wqes[1];
  1783. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1784. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1785. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1786. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1787. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1788. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1789. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1790. }
  1791. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1792. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1793. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1794. conn_addr->local_tcp_port = kwqe1->src_port;
  1795. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1796. conn_addr->pmtu = kwqe3->pmtu;
  1797. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1798. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1799. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1800. cnic_bnx2x_set_tcp_timestamp(dev,
  1801. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1802. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1803. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1804. if (!ret)
  1805. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1806. return ret;
  1807. }
  1808. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1809. {
  1810. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1811. union l5cm_specific_data l5_data;
  1812. int ret;
  1813. memset(&l5_data, 0, sizeof(l5_data));
  1814. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1815. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1816. return ret;
  1817. }
  1818. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1819. {
  1820. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1821. union l5cm_specific_data l5_data;
  1822. int ret;
  1823. memset(&l5_data, 0, sizeof(l5_data));
  1824. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1825. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1826. return ret;
  1827. }
  1828. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1829. {
  1830. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1831. struct l4_kcq kcqe;
  1832. struct kcqe *cqes[1];
  1833. memset(&kcqe, 0, sizeof(kcqe));
  1834. kcqe.pg_host_opaque = req->host_opaque;
  1835. kcqe.pg_cid = req->host_opaque;
  1836. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1837. cqes[0] = (struct kcqe *) &kcqe;
  1838. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1839. return 0;
  1840. }
  1841. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1842. {
  1843. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1844. struct l4_kcq kcqe;
  1845. struct kcqe *cqes[1];
  1846. memset(&kcqe, 0, sizeof(kcqe));
  1847. kcqe.pg_host_opaque = req->pg_host_opaque;
  1848. kcqe.pg_cid = req->pg_cid;
  1849. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1850. cqes[0] = (struct kcqe *) &kcqe;
  1851. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1852. return 0;
  1853. }
  1854. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1855. {
  1856. struct fcoe_kwqe_stat *req;
  1857. struct fcoe_stat_ramrod_params *fcoe_stat;
  1858. union l5cm_specific_data l5_data;
  1859. struct cnic_local *cp = dev->cnic_priv;
  1860. int ret;
  1861. u32 cid;
  1862. req = (struct fcoe_kwqe_stat *) kwqe;
  1863. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1864. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1865. if (!fcoe_stat)
  1866. return -ENOMEM;
  1867. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1868. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1869. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1870. FCOE_CONNECTION_TYPE, &l5_data);
  1871. return ret;
  1872. }
  1873. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1874. u32 num, int *work)
  1875. {
  1876. int ret;
  1877. struct cnic_local *cp = dev->cnic_priv;
  1878. u32 cid;
  1879. struct fcoe_init_ramrod_params *fcoe_init;
  1880. struct fcoe_kwqe_init1 *req1;
  1881. struct fcoe_kwqe_init2 *req2;
  1882. struct fcoe_kwqe_init3 *req3;
  1883. union l5cm_specific_data l5_data;
  1884. if (num < 3) {
  1885. *work = num;
  1886. return -EINVAL;
  1887. }
  1888. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1889. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1890. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1891. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1892. *work = 1;
  1893. return -EINVAL;
  1894. }
  1895. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1896. *work = 2;
  1897. return -EINVAL;
  1898. }
  1899. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1900. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1901. return -ENOMEM;
  1902. }
  1903. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1904. if (!fcoe_init)
  1905. return -ENOMEM;
  1906. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1907. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1908. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1909. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1910. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1911. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1912. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1913. fcoe_init->sb_num = cp->status_blk_num;
  1914. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1915. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1916. cp->kcq2.sw_prod_idx = 0;
  1917. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1918. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1919. FCOE_CONNECTION_TYPE, &l5_data);
  1920. *work = 3;
  1921. return ret;
  1922. }
  1923. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1924. u32 num, int *work)
  1925. {
  1926. int ret = 0;
  1927. u32 cid = -1, l5_cid;
  1928. struct cnic_local *cp = dev->cnic_priv;
  1929. struct fcoe_kwqe_conn_offload1 *req1;
  1930. struct fcoe_kwqe_conn_offload2 *req2;
  1931. struct fcoe_kwqe_conn_offload3 *req3;
  1932. struct fcoe_kwqe_conn_offload4 *req4;
  1933. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1934. struct cnic_context *ctx;
  1935. struct fcoe_context *fctx;
  1936. struct regpair ctx_addr;
  1937. union l5cm_specific_data l5_data;
  1938. struct fcoe_kcqe kcqe;
  1939. struct kcqe *cqes[1];
  1940. if (num < 4) {
  1941. *work = num;
  1942. return -EINVAL;
  1943. }
  1944. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1945. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1946. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1947. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1948. *work = 4;
  1949. l5_cid = req1->fcoe_conn_id;
  1950. if (l5_cid >= dev->max_fcoe_conn)
  1951. goto err_reply;
  1952. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1953. ctx = &cp->ctx_tbl[l5_cid];
  1954. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1955. goto err_reply;
  1956. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1957. if (ret) {
  1958. ret = 0;
  1959. goto err_reply;
  1960. }
  1961. cid = ctx->cid;
  1962. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1963. if (fctx) {
  1964. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1965. u32 val;
  1966. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1967. FCOE_CONNECTION_TYPE);
  1968. fctx->xstorm_ag_context.cdu_reserved = val;
  1969. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1970. FCOE_CONNECTION_TYPE);
  1971. fctx->ustorm_ag_context.cdu_usage = val;
  1972. }
  1973. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1974. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1975. goto err_reply;
  1976. }
  1977. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1978. if (!fcoe_offload)
  1979. goto err_reply;
  1980. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1981. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1982. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1983. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1984. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1985. cid = BNX2X_HW_CID(cp, cid);
  1986. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1987. FCOE_CONNECTION_TYPE, &l5_data);
  1988. if (!ret)
  1989. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1990. return ret;
  1991. err_reply:
  1992. if (cid != -1)
  1993. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1994. memset(&kcqe, 0, sizeof(kcqe));
  1995. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1996. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1997. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1998. cqes[0] = (struct kcqe *) &kcqe;
  1999. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2000. return ret;
  2001. }
  2002. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  2003. {
  2004. struct fcoe_kwqe_conn_enable_disable *req;
  2005. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  2006. union l5cm_specific_data l5_data;
  2007. int ret;
  2008. u32 cid, l5_cid;
  2009. struct cnic_local *cp = dev->cnic_priv;
  2010. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2011. cid = req->context_id;
  2012. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  2013. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  2014. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  2015. return -ENOMEM;
  2016. }
  2017. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2018. if (!fcoe_enable)
  2019. return -ENOMEM;
  2020. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  2021. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  2022. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  2023. FCOE_CONNECTION_TYPE, &l5_data);
  2024. return ret;
  2025. }
  2026. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  2027. {
  2028. struct fcoe_kwqe_conn_enable_disable *req;
  2029. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  2030. union l5cm_specific_data l5_data;
  2031. int ret;
  2032. u32 cid, l5_cid;
  2033. struct cnic_local *cp = dev->cnic_priv;
  2034. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2035. cid = req->context_id;
  2036. l5_cid = req->conn_id;
  2037. if (l5_cid >= dev->max_fcoe_conn)
  2038. return -EINVAL;
  2039. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2040. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2041. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2042. return -ENOMEM;
  2043. }
  2044. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2045. if (!fcoe_disable)
  2046. return -ENOMEM;
  2047. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2048. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2049. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2050. FCOE_CONNECTION_TYPE, &l5_data);
  2051. return ret;
  2052. }
  2053. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2054. {
  2055. struct fcoe_kwqe_conn_destroy *req;
  2056. union l5cm_specific_data l5_data;
  2057. int ret;
  2058. u32 cid, l5_cid;
  2059. struct cnic_local *cp = dev->cnic_priv;
  2060. struct cnic_context *ctx;
  2061. struct fcoe_kcqe kcqe;
  2062. struct kcqe *cqes[1];
  2063. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2064. cid = req->context_id;
  2065. l5_cid = req->conn_id;
  2066. if (l5_cid >= dev->max_fcoe_conn)
  2067. return -EINVAL;
  2068. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2069. ctx = &cp->ctx_tbl[l5_cid];
  2070. init_waitqueue_head(&ctx->waitq);
  2071. ctx->wait_cond = 0;
  2072. memset(&kcqe, 0, sizeof(kcqe));
  2073. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2074. memset(&l5_data, 0, sizeof(l5_data));
  2075. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2076. FCOE_CONNECTION_TYPE, &l5_data);
  2077. if (ret == 0) {
  2078. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2079. if (ctx->wait_cond)
  2080. kcqe.completion_status = 0;
  2081. }
  2082. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2083. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2084. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2085. kcqe.fcoe_conn_id = req->conn_id;
  2086. kcqe.fcoe_conn_context_id = cid;
  2087. cqes[0] = (struct kcqe *) &kcqe;
  2088. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2089. return ret;
  2090. }
  2091. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2092. {
  2093. struct cnic_local *cp = dev->cnic_priv;
  2094. u32 i;
  2095. for (i = start_cid; i < cp->max_cid_space; i++) {
  2096. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2097. int j;
  2098. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2099. msleep(10);
  2100. for (j = 0; j < 5; j++) {
  2101. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2102. break;
  2103. msleep(20);
  2104. }
  2105. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2106. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2107. ctx->cid);
  2108. }
  2109. }
  2110. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2111. {
  2112. struct fcoe_kwqe_destroy *req;
  2113. union l5cm_specific_data l5_data;
  2114. struct cnic_local *cp = dev->cnic_priv;
  2115. int ret;
  2116. u32 cid;
  2117. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2118. req = (struct fcoe_kwqe_destroy *) kwqe;
  2119. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2120. memset(&l5_data, 0, sizeof(l5_data));
  2121. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2122. FCOE_CONNECTION_TYPE, &l5_data);
  2123. return ret;
  2124. }
  2125. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2126. {
  2127. struct cnic_local *cp = dev->cnic_priv;
  2128. struct kcqe kcqe;
  2129. struct kcqe *cqes[1];
  2130. u32 cid;
  2131. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2132. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2133. u32 kcqe_op;
  2134. int ulp_type;
  2135. cid = kwqe->kwqe_info0;
  2136. memset(&kcqe, 0, sizeof(kcqe));
  2137. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2138. u32 l5_cid = 0;
  2139. ulp_type = CNIC_ULP_FCOE;
  2140. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2141. struct fcoe_kwqe_conn_enable_disable *req;
  2142. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2143. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2144. cid = req->context_id;
  2145. l5_cid = req->conn_id;
  2146. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2147. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2148. } else {
  2149. return;
  2150. }
  2151. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2152. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2153. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2154. kcqe.kcqe_info2 = cid;
  2155. kcqe.kcqe_info0 = l5_cid;
  2156. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2157. ulp_type = CNIC_ULP_ISCSI;
  2158. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2159. cid = kwqe->kwqe_info1;
  2160. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2161. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2162. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2163. kcqe.kcqe_info2 = cid;
  2164. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2165. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2166. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2167. ulp_type = CNIC_ULP_L4;
  2168. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2169. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2170. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2171. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2172. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2173. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2174. else
  2175. return;
  2176. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2177. KCQE_FLAGS_LAYER_MASK_L4;
  2178. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2179. l4kcqe->cid = cid;
  2180. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2181. } else {
  2182. return;
  2183. }
  2184. cqes[0] = &kcqe;
  2185. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2186. }
  2187. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2188. struct kwqe *wqes[], u32 num_wqes)
  2189. {
  2190. int i, work, ret;
  2191. u32 opcode;
  2192. struct kwqe *kwqe;
  2193. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2194. return -EAGAIN; /* bnx2 is down */
  2195. for (i = 0; i < num_wqes; ) {
  2196. kwqe = wqes[i];
  2197. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2198. work = 1;
  2199. switch (opcode) {
  2200. case ISCSI_KWQE_OPCODE_INIT1:
  2201. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2202. break;
  2203. case ISCSI_KWQE_OPCODE_INIT2:
  2204. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2205. break;
  2206. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2207. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2208. num_wqes - i, &work);
  2209. break;
  2210. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2211. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2212. break;
  2213. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2214. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2215. break;
  2216. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2217. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2218. &work);
  2219. break;
  2220. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2221. ret = cnic_bnx2x_close(dev, kwqe);
  2222. break;
  2223. case L4_KWQE_OPCODE_VALUE_RESET:
  2224. ret = cnic_bnx2x_reset(dev, kwqe);
  2225. break;
  2226. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2227. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2228. break;
  2229. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2230. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2231. break;
  2232. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2233. ret = 0;
  2234. break;
  2235. default:
  2236. ret = 0;
  2237. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2238. opcode);
  2239. break;
  2240. }
  2241. if (ret < 0) {
  2242. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2243. opcode);
  2244. /* Possibly bnx2x parity error, send completion
  2245. * to ulp drivers with error code to speed up
  2246. * cleanup and reset recovery.
  2247. */
  2248. if (ret == -EIO || ret == -EAGAIN)
  2249. cnic_bnx2x_kwqe_err(dev, kwqe);
  2250. }
  2251. i += work;
  2252. }
  2253. return 0;
  2254. }
  2255. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2256. struct kwqe *wqes[], u32 num_wqes)
  2257. {
  2258. struct cnic_local *cp = dev->cnic_priv;
  2259. int i, work, ret;
  2260. u32 opcode;
  2261. struct kwqe *kwqe;
  2262. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2263. return -EAGAIN; /* bnx2 is down */
  2264. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2265. return -EINVAL;
  2266. for (i = 0; i < num_wqes; ) {
  2267. kwqe = wqes[i];
  2268. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2269. work = 1;
  2270. switch (opcode) {
  2271. case FCOE_KWQE_OPCODE_INIT1:
  2272. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2273. num_wqes - i, &work);
  2274. break;
  2275. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2276. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2277. num_wqes - i, &work);
  2278. break;
  2279. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2280. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2281. break;
  2282. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2283. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2284. break;
  2285. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2286. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2287. break;
  2288. case FCOE_KWQE_OPCODE_DESTROY:
  2289. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2290. break;
  2291. case FCOE_KWQE_OPCODE_STAT:
  2292. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2293. break;
  2294. default:
  2295. ret = 0;
  2296. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2297. opcode);
  2298. break;
  2299. }
  2300. if (ret < 0) {
  2301. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2302. opcode);
  2303. /* Possibly bnx2x parity error, send completion
  2304. * to ulp drivers with error code to speed up
  2305. * cleanup and reset recovery.
  2306. */
  2307. if (ret == -EIO || ret == -EAGAIN)
  2308. cnic_bnx2x_kwqe_err(dev, kwqe);
  2309. }
  2310. i += work;
  2311. }
  2312. return 0;
  2313. }
  2314. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2315. u32 num_wqes)
  2316. {
  2317. int ret = -EINVAL;
  2318. u32 layer_code;
  2319. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2320. return -EAGAIN; /* bnx2x is down */
  2321. if (!num_wqes)
  2322. return 0;
  2323. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2324. switch (layer_code) {
  2325. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2326. case KWQE_FLAGS_LAYER_MASK_L4:
  2327. case KWQE_FLAGS_LAYER_MASK_L2:
  2328. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2329. break;
  2330. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2331. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2332. break;
  2333. }
  2334. return ret;
  2335. }
  2336. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2337. {
  2338. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2339. return KCQE_FLAGS_LAYER_MASK_L4;
  2340. return opflag & KCQE_FLAGS_LAYER_MASK;
  2341. }
  2342. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2343. {
  2344. struct cnic_local *cp = dev->cnic_priv;
  2345. int i, j, comp = 0;
  2346. i = 0;
  2347. j = 1;
  2348. while (num_cqes) {
  2349. struct cnic_ulp_ops *ulp_ops;
  2350. int ulp_type;
  2351. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2352. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2353. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2354. comp++;
  2355. while (j < num_cqes) {
  2356. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2357. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2358. break;
  2359. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2360. comp++;
  2361. j++;
  2362. }
  2363. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2364. ulp_type = CNIC_ULP_RDMA;
  2365. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2366. ulp_type = CNIC_ULP_ISCSI;
  2367. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2368. ulp_type = CNIC_ULP_FCOE;
  2369. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2370. ulp_type = CNIC_ULP_L4;
  2371. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2372. goto end;
  2373. else {
  2374. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2375. kcqe_op_flag);
  2376. goto end;
  2377. }
  2378. rcu_read_lock();
  2379. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2380. if (likely(ulp_ops)) {
  2381. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2382. cp->completed_kcq + i, j);
  2383. }
  2384. rcu_read_unlock();
  2385. end:
  2386. num_cqes -= j;
  2387. i += j;
  2388. j = 1;
  2389. }
  2390. if (unlikely(comp))
  2391. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2392. }
  2393. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2394. {
  2395. struct cnic_local *cp = dev->cnic_priv;
  2396. u16 i, ri, hw_prod, last;
  2397. struct kcqe *kcqe;
  2398. int kcqe_cnt = 0, last_cnt = 0;
  2399. i = ri = last = info->sw_prod_idx;
  2400. ri &= MAX_KCQ_IDX;
  2401. hw_prod = *info->hw_prod_idx_ptr;
  2402. hw_prod = info->hw_idx(hw_prod);
  2403. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2404. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2405. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2406. i = info->next_idx(i);
  2407. ri = i & MAX_KCQ_IDX;
  2408. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2409. last_cnt = kcqe_cnt;
  2410. last = i;
  2411. }
  2412. }
  2413. info->sw_prod_idx = last;
  2414. return last_cnt;
  2415. }
  2416. static int cnic_l2_completion(struct cnic_local *cp)
  2417. {
  2418. u16 hw_cons, sw_cons;
  2419. struct cnic_uio_dev *udev = cp->udev;
  2420. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2421. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2422. u32 cmd;
  2423. int comp = 0;
  2424. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2425. return 0;
  2426. hw_cons = *cp->rx_cons_ptr;
  2427. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2428. hw_cons++;
  2429. sw_cons = cp->rx_cons;
  2430. while (sw_cons != hw_cons) {
  2431. u8 cqe_fp_flags;
  2432. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2433. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2434. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2435. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2436. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2437. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2438. cmd == RAMROD_CMD_ID_ETH_HALT)
  2439. comp++;
  2440. }
  2441. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2442. }
  2443. return comp;
  2444. }
  2445. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2446. {
  2447. u16 rx_cons, tx_cons;
  2448. int comp = 0;
  2449. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2450. return;
  2451. rx_cons = *cp->rx_cons_ptr;
  2452. tx_cons = *cp->tx_cons_ptr;
  2453. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2454. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2455. comp = cnic_l2_completion(cp);
  2456. cp->tx_cons = tx_cons;
  2457. cp->rx_cons = rx_cons;
  2458. if (cp->udev)
  2459. uio_event_notify(&cp->udev->cnic_uinfo);
  2460. }
  2461. if (comp)
  2462. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2463. }
  2464. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2465. {
  2466. struct cnic_local *cp = dev->cnic_priv;
  2467. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2468. int kcqe_cnt;
  2469. /* status block index must be read before reading other fields */
  2470. rmb();
  2471. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2472. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2473. service_kcqes(dev, kcqe_cnt);
  2474. /* Tell compiler that status_blk fields can change. */
  2475. barrier();
  2476. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2477. /* status block index must be read first */
  2478. rmb();
  2479. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2480. }
  2481. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2482. cnic_chk_pkt_rings(cp);
  2483. return status_idx;
  2484. }
  2485. static int cnic_service_bnx2(void *data, void *status_blk)
  2486. {
  2487. struct cnic_dev *dev = data;
  2488. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2489. struct status_block *sblk = status_blk;
  2490. return sblk->status_idx;
  2491. }
  2492. return cnic_service_bnx2_queues(dev);
  2493. }
  2494. static void cnic_service_bnx2_msix(unsigned long data)
  2495. {
  2496. struct cnic_dev *dev = (struct cnic_dev *) data;
  2497. struct cnic_local *cp = dev->cnic_priv;
  2498. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2499. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2500. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2501. }
  2502. static void cnic_doirq(struct cnic_dev *dev)
  2503. {
  2504. struct cnic_local *cp = dev->cnic_priv;
  2505. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2506. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2507. prefetch(cp->status_blk.gen);
  2508. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2509. tasklet_schedule(&cp->cnic_irq_task);
  2510. }
  2511. }
  2512. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2513. {
  2514. struct cnic_dev *dev = dev_instance;
  2515. struct cnic_local *cp = dev->cnic_priv;
  2516. if (cp->ack_int)
  2517. cp->ack_int(dev);
  2518. cnic_doirq(dev);
  2519. return IRQ_HANDLED;
  2520. }
  2521. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2522. u16 index, u8 op, u8 update)
  2523. {
  2524. struct cnic_local *cp = dev->cnic_priv;
  2525. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2526. COMMAND_REG_INT_ACK);
  2527. struct igu_ack_register igu_ack;
  2528. igu_ack.status_block_index = index;
  2529. igu_ack.sb_id_and_flags =
  2530. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2531. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2532. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2533. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2534. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2535. }
  2536. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2537. u16 index, u8 op, u8 update)
  2538. {
  2539. struct igu_regular cmd_data;
  2540. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2541. cmd_data.sb_id_and_flags =
  2542. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2543. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2544. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2545. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2546. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2547. }
  2548. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2549. {
  2550. struct cnic_local *cp = dev->cnic_priv;
  2551. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2552. IGU_INT_DISABLE, 0);
  2553. }
  2554. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2555. {
  2556. struct cnic_local *cp = dev->cnic_priv;
  2557. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2558. IGU_INT_DISABLE, 0);
  2559. }
  2560. static void cnic_arm_bnx2x_msix(struct cnic_dev *dev, u32 idx)
  2561. {
  2562. struct cnic_local *cp = dev->cnic_priv;
  2563. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, idx,
  2564. IGU_INT_ENABLE, 1);
  2565. }
  2566. static void cnic_arm_bnx2x_e2_msix(struct cnic_dev *dev, u32 idx)
  2567. {
  2568. struct cnic_local *cp = dev->cnic_priv;
  2569. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, idx,
  2570. IGU_INT_ENABLE, 1);
  2571. }
  2572. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2573. {
  2574. u32 last_status = *info->status_idx_ptr;
  2575. int kcqe_cnt;
  2576. /* status block index must be read before reading the KCQ */
  2577. rmb();
  2578. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2579. service_kcqes(dev, kcqe_cnt);
  2580. /* Tell compiler that sblk fields can change. */
  2581. barrier();
  2582. last_status = *info->status_idx_ptr;
  2583. /* status block index must be read before reading the KCQ */
  2584. rmb();
  2585. }
  2586. return last_status;
  2587. }
  2588. static void cnic_service_bnx2x_bh(unsigned long data)
  2589. {
  2590. struct cnic_dev *dev = (struct cnic_dev *) data;
  2591. struct cnic_local *cp = dev->cnic_priv;
  2592. u32 status_idx, new_status_idx;
  2593. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2594. return;
  2595. while (1) {
  2596. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2597. CNIC_WR16(dev, cp->kcq1.io_addr,
  2598. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2599. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE) {
  2600. cp->arm_int(dev, status_idx);
  2601. break;
  2602. }
  2603. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2604. if (new_status_idx != status_idx)
  2605. continue;
  2606. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2607. MAX_KCQ_IDX);
  2608. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2609. status_idx, IGU_INT_ENABLE, 1);
  2610. break;
  2611. }
  2612. }
  2613. static int cnic_service_bnx2x(void *data, void *status_blk)
  2614. {
  2615. struct cnic_dev *dev = data;
  2616. struct cnic_local *cp = dev->cnic_priv;
  2617. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2618. cnic_doirq(dev);
  2619. cnic_chk_pkt_rings(cp);
  2620. return 0;
  2621. }
  2622. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2623. {
  2624. struct cnic_ulp_ops *ulp_ops;
  2625. if (if_type == CNIC_ULP_ISCSI)
  2626. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2627. mutex_lock(&cnic_lock);
  2628. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2629. lockdep_is_held(&cnic_lock));
  2630. if (!ulp_ops) {
  2631. mutex_unlock(&cnic_lock);
  2632. return;
  2633. }
  2634. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2635. mutex_unlock(&cnic_lock);
  2636. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2637. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2638. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2639. }
  2640. static void cnic_ulp_stop(struct cnic_dev *dev)
  2641. {
  2642. struct cnic_local *cp = dev->cnic_priv;
  2643. int if_type;
  2644. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2645. cnic_ulp_stop_one(cp, if_type);
  2646. }
  2647. static void cnic_ulp_start(struct cnic_dev *dev)
  2648. {
  2649. struct cnic_local *cp = dev->cnic_priv;
  2650. int if_type;
  2651. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2652. struct cnic_ulp_ops *ulp_ops;
  2653. mutex_lock(&cnic_lock);
  2654. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2655. lockdep_is_held(&cnic_lock));
  2656. if (!ulp_ops || !ulp_ops->cnic_start) {
  2657. mutex_unlock(&cnic_lock);
  2658. continue;
  2659. }
  2660. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2661. mutex_unlock(&cnic_lock);
  2662. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2663. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2664. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2665. }
  2666. }
  2667. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2668. {
  2669. struct cnic_local *cp = dev->cnic_priv;
  2670. struct cnic_ulp_ops *ulp_ops;
  2671. int rc;
  2672. mutex_lock(&cnic_lock);
  2673. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  2674. if (ulp_ops && ulp_ops->cnic_get_stats)
  2675. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2676. else
  2677. rc = -ENODEV;
  2678. mutex_unlock(&cnic_lock);
  2679. return rc;
  2680. }
  2681. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2682. {
  2683. struct cnic_dev *dev = data;
  2684. int ulp_type = CNIC_ULP_ISCSI;
  2685. switch (info->cmd) {
  2686. case CNIC_CTL_STOP_CMD:
  2687. cnic_hold(dev);
  2688. cnic_ulp_stop(dev);
  2689. cnic_stop_hw(dev);
  2690. cnic_put(dev);
  2691. break;
  2692. case CNIC_CTL_START_CMD:
  2693. cnic_hold(dev);
  2694. if (!cnic_start_hw(dev))
  2695. cnic_ulp_start(dev);
  2696. cnic_put(dev);
  2697. break;
  2698. case CNIC_CTL_STOP_ISCSI_CMD: {
  2699. struct cnic_local *cp = dev->cnic_priv;
  2700. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2701. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2702. break;
  2703. }
  2704. case CNIC_CTL_COMPLETION_CMD: {
  2705. struct cnic_ctl_completion *comp = &info->data.comp;
  2706. u32 cid = BNX2X_SW_CID(comp->cid);
  2707. u32 l5_cid;
  2708. struct cnic_local *cp = dev->cnic_priv;
  2709. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2710. break;
  2711. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2712. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2713. if (unlikely(comp->error)) {
  2714. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2715. netdev_err(dev->netdev,
  2716. "CID %x CFC delete comp error %x\n",
  2717. cid, comp->error);
  2718. }
  2719. ctx->wait_cond = 1;
  2720. wake_up(&ctx->waitq);
  2721. }
  2722. break;
  2723. }
  2724. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2725. ulp_type = CNIC_ULP_FCOE;
  2726. /* fall through */
  2727. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2728. cnic_hold(dev);
  2729. cnic_copy_ulp_stats(dev, ulp_type);
  2730. cnic_put(dev);
  2731. break;
  2732. default:
  2733. return -EINVAL;
  2734. }
  2735. return 0;
  2736. }
  2737. static void cnic_ulp_init(struct cnic_dev *dev)
  2738. {
  2739. int i;
  2740. struct cnic_local *cp = dev->cnic_priv;
  2741. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2742. struct cnic_ulp_ops *ulp_ops;
  2743. mutex_lock(&cnic_lock);
  2744. ulp_ops = cnic_ulp_tbl_prot(i);
  2745. if (!ulp_ops || !ulp_ops->cnic_init) {
  2746. mutex_unlock(&cnic_lock);
  2747. continue;
  2748. }
  2749. ulp_get(ulp_ops);
  2750. mutex_unlock(&cnic_lock);
  2751. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2752. ulp_ops->cnic_init(dev);
  2753. ulp_put(ulp_ops);
  2754. }
  2755. }
  2756. static void cnic_ulp_exit(struct cnic_dev *dev)
  2757. {
  2758. int i;
  2759. struct cnic_local *cp = dev->cnic_priv;
  2760. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2761. struct cnic_ulp_ops *ulp_ops;
  2762. mutex_lock(&cnic_lock);
  2763. ulp_ops = cnic_ulp_tbl_prot(i);
  2764. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2765. mutex_unlock(&cnic_lock);
  2766. continue;
  2767. }
  2768. ulp_get(ulp_ops);
  2769. mutex_unlock(&cnic_lock);
  2770. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2771. ulp_ops->cnic_exit(dev);
  2772. ulp_put(ulp_ops);
  2773. }
  2774. }
  2775. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2776. {
  2777. struct cnic_dev *dev = csk->dev;
  2778. struct l4_kwq_offload_pg *l4kwqe;
  2779. struct kwqe *wqes[1];
  2780. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2781. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2782. wqes[0] = (struct kwqe *) l4kwqe;
  2783. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2784. l4kwqe->flags =
  2785. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2786. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2787. l4kwqe->da0 = csk->ha[0];
  2788. l4kwqe->da1 = csk->ha[1];
  2789. l4kwqe->da2 = csk->ha[2];
  2790. l4kwqe->da3 = csk->ha[3];
  2791. l4kwqe->da4 = csk->ha[4];
  2792. l4kwqe->da5 = csk->ha[5];
  2793. l4kwqe->sa0 = dev->mac_addr[0];
  2794. l4kwqe->sa1 = dev->mac_addr[1];
  2795. l4kwqe->sa2 = dev->mac_addr[2];
  2796. l4kwqe->sa3 = dev->mac_addr[3];
  2797. l4kwqe->sa4 = dev->mac_addr[4];
  2798. l4kwqe->sa5 = dev->mac_addr[5];
  2799. l4kwqe->etype = ETH_P_IP;
  2800. l4kwqe->ipid_start = DEF_IPID_START;
  2801. l4kwqe->host_opaque = csk->l5_cid;
  2802. if (csk->vlan_id) {
  2803. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2804. l4kwqe->vlan_tag = csk->vlan_id;
  2805. l4kwqe->l2hdr_nbytes += 4;
  2806. }
  2807. return dev->submit_kwqes(dev, wqes, 1);
  2808. }
  2809. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2810. {
  2811. struct cnic_dev *dev = csk->dev;
  2812. struct l4_kwq_update_pg *l4kwqe;
  2813. struct kwqe *wqes[1];
  2814. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2815. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2816. wqes[0] = (struct kwqe *) l4kwqe;
  2817. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2818. l4kwqe->flags =
  2819. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2820. l4kwqe->pg_cid = csk->pg_cid;
  2821. l4kwqe->da0 = csk->ha[0];
  2822. l4kwqe->da1 = csk->ha[1];
  2823. l4kwqe->da2 = csk->ha[2];
  2824. l4kwqe->da3 = csk->ha[3];
  2825. l4kwqe->da4 = csk->ha[4];
  2826. l4kwqe->da5 = csk->ha[5];
  2827. l4kwqe->pg_host_opaque = csk->l5_cid;
  2828. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2829. return dev->submit_kwqes(dev, wqes, 1);
  2830. }
  2831. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2832. {
  2833. struct cnic_dev *dev = csk->dev;
  2834. struct l4_kwq_upload *l4kwqe;
  2835. struct kwqe *wqes[1];
  2836. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2837. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2838. wqes[0] = (struct kwqe *) l4kwqe;
  2839. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2840. l4kwqe->flags =
  2841. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2842. l4kwqe->cid = csk->pg_cid;
  2843. return dev->submit_kwqes(dev, wqes, 1);
  2844. }
  2845. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2846. {
  2847. struct cnic_dev *dev = csk->dev;
  2848. struct l4_kwq_connect_req1 *l4kwqe1;
  2849. struct l4_kwq_connect_req2 *l4kwqe2;
  2850. struct l4_kwq_connect_req3 *l4kwqe3;
  2851. struct kwqe *wqes[3];
  2852. u8 tcp_flags = 0;
  2853. int num_wqes = 2;
  2854. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2855. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2856. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2857. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2858. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2859. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2860. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2861. l4kwqe3->flags =
  2862. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2863. l4kwqe3->ka_timeout = csk->ka_timeout;
  2864. l4kwqe3->ka_interval = csk->ka_interval;
  2865. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2866. l4kwqe3->tos = csk->tos;
  2867. l4kwqe3->ttl = csk->ttl;
  2868. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2869. l4kwqe3->pmtu = csk->mtu;
  2870. l4kwqe3->rcv_buf = csk->rcv_buf;
  2871. l4kwqe3->snd_buf = csk->snd_buf;
  2872. l4kwqe3->seed = csk->seed;
  2873. wqes[0] = (struct kwqe *) l4kwqe1;
  2874. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2875. wqes[1] = (struct kwqe *) l4kwqe2;
  2876. wqes[2] = (struct kwqe *) l4kwqe3;
  2877. num_wqes = 3;
  2878. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2879. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2880. l4kwqe2->flags =
  2881. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2882. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2883. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2884. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2885. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2886. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2887. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2888. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2889. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2890. sizeof(struct tcphdr);
  2891. } else {
  2892. wqes[1] = (struct kwqe *) l4kwqe3;
  2893. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2894. sizeof(struct tcphdr);
  2895. }
  2896. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2897. l4kwqe1->flags =
  2898. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2899. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2900. l4kwqe1->cid = csk->cid;
  2901. l4kwqe1->pg_cid = csk->pg_cid;
  2902. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2903. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2904. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2905. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2906. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2907. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2908. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2909. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2910. if (csk->tcp_flags & SK_TCP_NAGLE)
  2911. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2912. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2913. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2914. if (csk->tcp_flags & SK_TCP_SACK)
  2915. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2916. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2917. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2918. l4kwqe1->tcp_flags = tcp_flags;
  2919. return dev->submit_kwqes(dev, wqes, num_wqes);
  2920. }
  2921. static int cnic_cm_close_req(struct cnic_sock *csk)
  2922. {
  2923. struct cnic_dev *dev = csk->dev;
  2924. struct l4_kwq_close_req *l4kwqe;
  2925. struct kwqe *wqes[1];
  2926. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2927. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2928. wqes[0] = (struct kwqe *) l4kwqe;
  2929. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2930. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2931. l4kwqe->cid = csk->cid;
  2932. return dev->submit_kwqes(dev, wqes, 1);
  2933. }
  2934. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2935. {
  2936. struct cnic_dev *dev = csk->dev;
  2937. struct l4_kwq_reset_req *l4kwqe;
  2938. struct kwqe *wqes[1];
  2939. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2940. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2941. wqes[0] = (struct kwqe *) l4kwqe;
  2942. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2943. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2944. l4kwqe->cid = csk->cid;
  2945. return dev->submit_kwqes(dev, wqes, 1);
  2946. }
  2947. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2948. u32 l5_cid, struct cnic_sock **csk, void *context)
  2949. {
  2950. struct cnic_local *cp = dev->cnic_priv;
  2951. struct cnic_sock *csk1;
  2952. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2953. return -EINVAL;
  2954. if (cp->ctx_tbl) {
  2955. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2956. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2957. return -EAGAIN;
  2958. }
  2959. csk1 = &cp->csk_tbl[l5_cid];
  2960. if (atomic_read(&csk1->ref_count))
  2961. return -EAGAIN;
  2962. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2963. return -EBUSY;
  2964. csk1->dev = dev;
  2965. csk1->cid = cid;
  2966. csk1->l5_cid = l5_cid;
  2967. csk1->ulp_type = ulp_type;
  2968. csk1->context = context;
  2969. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2970. csk1->ka_interval = DEF_KA_INTERVAL;
  2971. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2972. csk1->tos = DEF_TOS;
  2973. csk1->ttl = DEF_TTL;
  2974. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2975. csk1->rcv_buf = DEF_RCV_BUF;
  2976. csk1->snd_buf = DEF_SND_BUF;
  2977. csk1->seed = DEF_SEED;
  2978. *csk = csk1;
  2979. return 0;
  2980. }
  2981. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2982. {
  2983. if (csk->src_port) {
  2984. struct cnic_dev *dev = csk->dev;
  2985. struct cnic_local *cp = dev->cnic_priv;
  2986. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2987. csk->src_port = 0;
  2988. }
  2989. }
  2990. static void cnic_close_conn(struct cnic_sock *csk)
  2991. {
  2992. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2993. cnic_cm_upload_pg(csk);
  2994. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2995. }
  2996. cnic_cm_cleanup(csk);
  2997. }
  2998. static int cnic_cm_destroy(struct cnic_sock *csk)
  2999. {
  3000. if (!cnic_in_use(csk))
  3001. return -EINVAL;
  3002. csk_hold(csk);
  3003. clear_bit(SK_F_INUSE, &csk->flags);
  3004. smp_mb__after_clear_bit();
  3005. while (atomic_read(&csk->ref_count) != 1)
  3006. msleep(1);
  3007. cnic_cm_cleanup(csk);
  3008. csk->flags = 0;
  3009. csk_put(csk);
  3010. return 0;
  3011. }
  3012. static inline u16 cnic_get_vlan(struct net_device *dev,
  3013. struct net_device **vlan_dev)
  3014. {
  3015. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  3016. *vlan_dev = vlan_dev_real_dev(dev);
  3017. return vlan_dev_vlan_id(dev);
  3018. }
  3019. *vlan_dev = dev;
  3020. return 0;
  3021. }
  3022. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  3023. struct dst_entry **dst)
  3024. {
  3025. #if defined(CONFIG_INET)
  3026. struct rtable *rt;
  3027. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  3028. if (!IS_ERR(rt)) {
  3029. *dst = &rt->dst;
  3030. return 0;
  3031. }
  3032. return PTR_ERR(rt);
  3033. #else
  3034. return -ENETUNREACH;
  3035. #endif
  3036. }
  3037. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  3038. struct dst_entry **dst)
  3039. {
  3040. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  3041. struct flowi6 fl6;
  3042. memset(&fl6, 0, sizeof(fl6));
  3043. fl6.daddr = dst_addr->sin6_addr;
  3044. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3045. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3046. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3047. if ((*dst)->error) {
  3048. dst_release(*dst);
  3049. *dst = NULL;
  3050. return -ENETUNREACH;
  3051. } else
  3052. return 0;
  3053. #endif
  3054. return -ENETUNREACH;
  3055. }
  3056. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3057. int ulp_type)
  3058. {
  3059. struct cnic_dev *dev = NULL;
  3060. struct dst_entry *dst;
  3061. struct net_device *netdev = NULL;
  3062. int err = -ENETUNREACH;
  3063. if (dst_addr->sin_family == AF_INET)
  3064. err = cnic_get_v4_route(dst_addr, &dst);
  3065. else if (dst_addr->sin_family == AF_INET6) {
  3066. struct sockaddr_in6 *dst_addr6 =
  3067. (struct sockaddr_in6 *) dst_addr;
  3068. err = cnic_get_v6_route(dst_addr6, &dst);
  3069. } else
  3070. return NULL;
  3071. if (err)
  3072. return NULL;
  3073. if (!dst->dev)
  3074. goto done;
  3075. cnic_get_vlan(dst->dev, &netdev);
  3076. dev = cnic_from_netdev(netdev);
  3077. done:
  3078. dst_release(dst);
  3079. if (dev)
  3080. cnic_put(dev);
  3081. return dev;
  3082. }
  3083. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3084. {
  3085. struct cnic_dev *dev = csk->dev;
  3086. struct cnic_local *cp = dev->cnic_priv;
  3087. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3088. }
  3089. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3090. {
  3091. struct cnic_dev *dev = csk->dev;
  3092. struct cnic_local *cp = dev->cnic_priv;
  3093. int is_v6, rc = 0;
  3094. struct dst_entry *dst = NULL;
  3095. struct net_device *realdev;
  3096. __be16 local_port;
  3097. u32 port_id;
  3098. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3099. saddr->remote.v6.sin6_family == AF_INET6)
  3100. is_v6 = 1;
  3101. else if (saddr->local.v4.sin_family == AF_INET &&
  3102. saddr->remote.v4.sin_family == AF_INET)
  3103. is_v6 = 0;
  3104. else
  3105. return -EINVAL;
  3106. clear_bit(SK_F_IPV6, &csk->flags);
  3107. if (is_v6) {
  3108. set_bit(SK_F_IPV6, &csk->flags);
  3109. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3110. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3111. sizeof(struct in6_addr));
  3112. csk->dst_port = saddr->remote.v6.sin6_port;
  3113. local_port = saddr->local.v6.sin6_port;
  3114. } else {
  3115. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3116. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3117. csk->dst_port = saddr->remote.v4.sin_port;
  3118. local_port = saddr->local.v4.sin_port;
  3119. }
  3120. csk->vlan_id = 0;
  3121. csk->mtu = dev->netdev->mtu;
  3122. if (dst && dst->dev) {
  3123. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3124. if (realdev == dev->netdev) {
  3125. csk->vlan_id = vlan;
  3126. csk->mtu = dst_mtu(dst);
  3127. }
  3128. }
  3129. port_id = be16_to_cpu(local_port);
  3130. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3131. port_id < CNIC_LOCAL_PORT_MAX) {
  3132. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3133. port_id = 0;
  3134. } else
  3135. port_id = 0;
  3136. if (!port_id) {
  3137. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3138. if (port_id == -1) {
  3139. rc = -ENOMEM;
  3140. goto err_out;
  3141. }
  3142. local_port = cpu_to_be16(port_id);
  3143. }
  3144. csk->src_port = local_port;
  3145. err_out:
  3146. dst_release(dst);
  3147. return rc;
  3148. }
  3149. static void cnic_init_csk_state(struct cnic_sock *csk)
  3150. {
  3151. csk->state = 0;
  3152. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3153. clear_bit(SK_F_CLOSING, &csk->flags);
  3154. }
  3155. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3156. {
  3157. struct cnic_local *cp = csk->dev->cnic_priv;
  3158. int err = 0;
  3159. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3160. return -EOPNOTSUPP;
  3161. if (!cnic_in_use(csk))
  3162. return -EINVAL;
  3163. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3164. return -EINVAL;
  3165. cnic_init_csk_state(csk);
  3166. err = cnic_get_route(csk, saddr);
  3167. if (err)
  3168. goto err_out;
  3169. err = cnic_resolve_addr(csk, saddr);
  3170. if (!err)
  3171. return 0;
  3172. err_out:
  3173. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3174. return err;
  3175. }
  3176. static int cnic_cm_abort(struct cnic_sock *csk)
  3177. {
  3178. struct cnic_local *cp = csk->dev->cnic_priv;
  3179. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3180. if (!cnic_in_use(csk))
  3181. return -EINVAL;
  3182. if (cnic_abort_prep(csk))
  3183. return cnic_cm_abort_req(csk);
  3184. /* Getting here means that we haven't started connect, or
  3185. * connect was not successful.
  3186. */
  3187. cp->close_conn(csk, opcode);
  3188. if (csk->state != opcode)
  3189. return -EALREADY;
  3190. return 0;
  3191. }
  3192. static int cnic_cm_close(struct cnic_sock *csk)
  3193. {
  3194. if (!cnic_in_use(csk))
  3195. return -EINVAL;
  3196. if (cnic_close_prep(csk)) {
  3197. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3198. return cnic_cm_close_req(csk);
  3199. } else {
  3200. return -EALREADY;
  3201. }
  3202. return 0;
  3203. }
  3204. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3205. u8 opcode)
  3206. {
  3207. struct cnic_ulp_ops *ulp_ops;
  3208. int ulp_type = csk->ulp_type;
  3209. rcu_read_lock();
  3210. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3211. if (ulp_ops) {
  3212. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3213. ulp_ops->cm_connect_complete(csk);
  3214. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3215. ulp_ops->cm_close_complete(csk);
  3216. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3217. ulp_ops->cm_remote_abort(csk);
  3218. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3219. ulp_ops->cm_abort_complete(csk);
  3220. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3221. ulp_ops->cm_remote_close(csk);
  3222. }
  3223. rcu_read_unlock();
  3224. }
  3225. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3226. {
  3227. if (cnic_offld_prep(csk)) {
  3228. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3229. cnic_cm_update_pg(csk);
  3230. else
  3231. cnic_cm_offload_pg(csk);
  3232. }
  3233. return 0;
  3234. }
  3235. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3236. {
  3237. struct cnic_local *cp = dev->cnic_priv;
  3238. u32 l5_cid = kcqe->pg_host_opaque;
  3239. u8 opcode = kcqe->op_code;
  3240. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3241. csk_hold(csk);
  3242. if (!cnic_in_use(csk))
  3243. goto done;
  3244. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3245. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3246. goto done;
  3247. }
  3248. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3249. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3250. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3251. cnic_cm_upcall(cp, csk,
  3252. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3253. goto done;
  3254. }
  3255. csk->pg_cid = kcqe->pg_cid;
  3256. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3257. cnic_cm_conn_req(csk);
  3258. done:
  3259. csk_put(csk);
  3260. }
  3261. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3262. {
  3263. struct cnic_local *cp = dev->cnic_priv;
  3264. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3265. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3266. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3267. ctx->timestamp = jiffies;
  3268. ctx->wait_cond = 1;
  3269. wake_up(&ctx->waitq);
  3270. }
  3271. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3272. {
  3273. struct cnic_local *cp = dev->cnic_priv;
  3274. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3275. u8 opcode = l4kcqe->op_code;
  3276. u32 l5_cid;
  3277. struct cnic_sock *csk;
  3278. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3279. cnic_process_fcoe_term_conn(dev, kcqe);
  3280. return;
  3281. }
  3282. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3283. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3284. cnic_cm_process_offld_pg(dev, l4kcqe);
  3285. return;
  3286. }
  3287. l5_cid = l4kcqe->conn_id;
  3288. if (opcode & 0x80)
  3289. l5_cid = l4kcqe->cid;
  3290. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3291. return;
  3292. csk = &cp->csk_tbl[l5_cid];
  3293. csk_hold(csk);
  3294. if (!cnic_in_use(csk)) {
  3295. csk_put(csk);
  3296. return;
  3297. }
  3298. switch (opcode) {
  3299. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3300. if (l4kcqe->status != 0) {
  3301. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3302. cnic_cm_upcall(cp, csk,
  3303. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3304. }
  3305. break;
  3306. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3307. if (l4kcqe->status == 0)
  3308. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3309. else if (l4kcqe->status ==
  3310. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3311. set_bit(SK_F_HW_ERR, &csk->flags);
  3312. smp_mb__before_clear_bit();
  3313. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3314. cnic_cm_upcall(cp, csk, opcode);
  3315. break;
  3316. case L5CM_RAMROD_CMD_ID_CLOSE:
  3317. if (l4kcqe->status != 0) {
  3318. netdev_warn(dev->netdev, "RAMROD CLOSE compl with "
  3319. "status 0x%x\n", l4kcqe->status);
  3320. opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3321. /* Fall through */
  3322. } else {
  3323. break;
  3324. }
  3325. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3326. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3327. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3328. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3329. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3330. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3331. set_bit(SK_F_HW_ERR, &csk->flags);
  3332. cp->close_conn(csk, opcode);
  3333. break;
  3334. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3335. /* after we already sent CLOSE_REQ */
  3336. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3337. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3338. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3339. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3340. else
  3341. cnic_cm_upcall(cp, csk, opcode);
  3342. break;
  3343. }
  3344. csk_put(csk);
  3345. }
  3346. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3347. {
  3348. struct cnic_dev *dev = data;
  3349. int i;
  3350. for (i = 0; i < num; i++)
  3351. cnic_cm_process_kcqe(dev, kcqe[i]);
  3352. }
  3353. static struct cnic_ulp_ops cm_ulp_ops = {
  3354. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3355. };
  3356. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3357. {
  3358. struct cnic_local *cp = dev->cnic_priv;
  3359. kfree(cp->csk_tbl);
  3360. cp->csk_tbl = NULL;
  3361. cnic_free_id_tbl(&cp->csk_port_tbl);
  3362. }
  3363. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3364. {
  3365. struct cnic_local *cp = dev->cnic_priv;
  3366. u32 port_id;
  3367. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3368. GFP_KERNEL);
  3369. if (!cp->csk_tbl)
  3370. return -ENOMEM;
  3371. port_id = random32();
  3372. port_id %= CNIC_LOCAL_PORT_RANGE;
  3373. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3374. CNIC_LOCAL_PORT_MIN, port_id)) {
  3375. cnic_cm_free_mem(dev);
  3376. return -ENOMEM;
  3377. }
  3378. return 0;
  3379. }
  3380. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3381. {
  3382. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3383. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3384. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3385. csk->state = opcode;
  3386. }
  3387. /* 1. If event opcode matches the expected event in csk->state
  3388. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3389. * event
  3390. * 3. If the expected event is 0, meaning the connection was never
  3391. * never established, we accept the opcode from cm_abort.
  3392. */
  3393. if (opcode == csk->state || csk->state == 0 ||
  3394. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3395. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3396. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3397. if (csk->state == 0)
  3398. csk->state = opcode;
  3399. return 1;
  3400. }
  3401. }
  3402. return 0;
  3403. }
  3404. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3405. {
  3406. struct cnic_dev *dev = csk->dev;
  3407. struct cnic_local *cp = dev->cnic_priv;
  3408. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3409. cnic_cm_upcall(cp, csk, opcode);
  3410. return;
  3411. }
  3412. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3413. cnic_close_conn(csk);
  3414. csk->state = opcode;
  3415. cnic_cm_upcall(cp, csk, opcode);
  3416. }
  3417. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3418. {
  3419. }
  3420. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3421. {
  3422. u32 seed;
  3423. seed = random32();
  3424. cnic_ctx_wr(dev, 45, 0, seed);
  3425. return 0;
  3426. }
  3427. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3428. {
  3429. struct cnic_dev *dev = csk->dev;
  3430. struct cnic_local *cp = dev->cnic_priv;
  3431. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3432. union l5cm_specific_data l5_data;
  3433. u32 cmd = 0;
  3434. int close_complete = 0;
  3435. switch (opcode) {
  3436. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3437. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3438. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3439. if (cnic_ready_to_close(csk, opcode)) {
  3440. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3441. close_complete = 1;
  3442. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3443. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3444. else
  3445. close_complete = 1;
  3446. }
  3447. break;
  3448. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3449. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3450. break;
  3451. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3452. close_complete = 1;
  3453. break;
  3454. }
  3455. if (cmd) {
  3456. memset(&l5_data, 0, sizeof(l5_data));
  3457. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3458. &l5_data);
  3459. } else if (close_complete) {
  3460. ctx->timestamp = jiffies;
  3461. cnic_close_conn(csk);
  3462. cnic_cm_upcall(cp, csk, csk->state);
  3463. }
  3464. }
  3465. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3466. {
  3467. struct cnic_local *cp = dev->cnic_priv;
  3468. if (!cp->ctx_tbl)
  3469. return;
  3470. if (!netif_running(dev->netdev))
  3471. return;
  3472. cnic_bnx2x_delete_wait(dev, 0);
  3473. cancel_delayed_work(&cp->delete_task);
  3474. flush_workqueue(cnic_wq);
  3475. if (atomic_read(&cp->iscsi_conn) != 0)
  3476. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3477. atomic_read(&cp->iscsi_conn));
  3478. }
  3479. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3480. {
  3481. struct cnic_local *cp = dev->cnic_priv;
  3482. u32 pfid = cp->pfid;
  3483. u32 port = CNIC_PORT(cp);
  3484. cnic_init_bnx2x_mac(dev);
  3485. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3486. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3487. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3488. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3489. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3490. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3491. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3492. DEF_MAX_DA_COUNT);
  3493. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3494. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3495. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3496. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3497. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3498. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3499. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3500. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3501. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3502. DEF_MAX_CWND);
  3503. return 0;
  3504. }
  3505. static void cnic_delete_task(struct work_struct *work)
  3506. {
  3507. struct cnic_local *cp;
  3508. struct cnic_dev *dev;
  3509. u32 i;
  3510. int need_resched = 0;
  3511. cp = container_of(work, struct cnic_local, delete_task.work);
  3512. dev = cp->dev;
  3513. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3514. struct drv_ctl_info info;
  3515. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3516. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3517. cp->ethdev->drv_ctl(dev->netdev, &info);
  3518. }
  3519. for (i = 0; i < cp->max_cid_space; i++) {
  3520. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3521. int err;
  3522. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3523. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3524. continue;
  3525. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3526. need_resched = 1;
  3527. continue;
  3528. }
  3529. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3530. continue;
  3531. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3532. cnic_free_bnx2x_conn_resc(dev, i);
  3533. if (!err) {
  3534. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3535. atomic_dec(&cp->iscsi_conn);
  3536. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3537. }
  3538. }
  3539. if (need_resched)
  3540. queue_delayed_work(cnic_wq, &cp->delete_task,
  3541. msecs_to_jiffies(10));
  3542. }
  3543. static int cnic_cm_open(struct cnic_dev *dev)
  3544. {
  3545. struct cnic_local *cp = dev->cnic_priv;
  3546. int err;
  3547. err = cnic_cm_alloc_mem(dev);
  3548. if (err)
  3549. return err;
  3550. err = cp->start_cm(dev);
  3551. if (err)
  3552. goto err_out;
  3553. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3554. dev->cm_create = cnic_cm_create;
  3555. dev->cm_destroy = cnic_cm_destroy;
  3556. dev->cm_connect = cnic_cm_connect;
  3557. dev->cm_abort = cnic_cm_abort;
  3558. dev->cm_close = cnic_cm_close;
  3559. dev->cm_select_dev = cnic_cm_select_dev;
  3560. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3561. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3562. return 0;
  3563. err_out:
  3564. cnic_cm_free_mem(dev);
  3565. return err;
  3566. }
  3567. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3568. {
  3569. struct cnic_local *cp = dev->cnic_priv;
  3570. int i;
  3571. if (!cp->csk_tbl)
  3572. return 0;
  3573. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3574. struct cnic_sock *csk = &cp->csk_tbl[i];
  3575. clear_bit(SK_F_INUSE, &csk->flags);
  3576. cnic_cm_cleanup(csk);
  3577. }
  3578. cnic_cm_free_mem(dev);
  3579. return 0;
  3580. }
  3581. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3582. {
  3583. u32 cid_addr;
  3584. int i;
  3585. cid_addr = GET_CID_ADDR(cid);
  3586. for (i = 0; i < CTX_SIZE; i += 4)
  3587. cnic_ctx_wr(dev, cid_addr, i, 0);
  3588. }
  3589. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3590. {
  3591. struct cnic_local *cp = dev->cnic_priv;
  3592. int ret = 0, i;
  3593. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3594. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3595. return 0;
  3596. for (i = 0; i < cp->ctx_blks; i++) {
  3597. int j;
  3598. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3599. u32 val;
  3600. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3601. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3602. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3603. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3604. (u64) cp->ctx_arr[i].mapping >> 32);
  3605. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3606. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3607. for (j = 0; j < 10; j++) {
  3608. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3609. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3610. break;
  3611. udelay(5);
  3612. }
  3613. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3614. ret = -EBUSY;
  3615. break;
  3616. }
  3617. }
  3618. return ret;
  3619. }
  3620. static void cnic_free_irq(struct cnic_dev *dev)
  3621. {
  3622. struct cnic_local *cp = dev->cnic_priv;
  3623. struct cnic_eth_dev *ethdev = cp->ethdev;
  3624. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3625. cp->disable_int_sync(dev);
  3626. tasklet_kill(&cp->cnic_irq_task);
  3627. free_irq(ethdev->irq_arr[0].vector, dev);
  3628. }
  3629. }
  3630. static int cnic_request_irq(struct cnic_dev *dev)
  3631. {
  3632. struct cnic_local *cp = dev->cnic_priv;
  3633. struct cnic_eth_dev *ethdev = cp->ethdev;
  3634. int err;
  3635. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3636. if (err)
  3637. tasklet_disable(&cp->cnic_irq_task);
  3638. return err;
  3639. }
  3640. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3641. {
  3642. struct cnic_local *cp = dev->cnic_priv;
  3643. struct cnic_eth_dev *ethdev = cp->ethdev;
  3644. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3645. int err, i = 0;
  3646. int sblk_num = cp->status_blk_num;
  3647. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3648. BNX2_HC_SB_CONFIG_1;
  3649. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3650. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3651. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3652. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3653. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3654. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3655. (unsigned long) dev);
  3656. err = cnic_request_irq(dev);
  3657. if (err)
  3658. return err;
  3659. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3660. i < 10) {
  3661. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3662. 1 << (11 + sblk_num));
  3663. udelay(10);
  3664. i++;
  3665. barrier();
  3666. }
  3667. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3668. cnic_free_irq(dev);
  3669. goto failed;
  3670. }
  3671. } else {
  3672. struct status_block *sblk = cp->status_blk.gen;
  3673. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3674. int i = 0;
  3675. while (sblk->status_completion_producer_index && i < 10) {
  3676. CNIC_WR(dev, BNX2_HC_COMMAND,
  3677. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3678. udelay(10);
  3679. i++;
  3680. barrier();
  3681. }
  3682. if (sblk->status_completion_producer_index)
  3683. goto failed;
  3684. }
  3685. return 0;
  3686. failed:
  3687. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3688. return -EBUSY;
  3689. }
  3690. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3691. {
  3692. struct cnic_local *cp = dev->cnic_priv;
  3693. struct cnic_eth_dev *ethdev = cp->ethdev;
  3694. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3695. return;
  3696. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3697. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3698. }
  3699. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3700. {
  3701. struct cnic_local *cp = dev->cnic_priv;
  3702. struct cnic_eth_dev *ethdev = cp->ethdev;
  3703. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3704. return;
  3705. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3706. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3707. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3708. synchronize_irq(ethdev->irq_arr[0].vector);
  3709. }
  3710. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3711. {
  3712. struct cnic_local *cp = dev->cnic_priv;
  3713. struct cnic_eth_dev *ethdev = cp->ethdev;
  3714. struct cnic_uio_dev *udev = cp->udev;
  3715. u32 cid_addr, tx_cid, sb_id;
  3716. u32 val, offset0, offset1, offset2, offset3;
  3717. int i;
  3718. struct tx_bd *txbd;
  3719. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3720. struct status_block *s_blk = cp->status_blk.gen;
  3721. sb_id = cp->status_blk_num;
  3722. tx_cid = 20;
  3723. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3724. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3725. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3726. tx_cid = TX_TSS_CID + sb_id - 1;
  3727. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3728. (TX_TSS_CID << 7));
  3729. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3730. }
  3731. cp->tx_cons = *cp->tx_cons_ptr;
  3732. cid_addr = GET_CID_ADDR(tx_cid);
  3733. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3734. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3735. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3736. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3737. offset0 = BNX2_L2CTX_TYPE_XI;
  3738. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3739. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3740. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3741. } else {
  3742. cnic_init_context(dev, tx_cid);
  3743. cnic_init_context(dev, tx_cid + 1);
  3744. offset0 = BNX2_L2CTX_TYPE;
  3745. offset1 = BNX2_L2CTX_CMD_TYPE;
  3746. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3747. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3748. }
  3749. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3750. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3751. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3752. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3753. txbd = udev->l2_ring;
  3754. buf_map = udev->l2_buf_map;
  3755. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3756. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3757. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3758. }
  3759. val = (u64) ring_map >> 32;
  3760. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3761. txbd->tx_bd_haddr_hi = val;
  3762. val = (u64) ring_map & 0xffffffff;
  3763. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3764. txbd->tx_bd_haddr_lo = val;
  3765. }
  3766. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3767. {
  3768. struct cnic_local *cp = dev->cnic_priv;
  3769. struct cnic_eth_dev *ethdev = cp->ethdev;
  3770. struct cnic_uio_dev *udev = cp->udev;
  3771. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3772. int i;
  3773. struct rx_bd *rxbd;
  3774. struct status_block *s_blk = cp->status_blk.gen;
  3775. dma_addr_t ring_map = udev->l2_ring_map;
  3776. sb_id = cp->status_blk_num;
  3777. cnic_init_context(dev, 2);
  3778. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3779. coal_reg = BNX2_HC_COMMAND;
  3780. coal_val = CNIC_RD(dev, coal_reg);
  3781. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3782. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3783. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3784. coal_reg = BNX2_HC_COALESCE_NOW;
  3785. coal_val = 1 << (11 + sb_id);
  3786. }
  3787. i = 0;
  3788. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3789. CNIC_WR(dev, coal_reg, coal_val);
  3790. udelay(10);
  3791. i++;
  3792. barrier();
  3793. }
  3794. cp->rx_cons = *cp->rx_cons_ptr;
  3795. cid_addr = GET_CID_ADDR(2);
  3796. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3797. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3798. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3799. if (sb_id == 0)
  3800. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3801. else
  3802. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3803. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3804. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3805. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3806. dma_addr_t buf_map;
  3807. int n = (i % cp->l2_rx_ring_size) + 1;
  3808. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3809. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3810. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3811. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3812. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3813. }
  3814. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3815. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3816. rxbd->rx_bd_haddr_hi = val;
  3817. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3818. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3819. rxbd->rx_bd_haddr_lo = val;
  3820. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3821. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3822. }
  3823. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3824. {
  3825. struct kwqe *wqes[1], l2kwqe;
  3826. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3827. wqes[0] = &l2kwqe;
  3828. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3829. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3830. KWQE_OPCODE_SHIFT) | 2;
  3831. dev->submit_kwqes(dev, wqes, 1);
  3832. }
  3833. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3834. {
  3835. struct cnic_local *cp = dev->cnic_priv;
  3836. u32 val;
  3837. val = cp->func << 2;
  3838. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3839. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3840. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3841. dev->mac_addr[0] = (u8) (val >> 8);
  3842. dev->mac_addr[1] = (u8) val;
  3843. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3844. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3845. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3846. dev->mac_addr[2] = (u8) (val >> 24);
  3847. dev->mac_addr[3] = (u8) (val >> 16);
  3848. dev->mac_addr[4] = (u8) (val >> 8);
  3849. dev->mac_addr[5] = (u8) val;
  3850. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3851. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3852. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3853. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3854. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3855. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3856. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3857. }
  3858. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3859. {
  3860. struct cnic_local *cp = dev->cnic_priv;
  3861. struct cnic_eth_dev *ethdev = cp->ethdev;
  3862. struct status_block *sblk = cp->status_blk.gen;
  3863. u32 val, kcq_cid_addr, kwq_cid_addr;
  3864. int err;
  3865. cnic_set_bnx2_mac(dev);
  3866. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3867. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3868. if (BCM_PAGE_BITS > 12)
  3869. val |= (12 - 8) << 4;
  3870. else
  3871. val |= (BCM_PAGE_BITS - 8) << 4;
  3872. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3873. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3874. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3875. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3876. err = cnic_setup_5709_context(dev, 1);
  3877. if (err)
  3878. return err;
  3879. cnic_init_context(dev, KWQ_CID);
  3880. cnic_init_context(dev, KCQ_CID);
  3881. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3882. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3883. cp->max_kwq_idx = MAX_KWQ_IDX;
  3884. cp->kwq_prod_idx = 0;
  3885. cp->kwq_con_idx = 0;
  3886. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3887. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3888. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3889. else
  3890. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3891. /* Initialize the kernel work queue context. */
  3892. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3893. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3894. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3895. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3896. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3897. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3898. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3899. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3900. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3901. val = (u32) cp->kwq_info.pgtbl_map;
  3902. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3903. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3904. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3905. cp->kcq1.sw_prod_idx = 0;
  3906. cp->kcq1.hw_prod_idx_ptr =
  3907. &sblk->status_completion_producer_index;
  3908. cp->kcq1.status_idx_ptr = &sblk->status_idx;
  3909. /* Initialize the kernel complete queue context. */
  3910. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3911. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3912. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3913. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3914. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3915. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3916. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3917. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3918. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3919. val = (u32) cp->kcq1.dma.pgtbl_map;
  3920. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3921. cp->int_num = 0;
  3922. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3923. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3924. u32 sb_id = cp->status_blk_num;
  3925. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3926. cp->kcq1.hw_prod_idx_ptr =
  3927. &msblk->status_completion_producer_index;
  3928. cp->kcq1.status_idx_ptr = &msblk->status_idx;
  3929. cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
  3930. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3931. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3932. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3933. }
  3934. /* Enable Commnad Scheduler notification when we write to the
  3935. * host producer index of the kernel contexts. */
  3936. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3937. /* Enable Command Scheduler notification when we write to either
  3938. * the Send Queue or Receive Queue producer indexes of the kernel
  3939. * bypass contexts. */
  3940. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3941. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3942. /* Notify COM when the driver post an application buffer. */
  3943. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3944. /* Set the CP and COM doorbells. These two processors polls the
  3945. * doorbell for a non zero value before running. This must be done
  3946. * after setting up the kernel queue contexts. */
  3947. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3948. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3949. cnic_init_bnx2_tx_ring(dev);
  3950. cnic_init_bnx2_rx_ring(dev);
  3951. err = cnic_init_bnx2_irq(dev);
  3952. if (err) {
  3953. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3954. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3955. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3956. return err;
  3957. }
  3958. return 0;
  3959. }
  3960. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3961. {
  3962. struct cnic_local *cp = dev->cnic_priv;
  3963. struct cnic_eth_dev *ethdev = cp->ethdev;
  3964. u32 start_offset = ethdev->ctx_tbl_offset;
  3965. int i;
  3966. for (i = 0; i < cp->ctx_blks; i++) {
  3967. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3968. dma_addr_t map = ctx->mapping;
  3969. if (cp->ctx_align) {
  3970. unsigned long mask = cp->ctx_align - 1;
  3971. map = (map + mask) & ~mask;
  3972. }
  3973. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3974. }
  3975. }
  3976. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3977. {
  3978. struct cnic_local *cp = dev->cnic_priv;
  3979. struct cnic_eth_dev *ethdev = cp->ethdev;
  3980. int err = 0;
  3981. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3982. (unsigned long) dev);
  3983. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3984. err = cnic_request_irq(dev);
  3985. return err;
  3986. }
  3987. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3988. u16 sb_id, u8 sb_index,
  3989. u8 disable)
  3990. {
  3991. u32 addr = BAR_CSTRORM_INTMEM +
  3992. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3993. offsetof(struct hc_status_block_data_e1x, index_data) +
  3994. sizeof(struct hc_index_data)*sb_index +
  3995. offsetof(struct hc_index_data, flags);
  3996. u16 flags = CNIC_RD16(dev, addr);
  3997. /* clear and set */
  3998. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3999. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  4000. HC_INDEX_DATA_HC_ENABLED);
  4001. CNIC_WR16(dev, addr, flags);
  4002. }
  4003. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  4004. {
  4005. struct cnic_local *cp = dev->cnic_priv;
  4006. u8 sb_id = cp->status_blk_num;
  4007. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4008. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4009. offsetof(struct hc_status_block_data_e1x, index_data) +
  4010. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  4011. offsetof(struct hc_index_data, timeout), 64 / 4);
  4012. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  4013. }
  4014. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  4015. {
  4016. }
  4017. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  4018. struct client_init_ramrod_data *data)
  4019. {
  4020. struct cnic_local *cp = dev->cnic_priv;
  4021. struct cnic_uio_dev *udev = cp->udev;
  4022. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  4023. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  4024. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4025. int i;
  4026. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4027. u32 val;
  4028. memset(txbd, 0, BCM_PAGE_SIZE);
  4029. buf_map = udev->l2_buf_map;
  4030. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  4031. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  4032. struct eth_tx_parse_bd_e1x *pbd_e1x =
  4033. &((txbd + 1)->parse_bd_e1x);
  4034. struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
  4035. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  4036. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4037. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4038. reg_bd->addr_hi = start_bd->addr_hi;
  4039. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  4040. start_bd->nbytes = cpu_to_le16(0x10);
  4041. start_bd->nbd = cpu_to_le16(3);
  4042. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  4043. start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
  4044. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  4045. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4046. pbd_e2->parsing_data = (UNICAST_ADDRESS <<
  4047. ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
  4048. else
  4049. pbd_e1x->global_data = (UNICAST_ADDRESS <<
  4050. ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
  4051. }
  4052. val = (u64) ring_map >> 32;
  4053. txbd->next_bd.addr_hi = cpu_to_le32(val);
  4054. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  4055. val = (u64) ring_map & 0xffffffff;
  4056. txbd->next_bd.addr_lo = cpu_to_le32(val);
  4057. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  4058. /* Other ramrod params */
  4059. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4060. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4061. /* reset xstorm per client statistics */
  4062. if (cli < MAX_STAT_COUNTER_ID) {
  4063. data->general.statistics_zero_flg = 1;
  4064. data->general.statistics_en_flg = 1;
  4065. data->general.statistics_counter_id = cli;
  4066. }
  4067. cp->tx_cons_ptr =
  4068. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4069. }
  4070. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4071. struct client_init_ramrod_data *data)
  4072. {
  4073. struct cnic_local *cp = dev->cnic_priv;
  4074. struct cnic_uio_dev *udev = cp->udev;
  4075. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4076. BCM_PAGE_SIZE);
  4077. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4078. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  4079. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4080. int i;
  4081. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4082. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4083. u32 val;
  4084. dma_addr_t ring_map = udev->l2_ring_map;
  4085. /* General data */
  4086. data->general.client_id = cli;
  4087. data->general.activate_flg = 1;
  4088. data->general.sp_client_id = cli;
  4089. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4090. data->general.func_id = cp->pfid;
  4091. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4092. dma_addr_t buf_map;
  4093. int n = (i % cp->l2_rx_ring_size) + 1;
  4094. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4095. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4096. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4097. }
  4098. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  4099. rxbd->addr_hi = cpu_to_le32(val);
  4100. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4101. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  4102. rxbd->addr_lo = cpu_to_le32(val);
  4103. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4104. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4105. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  4106. rxcqe->addr_hi = cpu_to_le32(val);
  4107. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4108. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  4109. rxcqe->addr_lo = cpu_to_le32(val);
  4110. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4111. /* Other ramrod params */
  4112. data->rx.client_qzone_id = cl_qzone_id;
  4113. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4114. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4115. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4116. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4117. data->rx.outer_vlan_removal_enable_flg = 1;
  4118. data->rx.silent_vlan_removal_flg = 1;
  4119. data->rx.silent_vlan_value = 0;
  4120. data->rx.silent_vlan_mask = 0xffff;
  4121. cp->rx_cons_ptr =
  4122. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4123. cp->rx_cons = *cp->rx_cons_ptr;
  4124. }
  4125. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4126. {
  4127. struct cnic_local *cp = dev->cnic_priv;
  4128. u32 pfid = cp->pfid;
  4129. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4130. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4131. cp->kcq1.sw_prod_idx = 0;
  4132. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4133. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4134. cp->kcq1.hw_prod_idx_ptr =
  4135. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4136. cp->kcq1.status_idx_ptr =
  4137. &sb->sb.running_index[SM_RX_ID];
  4138. } else {
  4139. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4140. cp->kcq1.hw_prod_idx_ptr =
  4141. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4142. cp->kcq1.status_idx_ptr =
  4143. &sb->sb.running_index[SM_RX_ID];
  4144. }
  4145. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4146. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4147. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4148. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4149. cp->kcq2.sw_prod_idx = 0;
  4150. cp->kcq2.hw_prod_idx_ptr =
  4151. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4152. cp->kcq2.status_idx_ptr =
  4153. &sb->sb.running_index[SM_RX_ID];
  4154. }
  4155. }
  4156. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4157. {
  4158. struct cnic_local *cp = dev->cnic_priv;
  4159. struct cnic_eth_dev *ethdev = cp->ethdev;
  4160. int func = CNIC_FUNC(cp), ret;
  4161. u32 pfid;
  4162. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4163. cp->port_mode = CHIP_PORT_MODE_NONE;
  4164. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4165. u32 val;
  4166. pci_read_config_dword(dev->pcidev, PCICFG_ME_REGISTER, &val);
  4167. cp->func = (u8) ((val & ME_REG_ABS_PF_NUM) >>
  4168. ME_REG_ABS_PF_NUM_SHIFT);
  4169. func = CNIC_FUNC(cp);
  4170. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  4171. if (!(val & 1))
  4172. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  4173. else
  4174. val = (val >> 1) & 1;
  4175. if (val) {
  4176. cp->port_mode = CHIP_4_PORT_MODE;
  4177. cp->pfid = func >> 1;
  4178. } else {
  4179. cp->port_mode = CHIP_2_PORT_MODE;
  4180. cp->pfid = func & 0x6;
  4181. }
  4182. } else {
  4183. cp->pfid = func;
  4184. }
  4185. pfid = cp->pfid;
  4186. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4187. cp->iscsi_start_cid, 0);
  4188. if (ret)
  4189. return -ENOMEM;
  4190. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4191. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4192. cp->fcoe_start_cid, 0);
  4193. if (ret)
  4194. return -ENOMEM;
  4195. }
  4196. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4197. cnic_init_bnx2x_kcq(dev);
  4198. /* Only 1 EQ */
  4199. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4200. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4201. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4202. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4203. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4204. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4205. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4206. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4207. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4208. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4209. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4210. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4211. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4212. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4213. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4214. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4215. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4216. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4217. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4218. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4219. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4220. HC_INDEX_ISCSI_EQ_CONS);
  4221. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4222. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4223. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4224. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4225. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4226. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4227. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4228. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4229. cnic_setup_bnx2x_context(dev);
  4230. ret = cnic_init_bnx2x_irq(dev);
  4231. if (ret)
  4232. return ret;
  4233. return 0;
  4234. }
  4235. static void cnic_init_rings(struct cnic_dev *dev)
  4236. {
  4237. struct cnic_local *cp = dev->cnic_priv;
  4238. struct cnic_uio_dev *udev = cp->udev;
  4239. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4240. return;
  4241. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4242. cnic_init_bnx2_tx_ring(dev);
  4243. cnic_init_bnx2_rx_ring(dev);
  4244. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4245. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4246. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4247. u32 cid = cp->ethdev->iscsi_l2_cid;
  4248. u32 cl_qzone_id;
  4249. struct client_init_ramrod_data *data;
  4250. union l5cm_specific_data l5_data;
  4251. struct ustorm_eth_rx_producers rx_prods = {0};
  4252. u32 off, i, *cid_ptr;
  4253. rx_prods.bd_prod = 0;
  4254. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4255. barrier();
  4256. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4257. off = BAR_USTRORM_INTMEM +
  4258. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4259. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4260. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4261. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4262. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4263. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4264. data = udev->l2_buf;
  4265. cid_ptr = udev->l2_buf + 12;
  4266. memset(data, 0, sizeof(*data));
  4267. cnic_init_bnx2x_tx_ring(dev, data);
  4268. cnic_init_bnx2x_rx_ring(dev, data);
  4269. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4270. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4271. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4272. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4273. cid, ETH_CONNECTION_TYPE, &l5_data);
  4274. i = 0;
  4275. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4276. ++i < 10)
  4277. msleep(1);
  4278. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4279. netdev_err(dev->netdev,
  4280. "iSCSI CLIENT_SETUP did not complete\n");
  4281. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4282. cnic_ring_ctl(dev, cid, cli, 1);
  4283. *cid_ptr = cid;
  4284. }
  4285. }
  4286. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4287. {
  4288. struct cnic_local *cp = dev->cnic_priv;
  4289. struct cnic_uio_dev *udev = cp->udev;
  4290. void *rx_ring;
  4291. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4292. return;
  4293. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4294. cnic_shutdown_bnx2_rx_ring(dev);
  4295. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4296. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4297. u32 cid = cp->ethdev->iscsi_l2_cid;
  4298. union l5cm_specific_data l5_data;
  4299. int i;
  4300. cnic_ring_ctl(dev, cid, cli, 0);
  4301. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4302. l5_data.phy_address.lo = cli;
  4303. l5_data.phy_address.hi = 0;
  4304. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4305. cid, ETH_CONNECTION_TYPE, &l5_data);
  4306. i = 0;
  4307. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4308. ++i < 10)
  4309. msleep(1);
  4310. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4311. netdev_err(dev->netdev,
  4312. "iSCSI CLIENT_HALT did not complete\n");
  4313. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4314. memset(&l5_data, 0, sizeof(l5_data));
  4315. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4316. cid, NONE_CONNECTION_TYPE, &l5_data);
  4317. msleep(10);
  4318. }
  4319. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4320. rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
  4321. memset(rx_ring, 0, BCM_PAGE_SIZE);
  4322. }
  4323. static int cnic_register_netdev(struct cnic_dev *dev)
  4324. {
  4325. struct cnic_local *cp = dev->cnic_priv;
  4326. struct cnic_eth_dev *ethdev = cp->ethdev;
  4327. int err;
  4328. if (!ethdev)
  4329. return -ENODEV;
  4330. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4331. return 0;
  4332. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4333. if (err)
  4334. netdev_err(dev->netdev, "register_cnic failed\n");
  4335. return err;
  4336. }
  4337. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4338. {
  4339. struct cnic_local *cp = dev->cnic_priv;
  4340. struct cnic_eth_dev *ethdev = cp->ethdev;
  4341. if (!ethdev)
  4342. return;
  4343. ethdev->drv_unregister_cnic(dev->netdev);
  4344. }
  4345. static int cnic_start_hw(struct cnic_dev *dev)
  4346. {
  4347. struct cnic_local *cp = dev->cnic_priv;
  4348. struct cnic_eth_dev *ethdev = cp->ethdev;
  4349. int err;
  4350. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4351. return -EALREADY;
  4352. dev->regview = ethdev->io_base;
  4353. pci_dev_get(dev->pcidev);
  4354. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4355. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4356. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4357. err = cp->alloc_resc(dev);
  4358. if (err) {
  4359. netdev_err(dev->netdev, "allocate resource failure\n");
  4360. goto err1;
  4361. }
  4362. err = cp->start_hw(dev);
  4363. if (err)
  4364. goto err1;
  4365. err = cnic_cm_open(dev);
  4366. if (err)
  4367. goto err1;
  4368. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4369. cp->enable_int(dev);
  4370. return 0;
  4371. err1:
  4372. cp->free_resc(dev);
  4373. pci_dev_put(dev->pcidev);
  4374. return err;
  4375. }
  4376. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4377. {
  4378. cnic_disable_bnx2_int_sync(dev);
  4379. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4380. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4381. cnic_init_context(dev, KWQ_CID);
  4382. cnic_init_context(dev, KCQ_CID);
  4383. cnic_setup_5709_context(dev, 0);
  4384. cnic_free_irq(dev);
  4385. cnic_free_resc(dev);
  4386. }
  4387. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4388. {
  4389. struct cnic_local *cp = dev->cnic_priv;
  4390. cnic_free_irq(dev);
  4391. *cp->kcq1.hw_prod_idx_ptr = 0;
  4392. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4393. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4394. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4395. cnic_free_resc(dev);
  4396. }
  4397. static void cnic_stop_hw(struct cnic_dev *dev)
  4398. {
  4399. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4400. struct cnic_local *cp = dev->cnic_priv;
  4401. int i = 0;
  4402. /* Need to wait for the ring shutdown event to complete
  4403. * before clearing the CNIC_UP flag.
  4404. */
  4405. while (cp->udev && cp->udev->uio_dev != -1 && i < 15) {
  4406. msleep(100);
  4407. i++;
  4408. }
  4409. cnic_shutdown_rings(dev);
  4410. cp->stop_cm(dev);
  4411. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4412. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4413. synchronize_rcu();
  4414. cnic_cm_shutdown(dev);
  4415. cp->stop_hw(dev);
  4416. pci_dev_put(dev->pcidev);
  4417. }
  4418. }
  4419. static void cnic_free_dev(struct cnic_dev *dev)
  4420. {
  4421. int i = 0;
  4422. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4423. msleep(100);
  4424. i++;
  4425. }
  4426. if (atomic_read(&dev->ref_count) != 0)
  4427. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4428. netdev_info(dev->netdev, "Removed CNIC device\n");
  4429. dev_put(dev->netdev);
  4430. kfree(dev);
  4431. }
  4432. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4433. struct pci_dev *pdev)
  4434. {
  4435. struct cnic_dev *cdev;
  4436. struct cnic_local *cp;
  4437. int alloc_size;
  4438. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4439. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4440. if (cdev == NULL) {
  4441. netdev_err(dev, "allocate dev struct failure\n");
  4442. return NULL;
  4443. }
  4444. cdev->netdev = dev;
  4445. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4446. cdev->register_device = cnic_register_device;
  4447. cdev->unregister_device = cnic_unregister_device;
  4448. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4449. cp = cdev->cnic_priv;
  4450. cp->dev = cdev;
  4451. cp->l2_single_buf_size = 0x400;
  4452. cp->l2_rx_ring_size = 3;
  4453. spin_lock_init(&cp->cnic_ulp_lock);
  4454. netdev_info(dev, "Added CNIC device\n");
  4455. return cdev;
  4456. }
  4457. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4458. {
  4459. struct pci_dev *pdev;
  4460. struct cnic_dev *cdev;
  4461. struct cnic_local *cp;
  4462. struct cnic_eth_dev *ethdev = NULL;
  4463. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4464. probe = symbol_get(bnx2_cnic_probe);
  4465. if (probe) {
  4466. ethdev = (*probe)(dev);
  4467. symbol_put(bnx2_cnic_probe);
  4468. }
  4469. if (!ethdev)
  4470. return NULL;
  4471. pdev = ethdev->pdev;
  4472. if (!pdev)
  4473. return NULL;
  4474. dev_hold(dev);
  4475. pci_dev_get(pdev);
  4476. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4477. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4478. (pdev->revision < 0x10)) {
  4479. pci_dev_put(pdev);
  4480. goto cnic_err;
  4481. }
  4482. pci_dev_put(pdev);
  4483. cdev = cnic_alloc_dev(dev, pdev);
  4484. if (cdev == NULL)
  4485. goto cnic_err;
  4486. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4487. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4488. cp = cdev->cnic_priv;
  4489. cp->ethdev = ethdev;
  4490. cdev->pcidev = pdev;
  4491. cp->chip_id = ethdev->chip_id;
  4492. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4493. cp->cnic_ops = &cnic_bnx2_ops;
  4494. cp->start_hw = cnic_start_bnx2_hw;
  4495. cp->stop_hw = cnic_stop_bnx2_hw;
  4496. cp->setup_pgtbl = cnic_setup_page_tbl;
  4497. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4498. cp->free_resc = cnic_free_resc;
  4499. cp->start_cm = cnic_cm_init_bnx2_hw;
  4500. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4501. cp->enable_int = cnic_enable_bnx2_int;
  4502. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4503. cp->close_conn = cnic_close_bnx2_conn;
  4504. return cdev;
  4505. cnic_err:
  4506. dev_put(dev);
  4507. return NULL;
  4508. }
  4509. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4510. {
  4511. struct pci_dev *pdev;
  4512. struct cnic_dev *cdev;
  4513. struct cnic_local *cp;
  4514. struct cnic_eth_dev *ethdev = NULL;
  4515. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4516. probe = symbol_get(bnx2x_cnic_probe);
  4517. if (probe) {
  4518. ethdev = (*probe)(dev);
  4519. symbol_put(bnx2x_cnic_probe);
  4520. }
  4521. if (!ethdev)
  4522. return NULL;
  4523. pdev = ethdev->pdev;
  4524. if (!pdev)
  4525. return NULL;
  4526. dev_hold(dev);
  4527. cdev = cnic_alloc_dev(dev, pdev);
  4528. if (cdev == NULL) {
  4529. dev_put(dev);
  4530. return NULL;
  4531. }
  4532. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4533. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4534. cp = cdev->cnic_priv;
  4535. cp->ethdev = ethdev;
  4536. cdev->pcidev = pdev;
  4537. cp->chip_id = ethdev->chip_id;
  4538. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4539. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4540. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4541. if (CNIC_SUPPORTS_FCOE(cp))
  4542. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4543. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4544. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4545. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4546. cp->cnic_ops = &cnic_bnx2x_ops;
  4547. cp->start_hw = cnic_start_bnx2x_hw;
  4548. cp->stop_hw = cnic_stop_bnx2x_hw;
  4549. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4550. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4551. cp->free_resc = cnic_free_resc;
  4552. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4553. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4554. cp->enable_int = cnic_enable_bnx2x_int;
  4555. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4556. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4557. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4558. cp->arm_int = cnic_arm_bnx2x_e2_msix;
  4559. } else {
  4560. cp->ack_int = cnic_ack_bnx2x_msix;
  4561. cp->arm_int = cnic_arm_bnx2x_msix;
  4562. }
  4563. cp->close_conn = cnic_close_bnx2x_conn;
  4564. return cdev;
  4565. }
  4566. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4567. {
  4568. struct ethtool_drvinfo drvinfo;
  4569. struct cnic_dev *cdev = NULL;
  4570. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4571. memset(&drvinfo, 0, sizeof(drvinfo));
  4572. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4573. if (!strcmp(drvinfo.driver, "bnx2"))
  4574. cdev = init_bnx2_cnic(dev);
  4575. if (!strcmp(drvinfo.driver, "bnx2x"))
  4576. cdev = init_bnx2x_cnic(dev);
  4577. if (cdev) {
  4578. write_lock(&cnic_dev_lock);
  4579. list_add(&cdev->list, &cnic_dev_list);
  4580. write_unlock(&cnic_dev_lock);
  4581. }
  4582. }
  4583. return cdev;
  4584. }
  4585. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4586. u16 vlan_id)
  4587. {
  4588. int if_type;
  4589. rcu_read_lock();
  4590. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4591. struct cnic_ulp_ops *ulp_ops;
  4592. void *ctx;
  4593. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4594. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4595. continue;
  4596. ctx = cp->ulp_handle[if_type];
  4597. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4598. }
  4599. rcu_read_unlock();
  4600. }
  4601. /* netdev event handler */
  4602. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4603. void *ptr)
  4604. {
  4605. struct net_device *netdev = ptr;
  4606. struct cnic_dev *dev;
  4607. int new_dev = 0;
  4608. dev = cnic_from_netdev(netdev);
  4609. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4610. /* Check for the hot-plug device */
  4611. dev = is_cnic_dev(netdev);
  4612. if (dev) {
  4613. new_dev = 1;
  4614. cnic_hold(dev);
  4615. }
  4616. }
  4617. if (dev) {
  4618. struct cnic_local *cp = dev->cnic_priv;
  4619. if (new_dev)
  4620. cnic_ulp_init(dev);
  4621. else if (event == NETDEV_UNREGISTER)
  4622. cnic_ulp_exit(dev);
  4623. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4624. if (cnic_register_netdev(dev) != 0) {
  4625. cnic_put(dev);
  4626. goto done;
  4627. }
  4628. if (!cnic_start_hw(dev))
  4629. cnic_ulp_start(dev);
  4630. }
  4631. cnic_rcv_netevent(cp, event, 0);
  4632. if (event == NETDEV_GOING_DOWN) {
  4633. cnic_ulp_stop(dev);
  4634. cnic_stop_hw(dev);
  4635. cnic_unregister_netdev(dev);
  4636. } else if (event == NETDEV_UNREGISTER) {
  4637. write_lock(&cnic_dev_lock);
  4638. list_del_init(&dev->list);
  4639. write_unlock(&cnic_dev_lock);
  4640. cnic_put(dev);
  4641. cnic_free_dev(dev);
  4642. goto done;
  4643. }
  4644. cnic_put(dev);
  4645. } else {
  4646. struct net_device *realdev;
  4647. u16 vid;
  4648. vid = cnic_get_vlan(netdev, &realdev);
  4649. if (realdev) {
  4650. dev = cnic_from_netdev(realdev);
  4651. if (dev) {
  4652. vid |= VLAN_TAG_PRESENT;
  4653. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4654. cnic_put(dev);
  4655. }
  4656. }
  4657. }
  4658. done:
  4659. return NOTIFY_DONE;
  4660. }
  4661. static struct notifier_block cnic_netdev_notifier = {
  4662. .notifier_call = cnic_netdev_event
  4663. };
  4664. static void cnic_release(void)
  4665. {
  4666. struct cnic_dev *dev;
  4667. struct cnic_uio_dev *udev;
  4668. while (!list_empty(&cnic_dev_list)) {
  4669. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4670. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4671. cnic_ulp_stop(dev);
  4672. cnic_stop_hw(dev);
  4673. }
  4674. cnic_ulp_exit(dev);
  4675. cnic_unregister_netdev(dev);
  4676. list_del_init(&dev->list);
  4677. cnic_free_dev(dev);
  4678. }
  4679. while (!list_empty(&cnic_udev_list)) {
  4680. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4681. list);
  4682. cnic_free_uio(udev);
  4683. }
  4684. }
  4685. static int __init cnic_init(void)
  4686. {
  4687. int rc = 0;
  4688. pr_info("%s", version);
  4689. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4690. if (rc) {
  4691. cnic_release();
  4692. return rc;
  4693. }
  4694. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4695. if (!cnic_wq) {
  4696. cnic_release();
  4697. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4698. return -ENOMEM;
  4699. }
  4700. return 0;
  4701. }
  4702. static void __exit cnic_exit(void)
  4703. {
  4704. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4705. cnic_release();
  4706. destroy_workqueue(cnic_wq);
  4707. }
  4708. module_init(cnic_init);
  4709. module_exit(cnic_exit);