rt2x00queue.c 16 KB

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  1. /*
  2. Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2x00lib
  19. Abstract: rt2x00 queue specific routines.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/dma-mapping.h>
  24. #include "rt2x00.h"
  25. #include "rt2x00lib.h"
  26. struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
  27. struct queue_entry *entry)
  28. {
  29. unsigned int frame_size;
  30. unsigned int reserved_size;
  31. struct sk_buff *skb;
  32. struct skb_frame_desc *skbdesc;
  33. /*
  34. * The frame size includes descriptor size, because the
  35. * hardware directly receive the frame into the skbuffer.
  36. */
  37. frame_size = entry->queue->data_size + entry->queue->desc_size;
  38. /*
  39. * Reserve a few bytes extra headroom to allow drivers some moving
  40. * space (e.g. for alignment), while keeping the skb aligned.
  41. */
  42. reserved_size = 8;
  43. /*
  44. * Allocate skbuffer.
  45. */
  46. skb = dev_alloc_skb(frame_size + reserved_size);
  47. if (!skb)
  48. return NULL;
  49. skb_reserve(skb, reserved_size);
  50. skb_put(skb, frame_size);
  51. /*
  52. * Populate skbdesc.
  53. */
  54. skbdesc = get_skb_frame_desc(skb);
  55. memset(skbdesc, 0, sizeof(*skbdesc));
  56. skbdesc->entry = entry;
  57. if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
  58. skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
  59. skb->data,
  60. skb->len,
  61. DMA_FROM_DEVICE);
  62. skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
  63. }
  64. return skb;
  65. }
  66. void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  67. {
  68. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  69. skbdesc->skb_dma = dma_map_single(rt2x00dev->dev, skb->data, skb->len,
  70. DMA_TO_DEVICE);
  71. skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
  72. }
  73. EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
  74. void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  75. {
  76. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  77. if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
  78. dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
  79. DMA_FROM_DEVICE);
  80. skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
  81. }
  82. if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
  83. dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
  84. DMA_TO_DEVICE);
  85. skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
  86. }
  87. }
  88. void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  89. {
  90. rt2x00queue_unmap_skb(rt2x00dev, skb);
  91. dev_kfree_skb_any(skb);
  92. }
  93. void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
  94. struct txentry_desc *txdesc)
  95. {
  96. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  97. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
  98. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
  99. struct ieee80211_rate *rate =
  100. ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
  101. const struct rt2x00_rate *hwrate;
  102. unsigned int data_length;
  103. unsigned int duration;
  104. unsigned int residual;
  105. memset(txdesc, 0, sizeof(*txdesc));
  106. /*
  107. * Initialize information from queue
  108. */
  109. txdesc->queue = entry->queue->qid;
  110. txdesc->cw_min = entry->queue->cw_min;
  111. txdesc->cw_max = entry->queue->cw_max;
  112. txdesc->aifs = entry->queue->aifs;
  113. /* Data length should be extended with 4 bytes for CRC */
  114. data_length = entry->skb->len + 4;
  115. /*
  116. * Check whether this frame is to be acked.
  117. */
  118. if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
  119. __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
  120. /*
  121. * Check if this is a RTS/CTS frame
  122. */
  123. if (ieee80211_is_rts(hdr->frame_control) ||
  124. ieee80211_is_cts(hdr->frame_control)) {
  125. __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
  126. if (ieee80211_is_rts(hdr->frame_control))
  127. __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
  128. else
  129. __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
  130. if (tx_info->control.rts_cts_rate_idx >= 0)
  131. rate =
  132. ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
  133. }
  134. /*
  135. * Determine retry information.
  136. */
  137. txdesc->retry_limit = tx_info->control.retry_limit;
  138. if (tx_info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT)
  139. __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
  140. /*
  141. * Check if more fragments are pending
  142. */
  143. if (ieee80211_has_morefrags(hdr->frame_control)) {
  144. __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
  145. __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
  146. }
  147. /*
  148. * Beacons and probe responses require the tsf timestamp
  149. * to be inserted into the frame.
  150. */
  151. if (ieee80211_is_beacon(hdr->frame_control) ||
  152. ieee80211_is_probe_resp(hdr->frame_control))
  153. __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
  154. /*
  155. * Determine with what IFS priority this frame should be send.
  156. * Set ifs to IFS_SIFS when the this is not the first fragment,
  157. * or this fragment came after RTS/CTS.
  158. */
  159. if (test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
  160. txdesc->ifs = IFS_SIFS;
  161. } else if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {
  162. __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
  163. txdesc->ifs = IFS_BACKOFF;
  164. } else {
  165. txdesc->ifs = IFS_SIFS;
  166. }
  167. /*
  168. * PLCP setup
  169. * Length calculation depends on OFDM/CCK rate.
  170. */
  171. hwrate = rt2x00_get_rate(rate->hw_value);
  172. txdesc->signal = hwrate->plcp;
  173. txdesc->service = 0x04;
  174. if (hwrate->flags & DEV_RATE_OFDM) {
  175. __set_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags);
  176. txdesc->length_high = (data_length >> 6) & 0x3f;
  177. txdesc->length_low = data_length & 0x3f;
  178. } else {
  179. /*
  180. * Convert length to microseconds.
  181. */
  182. residual = get_duration_res(data_length, hwrate->bitrate);
  183. duration = get_duration(data_length, hwrate->bitrate);
  184. if (residual != 0) {
  185. duration++;
  186. /*
  187. * Check if we need to set the Length Extension
  188. */
  189. if (hwrate->bitrate == 110 && residual <= 30)
  190. txdesc->service |= 0x80;
  191. }
  192. txdesc->length_high = (duration >> 8) & 0xff;
  193. txdesc->length_low = duration & 0xff;
  194. /*
  195. * When preamble is enabled we should set the
  196. * preamble bit for the signal.
  197. */
  198. if (rt2x00_get_rate_preamble(rate->hw_value))
  199. txdesc->signal |= 0x08;
  200. }
  201. }
  202. EXPORT_SYMBOL_GPL(rt2x00queue_create_tx_descriptor);
  203. void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
  204. struct txentry_desc *txdesc)
  205. {
  206. struct data_queue *queue = entry->queue;
  207. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  208. rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
  209. /*
  210. * All processing on the frame has been completed, this means
  211. * it is now ready to be dumped to userspace through debugfs.
  212. */
  213. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
  214. /*
  215. * Check if we need to kick the queue, there are however a few rules
  216. * 1) Don't kick beacon queue
  217. * 2) Don't kick unless this is the last in frame in a burst.
  218. * When the burst flag is set, this frame is always followed
  219. * by another frame which in some way are related to eachother.
  220. * This is true for fragments, RTS or CTS-to-self frames.
  221. * 3) Rule 2 can be broken when the available entries
  222. * in the queue are less then a certain threshold.
  223. */
  224. if (entry->queue->qid == QID_BEACON)
  225. return;
  226. if (rt2x00queue_threshold(queue) ||
  227. !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
  228. rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
  229. }
  230. EXPORT_SYMBOL_GPL(rt2x00queue_write_tx_descriptor);
  231. int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
  232. {
  233. struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
  234. struct txentry_desc txdesc;
  235. struct skb_frame_desc *skbdesc;
  236. if (unlikely(rt2x00queue_full(queue)))
  237. return -EINVAL;
  238. if (__test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
  239. ERROR(queue->rt2x00dev,
  240. "Arrived at non-free entry in the non-full queue %d.\n"
  241. "Please file bug report to %s.\n",
  242. queue->qid, DRV_PROJECT);
  243. return -EINVAL;
  244. }
  245. /*
  246. * Copy all TX descriptor information into txdesc,
  247. * after that we are free to use the skb->cb array
  248. * for our information.
  249. */
  250. entry->skb = skb;
  251. rt2x00queue_create_tx_descriptor(entry, &txdesc);
  252. /*
  253. * skb->cb array is now ours and we are free to use it.
  254. */
  255. skbdesc = get_skb_frame_desc(entry->skb);
  256. memset(skbdesc, 0, sizeof(*skbdesc));
  257. skbdesc->entry = entry;
  258. if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
  259. __clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
  260. return -EIO;
  261. }
  262. if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
  263. rt2x00queue_map_txskb(queue->rt2x00dev, skb);
  264. __set_bit(ENTRY_DATA_PENDING, &entry->flags);
  265. rt2x00queue_index_inc(queue, Q_INDEX);
  266. rt2x00queue_write_tx_descriptor(entry, &txdesc);
  267. return 0;
  268. }
  269. struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
  270. const enum data_queue_qid queue)
  271. {
  272. int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
  273. if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
  274. return &rt2x00dev->tx[queue];
  275. if (!rt2x00dev->bcn)
  276. return NULL;
  277. if (queue == QID_BEACON)
  278. return &rt2x00dev->bcn[0];
  279. else if (queue == QID_ATIM && atim)
  280. return &rt2x00dev->bcn[1];
  281. return NULL;
  282. }
  283. EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
  284. struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
  285. enum queue_index index)
  286. {
  287. struct queue_entry *entry;
  288. unsigned long irqflags;
  289. if (unlikely(index >= Q_INDEX_MAX)) {
  290. ERROR(queue->rt2x00dev,
  291. "Entry requested from invalid index type (%d)\n", index);
  292. return NULL;
  293. }
  294. spin_lock_irqsave(&queue->lock, irqflags);
  295. entry = &queue->entries[queue->index[index]];
  296. spin_unlock_irqrestore(&queue->lock, irqflags);
  297. return entry;
  298. }
  299. EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
  300. void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
  301. {
  302. unsigned long irqflags;
  303. if (unlikely(index >= Q_INDEX_MAX)) {
  304. ERROR(queue->rt2x00dev,
  305. "Index change on invalid index type (%d)\n", index);
  306. return;
  307. }
  308. spin_lock_irqsave(&queue->lock, irqflags);
  309. queue->index[index]++;
  310. if (queue->index[index] >= queue->limit)
  311. queue->index[index] = 0;
  312. if (index == Q_INDEX) {
  313. queue->length++;
  314. } else if (index == Q_INDEX_DONE) {
  315. queue->length--;
  316. queue->count ++;
  317. }
  318. spin_unlock_irqrestore(&queue->lock, irqflags);
  319. }
  320. static void rt2x00queue_reset(struct data_queue *queue)
  321. {
  322. unsigned long irqflags;
  323. spin_lock_irqsave(&queue->lock, irqflags);
  324. queue->count = 0;
  325. queue->length = 0;
  326. memset(queue->index, 0, sizeof(queue->index));
  327. spin_unlock_irqrestore(&queue->lock, irqflags);
  328. }
  329. void rt2x00queue_init_rx(struct rt2x00_dev *rt2x00dev)
  330. {
  331. struct data_queue *queue = rt2x00dev->rx;
  332. unsigned int i;
  333. rt2x00queue_reset(queue);
  334. if (!rt2x00dev->ops->lib->init_rxentry)
  335. return;
  336. for (i = 0; i < queue->limit; i++)
  337. rt2x00dev->ops->lib->init_rxentry(rt2x00dev,
  338. &queue->entries[i]);
  339. }
  340. void rt2x00queue_init_tx(struct rt2x00_dev *rt2x00dev)
  341. {
  342. struct data_queue *queue;
  343. unsigned int i;
  344. txall_queue_for_each(rt2x00dev, queue) {
  345. rt2x00queue_reset(queue);
  346. if (!rt2x00dev->ops->lib->init_txentry)
  347. continue;
  348. for (i = 0; i < queue->limit; i++)
  349. rt2x00dev->ops->lib->init_txentry(rt2x00dev,
  350. &queue->entries[i]);
  351. }
  352. }
  353. static int rt2x00queue_alloc_entries(struct data_queue *queue,
  354. const struct data_queue_desc *qdesc)
  355. {
  356. struct queue_entry *entries;
  357. unsigned int entry_size;
  358. unsigned int i;
  359. rt2x00queue_reset(queue);
  360. queue->limit = qdesc->entry_num;
  361. queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
  362. queue->data_size = qdesc->data_size;
  363. queue->desc_size = qdesc->desc_size;
  364. /*
  365. * Allocate all queue entries.
  366. */
  367. entry_size = sizeof(*entries) + qdesc->priv_size;
  368. entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
  369. if (!entries)
  370. return -ENOMEM;
  371. #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
  372. ( ((char *)(__base)) + ((__limit) * (__esize)) + \
  373. ((__index) * (__psize)) )
  374. for (i = 0; i < queue->limit; i++) {
  375. entries[i].flags = 0;
  376. entries[i].queue = queue;
  377. entries[i].skb = NULL;
  378. entries[i].entry_idx = i;
  379. entries[i].priv_data =
  380. QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
  381. sizeof(*entries), qdesc->priv_size);
  382. }
  383. #undef QUEUE_ENTRY_PRIV_OFFSET
  384. queue->entries = entries;
  385. return 0;
  386. }
  387. static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
  388. struct data_queue *queue)
  389. {
  390. unsigned int i;
  391. if (!queue->entries)
  392. return;
  393. for (i = 0; i < queue->limit; i++) {
  394. if (queue->entries[i].skb)
  395. rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
  396. }
  397. }
  398. static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
  399. struct data_queue *queue)
  400. {
  401. unsigned int i;
  402. struct sk_buff *skb;
  403. for (i = 0; i < queue->limit; i++) {
  404. skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
  405. if (!skb)
  406. return -ENOMEM;
  407. queue->entries[i].skb = skb;
  408. }
  409. return 0;
  410. }
  411. int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
  412. {
  413. struct data_queue *queue;
  414. int status;
  415. status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
  416. if (status)
  417. goto exit;
  418. tx_queue_for_each(rt2x00dev, queue) {
  419. status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
  420. if (status)
  421. goto exit;
  422. }
  423. status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
  424. if (status)
  425. goto exit;
  426. if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
  427. status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
  428. rt2x00dev->ops->atim);
  429. if (status)
  430. goto exit;
  431. }
  432. status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
  433. if (status)
  434. goto exit;
  435. return 0;
  436. exit:
  437. ERROR(rt2x00dev, "Queue entries allocation failed.\n");
  438. rt2x00queue_uninitialize(rt2x00dev);
  439. return status;
  440. }
  441. void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
  442. {
  443. struct data_queue *queue;
  444. rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
  445. queue_for_each(rt2x00dev, queue) {
  446. kfree(queue->entries);
  447. queue->entries = NULL;
  448. }
  449. }
  450. static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
  451. struct data_queue *queue, enum data_queue_qid qid)
  452. {
  453. spin_lock_init(&queue->lock);
  454. queue->rt2x00dev = rt2x00dev;
  455. queue->qid = qid;
  456. queue->aifs = 2;
  457. queue->cw_min = 5;
  458. queue->cw_max = 10;
  459. }
  460. int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
  461. {
  462. struct data_queue *queue;
  463. enum data_queue_qid qid;
  464. unsigned int req_atim =
  465. !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
  466. /*
  467. * We need the following queues:
  468. * RX: 1
  469. * TX: ops->tx_queues
  470. * Beacon: 1
  471. * Atim: 1 (if required)
  472. */
  473. rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
  474. queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
  475. if (!queue) {
  476. ERROR(rt2x00dev, "Queue allocation failed.\n");
  477. return -ENOMEM;
  478. }
  479. /*
  480. * Initialize pointers
  481. */
  482. rt2x00dev->rx = queue;
  483. rt2x00dev->tx = &queue[1];
  484. rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
  485. /*
  486. * Initialize queue parameters.
  487. * RX: qid = QID_RX
  488. * TX: qid = QID_AC_BE + index
  489. * TX: cw_min: 2^5 = 32.
  490. * TX: cw_max: 2^10 = 1024.
  491. * BCN: qid = QID_BEACON
  492. * ATIM: qid = QID_ATIM
  493. */
  494. rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
  495. qid = QID_AC_BE;
  496. tx_queue_for_each(rt2x00dev, queue)
  497. rt2x00queue_init(rt2x00dev, queue, qid++);
  498. rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
  499. if (req_atim)
  500. rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
  501. return 0;
  502. }
  503. void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
  504. {
  505. kfree(rt2x00dev->rx);
  506. rt2x00dev->rx = NULL;
  507. rt2x00dev->tx = NULL;
  508. rt2x00dev->bcn = NULL;
  509. }