processor_idle.c 46 KB

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  1. /*
  2. * processor_idle - idle state submodule to the ACPI processor driver
  3. *
  4. * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
  5. * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  6. * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de>
  7. * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  8. * - Added processor hotplug support
  9. * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
  10. * - Added support for C3 on SMP
  11. *
  12. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or (at
  17. * your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful, but
  20. * WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  22. * General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License along
  25. * with this program; if not, write to the Free Software Foundation, Inc.,
  26. * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  27. *
  28. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  29. */
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/cpufreq.h>
  34. #include <linux/proc_fs.h>
  35. #include <linux/seq_file.h>
  36. #include <linux/acpi.h>
  37. #include <linux/dmi.h>
  38. #include <linux/moduleparam.h>
  39. #include <linux/sched.h> /* need_resched() */
  40. #include <linux/latency.h>
  41. #include <linux/clockchips.h>
  42. #include <linux/cpuidle.h>
  43. /*
  44. * Include the apic definitions for x86 to have the APIC timer related defines
  45. * available also for UP (on SMP it gets magically included via linux/smp.h).
  46. * asm/acpi.h is not an option, as it would require more include magic. Also
  47. * creating an empty asm-ia64/apic.h would just trade pest vs. cholera.
  48. */
  49. #ifdef CONFIG_X86
  50. #include <asm/apic.h>
  51. #endif
  52. #include <asm/io.h>
  53. #include <asm/uaccess.h>
  54. #include <acpi/acpi_bus.h>
  55. #include <acpi/processor.h>
  56. #define ACPI_PROCESSOR_COMPONENT 0x01000000
  57. #define ACPI_PROCESSOR_CLASS "processor"
  58. #define _COMPONENT ACPI_PROCESSOR_COMPONENT
  59. ACPI_MODULE_NAME("processor_idle");
  60. #define ACPI_PROCESSOR_FILE_POWER "power"
  61. #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000)
  62. #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY)
  63. #ifndef CONFIG_CPU_IDLE
  64. #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */
  65. #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */
  66. static void (*pm_idle_save) (void) __read_mostly;
  67. #else
  68. #define C2_OVERHEAD 1 /* 1us */
  69. #define C3_OVERHEAD 1 /* 1us */
  70. #endif
  71. #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000))
  72. static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
  73. module_param(max_cstate, uint, 0000);
  74. static unsigned int nocst __read_mostly;
  75. module_param(nocst, uint, 0000);
  76. #ifndef CONFIG_CPU_IDLE
  77. /*
  78. * bm_history -- bit-mask with a bit per jiffy of bus-master activity
  79. * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms
  80. * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms
  81. * 100 HZ: 0x0000000F: 4 jiffies = 40ms
  82. * reduce history for more aggressive entry into C3
  83. */
  84. static unsigned int bm_history __read_mostly =
  85. (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1));
  86. module_param(bm_history, uint, 0644);
  87. static int acpi_processor_set_power_policy(struct acpi_processor *pr);
  88. #endif
  89. /*
  90. * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
  91. * For now disable this. Probably a bug somewhere else.
  92. *
  93. * To skip this limit, boot/load with a large max_cstate limit.
  94. */
  95. static int set_max_cstate(const struct dmi_system_id *id)
  96. {
  97. if (max_cstate > ACPI_PROCESSOR_MAX_POWER)
  98. return 0;
  99. printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate."
  100. " Override with \"processor.max_cstate=%d\"\n", id->ident,
  101. (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1);
  102. max_cstate = (long)id->driver_data;
  103. return 0;
  104. }
  105. /* Actually this shouldn't be __cpuinitdata, would be better to fix the
  106. callers to only run once -AK */
  107. static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = {
  108. { set_max_cstate, "IBM ThinkPad R40e", {
  109. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  110. DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1},
  111. { set_max_cstate, "IBM ThinkPad R40e", {
  112. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  113. DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1},
  114. { set_max_cstate, "IBM ThinkPad R40e", {
  115. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  116. DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1},
  117. { set_max_cstate, "IBM ThinkPad R40e", {
  118. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  119. DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1},
  120. { set_max_cstate, "IBM ThinkPad R40e", {
  121. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  122. DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1},
  123. { set_max_cstate, "IBM ThinkPad R40e", {
  124. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  125. DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1},
  126. { set_max_cstate, "IBM ThinkPad R40e", {
  127. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  128. DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1},
  129. { set_max_cstate, "IBM ThinkPad R40e", {
  130. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  131. DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1},
  132. { set_max_cstate, "IBM ThinkPad R40e", {
  133. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  134. DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1},
  135. { set_max_cstate, "IBM ThinkPad R40e", {
  136. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  137. DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1},
  138. { set_max_cstate, "IBM ThinkPad R40e", {
  139. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  140. DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1},
  141. { set_max_cstate, "IBM ThinkPad R40e", {
  142. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  143. DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1},
  144. { set_max_cstate, "IBM ThinkPad R40e", {
  145. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  146. DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1},
  147. { set_max_cstate, "IBM ThinkPad R40e", {
  148. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  149. DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1},
  150. { set_max_cstate, "IBM ThinkPad R40e", {
  151. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  152. DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1},
  153. { set_max_cstate, "IBM ThinkPad R40e", {
  154. DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
  155. DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1},
  156. { set_max_cstate, "Medion 41700", {
  157. DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
  158. DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1},
  159. { set_max_cstate, "Clevo 5600D", {
  160. DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
  161. DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")},
  162. (void *)2},
  163. {},
  164. };
  165. static inline u32 ticks_elapsed(u32 t1, u32 t2)
  166. {
  167. if (t2 >= t1)
  168. return (t2 - t1);
  169. else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
  170. return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
  171. else
  172. return ((0xFFFFFFFF - t1) + t2);
  173. }
  174. static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2)
  175. {
  176. if (t2 >= t1)
  177. return PM_TIMER_TICKS_TO_US(t2 - t1);
  178. else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
  179. return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
  180. else
  181. return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2);
  182. }
  183. static void acpi_safe_halt(void)
  184. {
  185. current_thread_info()->status &= ~TS_POLLING;
  186. /*
  187. * TS_POLLING-cleared state must be visible before we
  188. * test NEED_RESCHED:
  189. */
  190. smp_mb();
  191. if (!need_resched())
  192. safe_halt();
  193. current_thread_info()->status |= TS_POLLING;
  194. }
  195. #ifndef CONFIG_CPU_IDLE
  196. static void
  197. acpi_processor_power_activate(struct acpi_processor *pr,
  198. struct acpi_processor_cx *new)
  199. {
  200. struct acpi_processor_cx *old;
  201. if (!pr || !new)
  202. return;
  203. old = pr->power.state;
  204. if (old)
  205. old->promotion.count = 0;
  206. new->demotion.count = 0;
  207. /* Cleanup from old state. */
  208. if (old) {
  209. switch (old->type) {
  210. case ACPI_STATE_C3:
  211. /* Disable bus master reload */
  212. if (new->type != ACPI_STATE_C3 && pr->flags.bm_check)
  213. acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
  214. break;
  215. }
  216. }
  217. /* Prepare to use new state. */
  218. switch (new->type) {
  219. case ACPI_STATE_C3:
  220. /* Enable bus master reload */
  221. if (old->type != ACPI_STATE_C3 && pr->flags.bm_check)
  222. acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
  223. break;
  224. }
  225. pr->power.state = new;
  226. return;
  227. }
  228. static atomic_t c3_cpu_count;
  229. /* Common C-state entry for C2, C3, .. */
  230. static void acpi_cstate_enter(struct acpi_processor_cx *cstate)
  231. {
  232. if (cstate->space_id == ACPI_CSTATE_FFH) {
  233. /* Call into architectural FFH based C-state */
  234. acpi_processor_ffh_cstate_enter(cstate);
  235. } else {
  236. int unused;
  237. /* IO port based C-state */
  238. inb(cstate->address);
  239. /* Dummy wait op - must do something useless after P_LVL2 read
  240. because chipsets cannot guarantee that STPCLK# signal
  241. gets asserted in time to freeze execution properly. */
  242. unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
  243. }
  244. }
  245. #endif /* !CONFIG_CPU_IDLE */
  246. #ifdef ARCH_APICTIMER_STOPS_ON_C3
  247. /*
  248. * Some BIOS implementations switch to C3 in the published C2 state.
  249. * This seems to be a common problem on AMD boxen, but other vendors
  250. * are affected too. We pick the most conservative approach: we assume
  251. * that the local APIC stops in both C2 and C3.
  252. */
  253. static void acpi_timer_check_state(int state, struct acpi_processor *pr,
  254. struct acpi_processor_cx *cx)
  255. {
  256. struct acpi_processor_power *pwr = &pr->power;
  257. u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2;
  258. /*
  259. * Check, if one of the previous states already marked the lapic
  260. * unstable
  261. */
  262. if (pwr->timer_broadcast_on_state < state)
  263. return;
  264. if (cx->type >= type)
  265. pr->power.timer_broadcast_on_state = state;
  266. }
  267. static void acpi_propagate_timer_broadcast(struct acpi_processor *pr)
  268. {
  269. unsigned long reason;
  270. reason = pr->power.timer_broadcast_on_state < INT_MAX ?
  271. CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
  272. clockevents_notify(reason, &pr->id);
  273. }
  274. /* Power(C) State timer broadcast control */
  275. static void acpi_state_timer_broadcast(struct acpi_processor *pr,
  276. struct acpi_processor_cx *cx,
  277. int broadcast)
  278. {
  279. int state = cx - pr->power.states;
  280. if (state >= pr->power.timer_broadcast_on_state) {
  281. unsigned long reason;
  282. reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER :
  283. CLOCK_EVT_NOTIFY_BROADCAST_EXIT;
  284. clockevents_notify(reason, &pr->id);
  285. }
  286. }
  287. #else
  288. static void acpi_timer_check_state(int state, struct acpi_processor *pr,
  289. struct acpi_processor_cx *cstate) { }
  290. static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { }
  291. static void acpi_state_timer_broadcast(struct acpi_processor *pr,
  292. struct acpi_processor_cx *cx,
  293. int broadcast)
  294. {
  295. }
  296. #endif
  297. /*
  298. * Suspend / resume control
  299. */
  300. static int acpi_idle_suspend;
  301. int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
  302. {
  303. acpi_idle_suspend = 1;
  304. return 0;
  305. }
  306. int acpi_processor_resume(struct acpi_device * device)
  307. {
  308. acpi_idle_suspend = 0;
  309. return 0;
  310. }
  311. #ifndef CONFIG_CPU_IDLE
  312. static void acpi_processor_idle(void)
  313. {
  314. struct acpi_processor *pr = NULL;
  315. struct acpi_processor_cx *cx = NULL;
  316. struct acpi_processor_cx *next_state = NULL;
  317. int sleep_ticks = 0;
  318. u32 t1, t2 = 0;
  319. /*
  320. * Interrupts must be disabled during bus mastering calculations and
  321. * for C2/C3 transitions.
  322. */
  323. local_irq_disable();
  324. pr = processors[smp_processor_id()];
  325. if (!pr) {
  326. local_irq_enable();
  327. return;
  328. }
  329. /*
  330. * Check whether we truly need to go idle, or should
  331. * reschedule:
  332. */
  333. if (unlikely(need_resched())) {
  334. local_irq_enable();
  335. return;
  336. }
  337. cx = pr->power.state;
  338. if (!cx || acpi_idle_suspend) {
  339. if (pm_idle_save)
  340. pm_idle_save();
  341. else
  342. acpi_safe_halt();
  343. return;
  344. }
  345. /*
  346. * Check BM Activity
  347. * -----------------
  348. * Check for bus mastering activity (if required), record, and check
  349. * for demotion.
  350. */
  351. if (pr->flags.bm_check) {
  352. u32 bm_status = 0;
  353. unsigned long diff = jiffies - pr->power.bm_check_timestamp;
  354. if (diff > 31)
  355. diff = 31;
  356. pr->power.bm_activity <<= diff;
  357. acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
  358. if (bm_status) {
  359. pr->power.bm_activity |= 0x1;
  360. acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
  361. }
  362. /*
  363. * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
  364. * the true state of bus mastering activity; forcing us to
  365. * manually check the BMIDEA bit of each IDE channel.
  366. */
  367. else if (errata.piix4.bmisx) {
  368. if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
  369. || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
  370. pr->power.bm_activity |= 0x1;
  371. }
  372. pr->power.bm_check_timestamp = jiffies;
  373. /*
  374. * If bus mastering is or was active this jiffy, demote
  375. * to avoid a faulty transition. Note that the processor
  376. * won't enter a low-power state during this call (to this
  377. * function) but should upon the next.
  378. *
  379. * TBD: A better policy might be to fallback to the demotion
  380. * state (use it for this quantum only) istead of
  381. * demoting -- and rely on duration as our sole demotion
  382. * qualification. This may, however, introduce DMA
  383. * issues (e.g. floppy DMA transfer overrun/underrun).
  384. */
  385. if ((pr->power.bm_activity & 0x1) &&
  386. cx->demotion.threshold.bm) {
  387. local_irq_enable();
  388. next_state = cx->demotion.state;
  389. goto end;
  390. }
  391. }
  392. #ifdef CONFIG_HOTPLUG_CPU
  393. /*
  394. * Check for P_LVL2_UP flag before entering C2 and above on
  395. * an SMP system. We do it here instead of doing it at _CST/P_LVL
  396. * detection phase, to work cleanly with logical CPU hotplug.
  397. */
  398. if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
  399. !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
  400. cx = &pr->power.states[ACPI_STATE_C1];
  401. #endif
  402. /*
  403. * Sleep:
  404. * ------
  405. * Invoke the current Cx state to put the processor to sleep.
  406. */
  407. if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) {
  408. current_thread_info()->status &= ~TS_POLLING;
  409. /*
  410. * TS_POLLING-cleared state must be visible before we
  411. * test NEED_RESCHED:
  412. */
  413. smp_mb();
  414. if (need_resched()) {
  415. current_thread_info()->status |= TS_POLLING;
  416. local_irq_enable();
  417. return;
  418. }
  419. }
  420. switch (cx->type) {
  421. case ACPI_STATE_C1:
  422. /*
  423. * Invoke C1.
  424. * Use the appropriate idle routine, the one that would
  425. * be used without acpi C-states.
  426. */
  427. if (pm_idle_save)
  428. pm_idle_save();
  429. else
  430. acpi_safe_halt();
  431. /*
  432. * TBD: Can't get time duration while in C1, as resumes
  433. * go to an ISR rather than here. Need to instrument
  434. * base interrupt handler.
  435. *
  436. * Note: the TSC better not stop in C1, sched_clock() will
  437. * skew otherwise.
  438. */
  439. sleep_ticks = 0xFFFFFFFF;
  440. break;
  441. case ACPI_STATE_C2:
  442. /* Get start time (ticks) */
  443. t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
  444. /* Tell the scheduler that we are going deep-idle: */
  445. sched_clock_idle_sleep_event();
  446. /* Invoke C2 */
  447. acpi_state_timer_broadcast(pr, cx, 1);
  448. acpi_cstate_enter(cx);
  449. /* Get end time (ticks) */
  450. t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
  451. #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
  452. /* TSC halts in C2, so notify users */
  453. mark_tsc_unstable("possible TSC halt in C2");
  454. #endif
  455. /* Compute time (ticks) that we were actually asleep */
  456. sleep_ticks = ticks_elapsed(t1, t2);
  457. /* Tell the scheduler how much we idled: */
  458. sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
  459. /* Re-enable interrupts */
  460. local_irq_enable();
  461. /* Do not account our idle-switching overhead: */
  462. sleep_ticks -= cx->latency_ticks + C2_OVERHEAD;
  463. current_thread_info()->status |= TS_POLLING;
  464. acpi_state_timer_broadcast(pr, cx, 0);
  465. break;
  466. case ACPI_STATE_C3:
  467. /*
  468. * disable bus master
  469. * bm_check implies we need ARB_DIS
  470. * !bm_check implies we need cache flush
  471. * bm_control implies whether we can do ARB_DIS
  472. *
  473. * That leaves a case where bm_check is set and bm_control is
  474. * not set. In that case we cannot do much, we enter C3
  475. * without doing anything.
  476. */
  477. if (pr->flags.bm_check && pr->flags.bm_control) {
  478. if (atomic_inc_return(&c3_cpu_count) ==
  479. num_online_cpus()) {
  480. /*
  481. * All CPUs are trying to go to C3
  482. * Disable bus master arbitration
  483. */
  484. acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
  485. }
  486. } else if (!pr->flags.bm_check) {
  487. /* SMP with no shared cache... Invalidate cache */
  488. ACPI_FLUSH_CPU_CACHE();
  489. }
  490. /* Get start time (ticks) */
  491. t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
  492. /* Invoke C3 */
  493. acpi_state_timer_broadcast(pr, cx, 1);
  494. /* Tell the scheduler that we are going deep-idle: */
  495. sched_clock_idle_sleep_event();
  496. acpi_cstate_enter(cx);
  497. /* Get end time (ticks) */
  498. t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
  499. if (pr->flags.bm_check && pr->flags.bm_control) {
  500. /* Enable bus master arbitration */
  501. atomic_dec(&c3_cpu_count);
  502. acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
  503. }
  504. #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
  505. /* TSC halts in C3, so notify users */
  506. mark_tsc_unstable("TSC halts in C3");
  507. #endif
  508. /* Compute time (ticks) that we were actually asleep */
  509. sleep_ticks = ticks_elapsed(t1, t2);
  510. /* Tell the scheduler how much we idled: */
  511. sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
  512. /* Re-enable interrupts */
  513. local_irq_enable();
  514. /* Do not account our idle-switching overhead: */
  515. sleep_ticks -= cx->latency_ticks + C3_OVERHEAD;
  516. current_thread_info()->status |= TS_POLLING;
  517. acpi_state_timer_broadcast(pr, cx, 0);
  518. break;
  519. default:
  520. local_irq_enable();
  521. return;
  522. }
  523. cx->usage++;
  524. if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0))
  525. cx->time += sleep_ticks;
  526. next_state = pr->power.state;
  527. #ifdef CONFIG_HOTPLUG_CPU
  528. /* Don't do promotion/demotion */
  529. if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) &&
  530. !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) {
  531. next_state = cx;
  532. goto end;
  533. }
  534. #endif
  535. /*
  536. * Promotion?
  537. * ----------
  538. * Track the number of longs (time asleep is greater than threshold)
  539. * and promote when the count threshold is reached. Note that bus
  540. * mastering activity may prevent promotions.
  541. * Do not promote above max_cstate.
  542. */
  543. if (cx->promotion.state &&
  544. ((cx->promotion.state - pr->power.states) <= max_cstate)) {
  545. if (sleep_ticks > cx->promotion.threshold.ticks &&
  546. cx->promotion.state->latency <= system_latency_constraint()) {
  547. cx->promotion.count++;
  548. cx->demotion.count = 0;
  549. if (cx->promotion.count >=
  550. cx->promotion.threshold.count) {
  551. if (pr->flags.bm_check) {
  552. if (!
  553. (pr->power.bm_activity & cx->
  554. promotion.threshold.bm)) {
  555. next_state =
  556. cx->promotion.state;
  557. goto end;
  558. }
  559. } else {
  560. next_state = cx->promotion.state;
  561. goto end;
  562. }
  563. }
  564. }
  565. }
  566. /*
  567. * Demotion?
  568. * ---------
  569. * Track the number of shorts (time asleep is less than time threshold)
  570. * and demote when the usage threshold is reached.
  571. */
  572. if (cx->demotion.state) {
  573. if (sleep_ticks < cx->demotion.threshold.ticks) {
  574. cx->demotion.count++;
  575. cx->promotion.count = 0;
  576. if (cx->demotion.count >= cx->demotion.threshold.count) {
  577. next_state = cx->demotion.state;
  578. goto end;
  579. }
  580. }
  581. }
  582. end:
  583. /*
  584. * Demote if current state exceeds max_cstate
  585. * or if the latency of the current state is unacceptable
  586. */
  587. if ((pr->power.state - pr->power.states) > max_cstate ||
  588. pr->power.state->latency > system_latency_constraint()) {
  589. if (cx->demotion.state)
  590. next_state = cx->demotion.state;
  591. }
  592. /*
  593. * New Cx State?
  594. * -------------
  595. * If we're going to start using a new Cx state we must clean up
  596. * from the previous and prepare to use the new.
  597. */
  598. if (next_state != pr->power.state)
  599. acpi_processor_power_activate(pr, next_state);
  600. }
  601. static int acpi_processor_set_power_policy(struct acpi_processor *pr)
  602. {
  603. unsigned int i;
  604. unsigned int state_is_set = 0;
  605. struct acpi_processor_cx *lower = NULL;
  606. struct acpi_processor_cx *higher = NULL;
  607. struct acpi_processor_cx *cx;
  608. if (!pr)
  609. return -EINVAL;
  610. /*
  611. * This function sets the default Cx state policy (OS idle handler).
  612. * Our scheme is to promote quickly to C2 but more conservatively
  613. * to C3. We're favoring C2 for its characteristics of low latency
  614. * (quick response), good power savings, and ability to allow bus
  615. * mastering activity. Note that the Cx state policy is completely
  616. * customizable and can be altered dynamically.
  617. */
  618. /* startup state */
  619. for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
  620. cx = &pr->power.states[i];
  621. if (!cx->valid)
  622. continue;
  623. if (!state_is_set)
  624. pr->power.state = cx;
  625. state_is_set++;
  626. break;
  627. }
  628. if (!state_is_set)
  629. return -ENODEV;
  630. /* demotion */
  631. for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
  632. cx = &pr->power.states[i];
  633. if (!cx->valid)
  634. continue;
  635. if (lower) {
  636. cx->demotion.state = lower;
  637. cx->demotion.threshold.ticks = cx->latency_ticks;
  638. cx->demotion.threshold.count = 1;
  639. if (cx->type == ACPI_STATE_C3)
  640. cx->demotion.threshold.bm = bm_history;
  641. }
  642. lower = cx;
  643. }
  644. /* promotion */
  645. for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) {
  646. cx = &pr->power.states[i];
  647. if (!cx->valid)
  648. continue;
  649. if (higher) {
  650. cx->promotion.state = higher;
  651. cx->promotion.threshold.ticks = cx->latency_ticks;
  652. if (cx->type >= ACPI_STATE_C2)
  653. cx->promotion.threshold.count = 4;
  654. else
  655. cx->promotion.threshold.count = 10;
  656. if (higher->type == ACPI_STATE_C3)
  657. cx->promotion.threshold.bm = bm_history;
  658. }
  659. higher = cx;
  660. }
  661. return 0;
  662. }
  663. #endif /* !CONFIG_CPU_IDLE */
  664. static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
  665. {
  666. if (!pr)
  667. return -EINVAL;
  668. if (!pr->pblk)
  669. return -ENODEV;
  670. /* if info is obtained from pblk/fadt, type equals state */
  671. pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2;
  672. pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3;
  673. #ifndef CONFIG_HOTPLUG_CPU
  674. /*
  675. * Check for P_LVL2_UP flag before entering C2 and above on
  676. * an SMP system.
  677. */
  678. if ((num_online_cpus() > 1) &&
  679. !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
  680. return -ENODEV;
  681. #endif
  682. /* determine C2 and C3 address from pblk */
  683. pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4;
  684. pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5;
  685. /* determine latencies from FADT */
  686. pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency;
  687. pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency;
  688. ACPI_DEBUG_PRINT((ACPI_DB_INFO,
  689. "lvl2[0x%08x] lvl3[0x%08x]\n",
  690. pr->power.states[ACPI_STATE_C2].address,
  691. pr->power.states[ACPI_STATE_C3].address));
  692. return 0;
  693. }
  694. static int acpi_processor_get_power_info_default(struct acpi_processor *pr)
  695. {
  696. if (!pr->power.states[ACPI_STATE_C1].valid) {
  697. /* set the first C-State to C1 */
  698. /* all processors need to support C1 */
  699. pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
  700. pr->power.states[ACPI_STATE_C1].valid = 1;
  701. }
  702. /* the C0 state only exists as a filler in our array */
  703. pr->power.states[ACPI_STATE_C0].valid = 1;
  704. return 0;
  705. }
  706. static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
  707. {
  708. acpi_status status = 0;
  709. acpi_integer count;
  710. int current_count;
  711. int i;
  712. struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
  713. union acpi_object *cst;
  714. if (nocst)
  715. return -ENODEV;
  716. current_count = 0;
  717. status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
  718. if (ACPI_FAILURE(status)) {
  719. ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n"));
  720. return -ENODEV;
  721. }
  722. cst = buffer.pointer;
  723. /* There must be at least 2 elements */
  724. if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) {
  725. printk(KERN_ERR PREFIX "not enough elements in _CST\n");
  726. status = -EFAULT;
  727. goto end;
  728. }
  729. count = cst->package.elements[0].integer.value;
  730. /* Validate number of power states. */
  731. if (count < 1 || count != cst->package.count - 1) {
  732. printk(KERN_ERR PREFIX "count given by _CST is not valid\n");
  733. status = -EFAULT;
  734. goto end;
  735. }
  736. /* Tell driver that at least _CST is supported. */
  737. pr->flags.has_cst = 1;
  738. for (i = 1; i <= count; i++) {
  739. union acpi_object *element;
  740. union acpi_object *obj;
  741. struct acpi_power_register *reg;
  742. struct acpi_processor_cx cx;
  743. memset(&cx, 0, sizeof(cx));
  744. element = &(cst->package.elements[i]);
  745. if (element->type != ACPI_TYPE_PACKAGE)
  746. continue;
  747. if (element->package.count != 4)
  748. continue;
  749. obj = &(element->package.elements[0]);
  750. if (obj->type != ACPI_TYPE_BUFFER)
  751. continue;
  752. reg = (struct acpi_power_register *)obj->buffer.pointer;
  753. if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO &&
  754. (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
  755. continue;
  756. /* There should be an easy way to extract an integer... */
  757. obj = &(element->package.elements[1]);
  758. if (obj->type != ACPI_TYPE_INTEGER)
  759. continue;
  760. cx.type = obj->integer.value;
  761. /*
  762. * Some buggy BIOSes won't list C1 in _CST -
  763. * Let acpi_processor_get_power_info_default() handle them later
  764. */
  765. if (i == 1 && cx.type != ACPI_STATE_C1)
  766. current_count++;
  767. cx.address = reg->address;
  768. cx.index = current_count + 1;
  769. cx.space_id = ACPI_CSTATE_SYSTEMIO;
  770. if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
  771. if (acpi_processor_ffh_cstate_probe
  772. (pr->id, &cx, reg) == 0) {
  773. cx.space_id = ACPI_CSTATE_FFH;
  774. } else if (cx.type != ACPI_STATE_C1) {
  775. /*
  776. * C1 is a special case where FIXED_HARDWARE
  777. * can be handled in non-MWAIT way as well.
  778. * In that case, save this _CST entry info.
  779. * That is, we retain space_id of SYSTEM_IO for
  780. * halt based C1.
  781. * Otherwise, ignore this info and continue.
  782. */
  783. continue;
  784. }
  785. }
  786. obj = &(element->package.elements[2]);
  787. if (obj->type != ACPI_TYPE_INTEGER)
  788. continue;
  789. cx.latency = obj->integer.value;
  790. obj = &(element->package.elements[3]);
  791. if (obj->type != ACPI_TYPE_INTEGER)
  792. continue;
  793. cx.power = obj->integer.value;
  794. current_count++;
  795. memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx));
  796. /*
  797. * We support total ACPI_PROCESSOR_MAX_POWER - 1
  798. * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1)
  799. */
  800. if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) {
  801. printk(KERN_WARNING
  802. "Limiting number of power states to max (%d)\n",
  803. ACPI_PROCESSOR_MAX_POWER);
  804. printk(KERN_WARNING
  805. "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n");
  806. break;
  807. }
  808. }
  809. ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n",
  810. current_count));
  811. /* Validate number of power states discovered */
  812. if (current_count < 2)
  813. status = -EFAULT;
  814. end:
  815. kfree(buffer.pointer);
  816. return status;
  817. }
  818. static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx)
  819. {
  820. if (!cx->address)
  821. return;
  822. /*
  823. * C2 latency must be less than or equal to 100
  824. * microseconds.
  825. */
  826. else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) {
  827. ACPI_DEBUG_PRINT((ACPI_DB_INFO,
  828. "latency too large [%d]\n", cx->latency));
  829. return;
  830. }
  831. /*
  832. * Otherwise we've met all of our C2 requirements.
  833. * Normalize the C2 latency to expidite policy
  834. */
  835. cx->valid = 1;
  836. #ifndef CONFIG_CPU_IDLE
  837. cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
  838. #else
  839. cx->latency_ticks = cx->latency;
  840. #endif
  841. return;
  842. }
  843. static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
  844. struct acpi_processor_cx *cx)
  845. {
  846. static int bm_check_flag;
  847. if (!cx->address)
  848. return;
  849. /*
  850. * C3 latency must be less than or equal to 1000
  851. * microseconds.
  852. */
  853. else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) {
  854. ACPI_DEBUG_PRINT((ACPI_DB_INFO,
  855. "latency too large [%d]\n", cx->latency));
  856. return;
  857. }
  858. /*
  859. * PIIX4 Erratum #18: We don't support C3 when Type-F (fast)
  860. * DMA transfers are used by any ISA device to avoid livelock.
  861. * Note that we could disable Type-F DMA (as recommended by
  862. * the erratum), but this is known to disrupt certain ISA
  863. * devices thus we take the conservative approach.
  864. */
  865. else if (errata.piix4.fdma) {
  866. ACPI_DEBUG_PRINT((ACPI_DB_INFO,
  867. "C3 not supported on PIIX4 with Type-F DMA\n"));
  868. return;
  869. }
  870. /* All the logic here assumes flags.bm_check is same across all CPUs */
  871. if (!bm_check_flag) {
  872. /* Determine whether bm_check is needed based on CPU */
  873. acpi_processor_power_init_bm_check(&(pr->flags), pr->id);
  874. bm_check_flag = pr->flags.bm_check;
  875. } else {
  876. pr->flags.bm_check = bm_check_flag;
  877. }
  878. if (pr->flags.bm_check) {
  879. if (!pr->flags.bm_control) {
  880. if (pr->flags.has_cst != 1) {
  881. /* bus mastering control is necessary */
  882. ACPI_DEBUG_PRINT((ACPI_DB_INFO,
  883. "C3 support requires BM control\n"));
  884. return;
  885. } else {
  886. /* Here we enter C3 without bus mastering */
  887. ACPI_DEBUG_PRINT((ACPI_DB_INFO,
  888. "C3 support without BM control\n"));
  889. }
  890. }
  891. } else {
  892. /*
  893. * WBINVD should be set in fadt, for C3 state to be
  894. * supported on when bm_check is not required.
  895. */
  896. if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) {
  897. ACPI_DEBUG_PRINT((ACPI_DB_INFO,
  898. "Cache invalidation should work properly"
  899. " for C3 to be enabled on SMP systems\n"));
  900. return;
  901. }
  902. acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
  903. }
  904. /*
  905. * Otherwise we've met all of our C3 requirements.
  906. * Normalize the C3 latency to expidite policy. Enable
  907. * checking of bus mastering status (bm_check) so we can
  908. * use this in our C3 policy
  909. */
  910. cx->valid = 1;
  911. #ifndef CONFIG_CPU_IDLE
  912. cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
  913. #else
  914. cx->latency_ticks = cx->latency;
  915. #endif
  916. return;
  917. }
  918. static int acpi_processor_power_verify(struct acpi_processor *pr)
  919. {
  920. unsigned int i;
  921. unsigned int working = 0;
  922. pr->power.timer_broadcast_on_state = INT_MAX;
  923. for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
  924. struct acpi_processor_cx *cx = &pr->power.states[i];
  925. switch (cx->type) {
  926. case ACPI_STATE_C1:
  927. cx->valid = 1;
  928. break;
  929. case ACPI_STATE_C2:
  930. acpi_processor_power_verify_c2(cx);
  931. if (cx->valid)
  932. acpi_timer_check_state(i, pr, cx);
  933. break;
  934. case ACPI_STATE_C3:
  935. acpi_processor_power_verify_c3(pr, cx);
  936. if (cx->valid)
  937. acpi_timer_check_state(i, pr, cx);
  938. break;
  939. }
  940. if (cx->valid)
  941. working++;
  942. }
  943. acpi_propagate_timer_broadcast(pr);
  944. return (working);
  945. }
  946. static int acpi_processor_get_power_info(struct acpi_processor *pr)
  947. {
  948. unsigned int i;
  949. int result;
  950. /* NOTE: the idle thread may not be running while calling
  951. * this function */
  952. /* Zero initialize all the C-states info. */
  953. memset(pr->power.states, 0, sizeof(pr->power.states));
  954. result = acpi_processor_get_power_info_cst(pr);
  955. if (result == -ENODEV)
  956. result = acpi_processor_get_power_info_fadt(pr);
  957. if (result)
  958. return result;
  959. acpi_processor_get_power_info_default(pr);
  960. pr->power.count = acpi_processor_power_verify(pr);
  961. #ifndef CONFIG_CPU_IDLE
  962. /*
  963. * Set Default Policy
  964. * ------------------
  965. * Now that we know which states are supported, set the default
  966. * policy. Note that this policy can be changed dynamically
  967. * (e.g. encourage deeper sleeps to conserve battery life when
  968. * not on AC).
  969. */
  970. result = acpi_processor_set_power_policy(pr);
  971. if (result)
  972. return result;
  973. #endif
  974. /*
  975. * if one state of type C2 or C3 is available, mark this
  976. * CPU as being "idle manageable"
  977. */
  978. for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
  979. if (pr->power.states[i].valid) {
  980. pr->power.count = i;
  981. if (pr->power.states[i].type >= ACPI_STATE_C2)
  982. pr->flags.power = 1;
  983. }
  984. }
  985. return 0;
  986. }
  987. static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset)
  988. {
  989. struct acpi_processor *pr = seq->private;
  990. unsigned int i;
  991. if (!pr)
  992. goto end;
  993. seq_printf(seq, "active state: C%zd\n"
  994. "max_cstate: C%d\n"
  995. "bus master activity: %08x\n"
  996. "maximum allowed latency: %d usec\n",
  997. pr->power.state ? pr->power.state - pr->power.states : 0,
  998. max_cstate, (unsigned)pr->power.bm_activity,
  999. system_latency_constraint());
  1000. seq_puts(seq, "states:\n");
  1001. for (i = 1; i <= pr->power.count; i++) {
  1002. seq_printf(seq, " %cC%d: ",
  1003. (&pr->power.states[i] ==
  1004. pr->power.state ? '*' : ' '), i);
  1005. if (!pr->power.states[i].valid) {
  1006. seq_puts(seq, "<not supported>\n");
  1007. continue;
  1008. }
  1009. switch (pr->power.states[i].type) {
  1010. case ACPI_STATE_C1:
  1011. seq_printf(seq, "type[C1] ");
  1012. break;
  1013. case ACPI_STATE_C2:
  1014. seq_printf(seq, "type[C2] ");
  1015. break;
  1016. case ACPI_STATE_C3:
  1017. seq_printf(seq, "type[C3] ");
  1018. break;
  1019. default:
  1020. seq_printf(seq, "type[--] ");
  1021. break;
  1022. }
  1023. if (pr->power.states[i].promotion.state)
  1024. seq_printf(seq, "promotion[C%zd] ",
  1025. (pr->power.states[i].promotion.state -
  1026. pr->power.states));
  1027. else
  1028. seq_puts(seq, "promotion[--] ");
  1029. if (pr->power.states[i].demotion.state)
  1030. seq_printf(seq, "demotion[C%zd] ",
  1031. (pr->power.states[i].demotion.state -
  1032. pr->power.states));
  1033. else
  1034. seq_puts(seq, "demotion[--] ");
  1035. seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n",
  1036. pr->power.states[i].latency,
  1037. pr->power.states[i].usage,
  1038. (unsigned long long)pr->power.states[i].time);
  1039. }
  1040. end:
  1041. return 0;
  1042. }
  1043. static int acpi_processor_power_open_fs(struct inode *inode, struct file *file)
  1044. {
  1045. return single_open(file, acpi_processor_power_seq_show,
  1046. PDE(inode)->data);
  1047. }
  1048. static const struct file_operations acpi_processor_power_fops = {
  1049. .open = acpi_processor_power_open_fs,
  1050. .read = seq_read,
  1051. .llseek = seq_lseek,
  1052. .release = single_release,
  1053. };
  1054. #ifndef CONFIG_CPU_IDLE
  1055. int acpi_processor_cst_has_changed(struct acpi_processor *pr)
  1056. {
  1057. int result = 0;
  1058. if (!pr)
  1059. return -EINVAL;
  1060. if (nocst) {
  1061. return -ENODEV;
  1062. }
  1063. if (!pr->flags.power_setup_done)
  1064. return -ENODEV;
  1065. /* Fall back to the default idle loop */
  1066. pm_idle = pm_idle_save;
  1067. synchronize_sched(); /* Relies on interrupts forcing exit from idle. */
  1068. pr->flags.power = 0;
  1069. result = acpi_processor_get_power_info(pr);
  1070. if ((pr->flags.power == 1) && (pr->flags.power_setup_done))
  1071. pm_idle = acpi_processor_idle;
  1072. return result;
  1073. }
  1074. #ifdef CONFIG_SMP
  1075. static void smp_callback(void *v)
  1076. {
  1077. /* we already woke the CPU up, nothing more to do */
  1078. }
  1079. /*
  1080. * This function gets called when a part of the kernel has a new latency
  1081. * requirement. This means we need to get all processors out of their C-state,
  1082. * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that
  1083. * wakes them all right up.
  1084. */
  1085. static int acpi_processor_latency_notify(struct notifier_block *b,
  1086. unsigned long l, void *v)
  1087. {
  1088. smp_call_function(smp_callback, NULL, 0, 1);
  1089. return NOTIFY_OK;
  1090. }
  1091. static struct notifier_block acpi_processor_latency_notifier = {
  1092. .notifier_call = acpi_processor_latency_notify,
  1093. };
  1094. #endif
  1095. #else /* CONFIG_CPU_IDLE */
  1096. /**
  1097. * acpi_idle_bm_check - checks if bus master activity was detected
  1098. */
  1099. static int acpi_idle_bm_check(void)
  1100. {
  1101. u32 bm_status = 0;
  1102. acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
  1103. if (bm_status)
  1104. acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
  1105. /*
  1106. * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
  1107. * the true state of bus mastering activity; forcing us to
  1108. * manually check the BMIDEA bit of each IDE channel.
  1109. */
  1110. else if (errata.piix4.bmisx) {
  1111. if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
  1112. || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
  1113. bm_status = 1;
  1114. }
  1115. return bm_status;
  1116. }
  1117. /**
  1118. * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state
  1119. * @pr: the processor
  1120. * @target: the new target state
  1121. */
  1122. static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr,
  1123. struct acpi_processor_cx *target)
  1124. {
  1125. if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) {
  1126. acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
  1127. pr->flags.bm_rld_set = 0;
  1128. }
  1129. if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) {
  1130. acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
  1131. pr->flags.bm_rld_set = 1;
  1132. }
  1133. }
  1134. /**
  1135. * acpi_idle_do_entry - a helper function that does C2 and C3 type entry
  1136. * @cx: cstate data
  1137. */
  1138. static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx)
  1139. {
  1140. if (cx->space_id == ACPI_CSTATE_FFH) {
  1141. /* Call into architectural FFH based C-state */
  1142. acpi_processor_ffh_cstate_enter(cx);
  1143. } else {
  1144. int unused;
  1145. /* IO port based C-state */
  1146. inb(cx->address);
  1147. /* Dummy wait op - must do something useless after P_LVL2 read
  1148. because chipsets cannot guarantee that STPCLK# signal
  1149. gets asserted in time to freeze execution properly. */
  1150. unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
  1151. }
  1152. }
  1153. /**
  1154. * acpi_idle_enter_c1 - enters an ACPI C1 state-type
  1155. * @dev: the target CPU
  1156. * @state: the state data
  1157. *
  1158. * This is equivalent to the HALT instruction.
  1159. */
  1160. static int acpi_idle_enter_c1(struct cpuidle_device *dev,
  1161. struct cpuidle_state *state)
  1162. {
  1163. struct acpi_processor *pr;
  1164. struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
  1165. pr = processors[smp_processor_id()];
  1166. if (unlikely(!pr))
  1167. return 0;
  1168. if (pr->flags.bm_check)
  1169. acpi_idle_update_bm_rld(pr, cx);
  1170. acpi_safe_halt();
  1171. cx->usage++;
  1172. return 0;
  1173. }
  1174. /**
  1175. * acpi_idle_enter_simple - enters an ACPI state without BM handling
  1176. * @dev: the target CPU
  1177. * @state: the state data
  1178. */
  1179. static int acpi_idle_enter_simple(struct cpuidle_device *dev,
  1180. struct cpuidle_state *state)
  1181. {
  1182. struct acpi_processor *pr;
  1183. struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
  1184. u32 t1, t2;
  1185. int sleep_ticks = 0;
  1186. pr = processors[smp_processor_id()];
  1187. if (unlikely(!pr))
  1188. return 0;
  1189. if (acpi_idle_suspend)
  1190. return(acpi_idle_enter_c1(dev, state));
  1191. if (pr->flags.bm_check)
  1192. acpi_idle_update_bm_rld(pr, cx);
  1193. local_irq_disable();
  1194. current_thread_info()->status &= ~TS_POLLING;
  1195. /*
  1196. * TS_POLLING-cleared state must be visible before we test
  1197. * NEED_RESCHED:
  1198. */
  1199. smp_mb();
  1200. if (unlikely(need_resched())) {
  1201. current_thread_info()->status |= TS_POLLING;
  1202. local_irq_enable();
  1203. return 0;
  1204. }
  1205. if (cx->type == ACPI_STATE_C3)
  1206. ACPI_FLUSH_CPU_CACHE();
  1207. t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
  1208. /* Tell the scheduler that we are going deep-idle: */
  1209. sched_clock_idle_sleep_event();
  1210. acpi_state_timer_broadcast(pr, cx, 1);
  1211. acpi_idle_do_entry(cx);
  1212. t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
  1213. #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
  1214. /* TSC could halt in idle, so notify users */
  1215. mark_tsc_unstable("TSC halts in idle");;
  1216. #endif
  1217. sleep_ticks = ticks_elapsed(t1, t2);
  1218. /* Tell the scheduler how much we idled: */
  1219. sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
  1220. local_irq_enable();
  1221. current_thread_info()->status |= TS_POLLING;
  1222. cx->usage++;
  1223. acpi_state_timer_broadcast(pr, cx, 0);
  1224. cx->time += sleep_ticks;
  1225. return ticks_elapsed_in_us(t1, t2);
  1226. }
  1227. static int c3_cpu_count;
  1228. static DEFINE_SPINLOCK(c3_lock);
  1229. /**
  1230. * acpi_idle_enter_bm - enters C3 with proper BM handling
  1231. * @dev: the target CPU
  1232. * @state: the state data
  1233. *
  1234. * If BM is detected, the deepest non-C3 idle state is entered instead.
  1235. */
  1236. static int acpi_idle_enter_bm(struct cpuidle_device *dev,
  1237. struct cpuidle_state *state)
  1238. {
  1239. struct acpi_processor *pr;
  1240. struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
  1241. u32 t1, t2;
  1242. int sleep_ticks = 0;
  1243. pr = processors[smp_processor_id()];
  1244. if (unlikely(!pr))
  1245. return 0;
  1246. if (acpi_idle_suspend)
  1247. return(acpi_idle_enter_c1(dev, state));
  1248. if (acpi_idle_bm_check()) {
  1249. if (dev->safe_state) {
  1250. return dev->safe_state->enter(dev, dev->safe_state);
  1251. } else {
  1252. acpi_safe_halt();
  1253. return 0;
  1254. }
  1255. }
  1256. local_irq_disable();
  1257. current_thread_info()->status &= ~TS_POLLING;
  1258. /*
  1259. * TS_POLLING-cleared state must be visible before we test
  1260. * NEED_RESCHED:
  1261. */
  1262. smp_mb();
  1263. if (unlikely(need_resched())) {
  1264. current_thread_info()->status |= TS_POLLING;
  1265. local_irq_enable();
  1266. return 0;
  1267. }
  1268. /* Tell the scheduler that we are going deep-idle: */
  1269. sched_clock_idle_sleep_event();
  1270. /*
  1271. * Must be done before busmaster disable as we might need to
  1272. * access HPET !
  1273. */
  1274. acpi_state_timer_broadcast(pr, cx, 1);
  1275. acpi_idle_update_bm_rld(pr, cx);
  1276. /*
  1277. * disable bus master
  1278. * bm_check implies we need ARB_DIS
  1279. * !bm_check implies we need cache flush
  1280. * bm_control implies whether we can do ARB_DIS
  1281. *
  1282. * That leaves a case where bm_check is set and bm_control is
  1283. * not set. In that case we cannot do much, we enter C3
  1284. * without doing anything.
  1285. */
  1286. if (pr->flags.bm_check && pr->flags.bm_control) {
  1287. spin_lock(&c3_lock);
  1288. c3_cpu_count++;
  1289. /* Disable bus master arbitration when all CPUs are in C3 */
  1290. if (c3_cpu_count == num_online_cpus())
  1291. acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
  1292. spin_unlock(&c3_lock);
  1293. } else if (!pr->flags.bm_check) {
  1294. ACPI_FLUSH_CPU_CACHE();
  1295. }
  1296. t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
  1297. acpi_idle_do_entry(cx);
  1298. t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
  1299. /* Re-enable bus master arbitration */
  1300. if (pr->flags.bm_check && pr->flags.bm_control) {
  1301. spin_lock(&c3_lock);
  1302. acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
  1303. c3_cpu_count--;
  1304. spin_unlock(&c3_lock);
  1305. }
  1306. #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
  1307. /* TSC could halt in idle, so notify users */
  1308. mark_tsc_unstable("TSC halts in idle");
  1309. #endif
  1310. sleep_ticks = ticks_elapsed(t1, t2);
  1311. /* Tell the scheduler how much we idled: */
  1312. sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
  1313. local_irq_enable();
  1314. current_thread_info()->status |= TS_POLLING;
  1315. cx->usage++;
  1316. acpi_state_timer_broadcast(pr, cx, 0);
  1317. cx->time += sleep_ticks;
  1318. return ticks_elapsed_in_us(t1, t2);
  1319. }
  1320. struct cpuidle_driver acpi_idle_driver = {
  1321. .name = "acpi_idle",
  1322. .owner = THIS_MODULE,
  1323. };
  1324. /**
  1325. * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE
  1326. * @pr: the ACPI processor
  1327. */
  1328. static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
  1329. {
  1330. int i, count = 0;
  1331. struct acpi_processor_cx *cx;
  1332. struct cpuidle_state *state;
  1333. struct cpuidle_device *dev = &pr->power.dev;
  1334. if (!pr->flags.power_setup_done)
  1335. return -EINVAL;
  1336. if (pr->flags.power == 0) {
  1337. return -EINVAL;
  1338. }
  1339. for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
  1340. cx = &pr->power.states[i];
  1341. state = &dev->states[count];
  1342. if (!cx->valid)
  1343. continue;
  1344. #ifdef CONFIG_HOTPLUG_CPU
  1345. if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
  1346. !pr->flags.has_cst &&
  1347. !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
  1348. continue;
  1349. #endif
  1350. cpuidle_set_statedata(state, cx);
  1351. snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i);
  1352. state->exit_latency = cx->latency;
  1353. state->target_residency = cx->latency * 6;
  1354. state->power_usage = cx->power;
  1355. state->flags = 0;
  1356. switch (cx->type) {
  1357. case ACPI_STATE_C1:
  1358. state->flags |= CPUIDLE_FLAG_SHALLOW;
  1359. state->enter = acpi_idle_enter_c1;
  1360. dev->safe_state = state;
  1361. break;
  1362. case ACPI_STATE_C2:
  1363. state->flags |= CPUIDLE_FLAG_BALANCED;
  1364. state->flags |= CPUIDLE_FLAG_TIME_VALID;
  1365. state->enter = acpi_idle_enter_simple;
  1366. dev->safe_state = state;
  1367. break;
  1368. case ACPI_STATE_C3:
  1369. state->flags |= CPUIDLE_FLAG_DEEP;
  1370. state->flags |= CPUIDLE_FLAG_TIME_VALID;
  1371. state->flags |= CPUIDLE_FLAG_CHECK_BM;
  1372. state->enter = pr->flags.bm_check ?
  1373. acpi_idle_enter_bm :
  1374. acpi_idle_enter_simple;
  1375. break;
  1376. }
  1377. count++;
  1378. }
  1379. dev->state_count = count;
  1380. if (!count)
  1381. return -EINVAL;
  1382. return 0;
  1383. }
  1384. int acpi_processor_cst_has_changed(struct acpi_processor *pr)
  1385. {
  1386. int ret;
  1387. if (!pr)
  1388. return -EINVAL;
  1389. if (nocst) {
  1390. return -ENODEV;
  1391. }
  1392. if (!pr->flags.power_setup_done)
  1393. return -ENODEV;
  1394. cpuidle_pause_and_lock();
  1395. cpuidle_disable_device(&pr->power.dev);
  1396. acpi_processor_get_power_info(pr);
  1397. acpi_processor_setup_cpuidle(pr);
  1398. ret = cpuidle_enable_device(&pr->power.dev);
  1399. cpuidle_resume_and_unlock();
  1400. return ret;
  1401. }
  1402. #endif /* CONFIG_CPU_IDLE */
  1403. int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
  1404. struct acpi_device *device)
  1405. {
  1406. acpi_status status = 0;
  1407. static int first_run;
  1408. struct proc_dir_entry *entry = NULL;
  1409. unsigned int i;
  1410. if (!first_run) {
  1411. dmi_check_system(processor_power_dmi_table);
  1412. max_cstate = acpi_processor_cstate_check(max_cstate);
  1413. if (max_cstate < ACPI_C_STATES_MAX)
  1414. printk(KERN_NOTICE
  1415. "ACPI: processor limited to max C-state %d\n",
  1416. max_cstate);
  1417. first_run++;
  1418. #if !defined (CONFIG_CPU_IDLE) && defined (CONFIG_SMP)
  1419. register_latency_notifier(&acpi_processor_latency_notifier);
  1420. #endif
  1421. }
  1422. if (!pr)
  1423. return -EINVAL;
  1424. if (acpi_gbl_FADT.cst_control && !nocst) {
  1425. status =
  1426. acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8);
  1427. if (ACPI_FAILURE(status)) {
  1428. ACPI_EXCEPTION((AE_INFO, status,
  1429. "Notifying BIOS of _CST ability failed"));
  1430. }
  1431. }
  1432. acpi_processor_get_power_info(pr);
  1433. pr->flags.power_setup_done = 1;
  1434. /*
  1435. * Install the idle handler if processor power management is supported.
  1436. * Note that we use previously set idle handler will be used on
  1437. * platforms that only support C1.
  1438. */
  1439. if ((pr->flags.power) && (!boot_option_idle_override)) {
  1440. #ifdef CONFIG_CPU_IDLE
  1441. acpi_processor_setup_cpuidle(pr);
  1442. pr->power.dev.cpu = pr->id;
  1443. if (cpuidle_register_device(&pr->power.dev))
  1444. return -EIO;
  1445. #endif
  1446. printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id);
  1447. for (i = 1; i <= pr->power.count; i++)
  1448. if (pr->power.states[i].valid)
  1449. printk(" C%d[C%d]", i,
  1450. pr->power.states[i].type);
  1451. printk(")\n");
  1452. #ifndef CONFIG_CPU_IDLE
  1453. if (pr->id == 0) {
  1454. pm_idle_save = pm_idle;
  1455. pm_idle = acpi_processor_idle;
  1456. }
  1457. #endif
  1458. }
  1459. /* 'power' [R] */
  1460. entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER,
  1461. S_IRUGO, acpi_device_dir(device));
  1462. if (!entry)
  1463. return -EIO;
  1464. else {
  1465. entry->proc_fops = &acpi_processor_power_fops;
  1466. entry->data = acpi_driver_data(device);
  1467. entry->owner = THIS_MODULE;
  1468. }
  1469. return 0;
  1470. }
  1471. int acpi_processor_power_exit(struct acpi_processor *pr,
  1472. struct acpi_device *device)
  1473. {
  1474. #ifdef CONFIG_CPU_IDLE
  1475. if ((pr->flags.power) && (!boot_option_idle_override))
  1476. cpuidle_unregister_device(&pr->power.dev);
  1477. #endif
  1478. pr->flags.power_setup_done = 0;
  1479. if (acpi_device_dir(device))
  1480. remove_proc_entry(ACPI_PROCESSOR_FILE_POWER,
  1481. acpi_device_dir(device));
  1482. #ifndef CONFIG_CPU_IDLE
  1483. /* Unregister the idle handler when processor #0 is removed. */
  1484. if (pr->id == 0) {
  1485. pm_idle = pm_idle_save;
  1486. /*
  1487. * We are about to unload the current idle thread pm callback
  1488. * (pm_idle), Wait for all processors to update cached/local
  1489. * copies of pm_idle before proceeding.
  1490. */
  1491. cpu_idle_wait();
  1492. #ifdef CONFIG_SMP
  1493. unregister_latency_notifier(&acpi_processor_latency_notifier);
  1494. #endif
  1495. }
  1496. #endif
  1497. return 0;
  1498. }