Kconfig 13 KB

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  1. comment "Processor Type"
  2. config CPU_32
  3. bool
  4. default y
  5. # Select CPU types depending on the architecture selected. This selects
  6. # which CPUs we support in the kernel image, and the compiler instruction
  7. # optimiser behaviour.
  8. # ARM610
  9. config CPU_ARM610
  10. bool "Support ARM610 processor"
  11. depends on ARCH_RPC
  12. select CPU_32v3
  13. select CPU_CACHE_V3
  14. select CPU_CACHE_VIVT
  15. select CPU_CP15_MMU
  16. select CPU_COPY_V3 if MMU
  17. select CPU_TLB_V3 if MMU
  18. help
  19. The ARM610 is the successor to the ARM3 processor
  20. and was produced by VLSI Technology Inc.
  21. Say Y if you want support for the ARM610 processor.
  22. Otherwise, say N.
  23. # ARM710
  24. config CPU_ARM710
  25. bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
  26. default y if ARCH_CLPS7500
  27. select CPU_32v3
  28. select CPU_CACHE_V3
  29. select CPU_CACHE_VIVT
  30. select CPU_CP15_MMU
  31. select CPU_COPY_V3 if MMU
  32. select CPU_TLB_V3 if MMU
  33. help
  34. A 32-bit RISC microprocessor based on the ARM7 processor core
  35. designed by Advanced RISC Machines Ltd. The ARM710 is the
  36. successor to the ARM610 processor. It was released in
  37. July 1994 by VLSI Technology Inc.
  38. Say Y if you want support for the ARM710 processor.
  39. Otherwise, say N.
  40. # ARM720T
  41. config CPU_ARM720T
  42. bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
  43. default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
  44. select CPU_32v4T
  45. select CPU_ABRT_LV4T
  46. select CPU_CACHE_V4
  47. select CPU_CACHE_VIVT
  48. select CPU_CP15_MMU
  49. select CPU_COPY_V4WT if MMU
  50. select CPU_TLB_V4WT if MMU
  51. help
  52. A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  53. MMU built around an ARM7TDMI core.
  54. Say Y if you want support for the ARM720T processor.
  55. Otherwise, say N.
  56. # ARM920T
  57. config CPU_ARM920T
  58. bool "Support ARM920T processor"
  59. depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
  60. default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
  61. select CPU_32v4T
  62. select CPU_ABRT_EV4T
  63. select CPU_CACHE_V4WT
  64. select CPU_CACHE_VIVT
  65. select CPU_CP15_MMU
  66. select CPU_COPY_V4WB if MMU
  67. select CPU_TLB_V4WBI if MMU
  68. help
  69. The ARM920T is licensed to be produced by numerous vendors,
  70. and is used in the Maverick EP9312 and the Samsung S3C2410.
  71. More information on the Maverick EP9312 at
  72. <http://linuxdevices.com/products/PD2382866068.html>.
  73. Say Y if you want support for the ARM920T processor.
  74. Otherwise, say N.
  75. # ARM922T
  76. config CPU_ARM922T
  77. bool "Support ARM922T processor" if ARCH_INTEGRATOR
  78. depends on ARCH_LH7A40X || ARCH_INTEGRATOR
  79. default y if ARCH_LH7A40X
  80. select CPU_32v4T
  81. select CPU_ABRT_EV4T
  82. select CPU_CACHE_V4WT
  83. select CPU_CACHE_VIVT
  84. select CPU_CP15_MMU
  85. select CPU_COPY_V4WB if MMU
  86. select CPU_TLB_V4WBI if MMU
  87. help
  88. The ARM922T is a version of the ARM920T, but with smaller
  89. instruction and data caches. It is used in Altera's
  90. Excalibur XA device family.
  91. Say Y if you want support for the ARM922T processor.
  92. Otherwise, say N.
  93. # ARM925T
  94. config CPU_ARM925T
  95. bool "Support ARM925T processor" if ARCH_OMAP1
  96. depends on ARCH_OMAP15XX
  97. default y if ARCH_OMAP15XX
  98. select CPU_32v4T
  99. select CPU_ABRT_EV4T
  100. select CPU_CACHE_V4WT
  101. select CPU_CACHE_VIVT
  102. select CPU_CP15_MMU
  103. select CPU_COPY_V4WB if MMU
  104. select CPU_TLB_V4WBI if MMU
  105. help
  106. The ARM925T is a mix between the ARM920T and ARM926T, but with
  107. different instruction and data caches. It is used in TI's OMAP
  108. device family.
  109. Say Y if you want support for the ARM925T processor.
  110. Otherwise, say N.
  111. # ARM926T
  112. config CPU_ARM926T
  113. bool "Support ARM926T processor"
  114. depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
  115. default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
  116. select CPU_32v5
  117. select CPU_ABRT_EV5TJ
  118. select CPU_CACHE_VIVT
  119. select CPU_CP15_MMU
  120. select CPU_COPY_V4WB if MMU
  121. select CPU_TLB_V4WBI if MMU
  122. help
  123. This is a variant of the ARM920. It has slightly different
  124. instruction sequences for cache and TLB operations. Curiously,
  125. there is no documentation on it at the ARM corporate website.
  126. Say Y if you want support for the ARM926T processor.
  127. Otherwise, say N.
  128. # ARM1020 - needs validating
  129. config CPU_ARM1020
  130. bool "Support ARM1020T (rev 0) processor"
  131. depends on ARCH_INTEGRATOR
  132. select CPU_32v5
  133. select CPU_ABRT_EV4T
  134. select CPU_CACHE_V4WT
  135. select CPU_CACHE_VIVT
  136. select CPU_CP15_MMU
  137. select CPU_COPY_V4WB if MMU
  138. select CPU_TLB_V4WBI if MMU
  139. help
  140. The ARM1020 is the 32K cached version of the ARM10 processor,
  141. with an addition of a floating-point unit.
  142. Say Y if you want support for the ARM1020 processor.
  143. Otherwise, say N.
  144. # ARM1020E - needs validating
  145. config CPU_ARM1020E
  146. bool "Support ARM1020E processor"
  147. depends on ARCH_INTEGRATOR
  148. select CPU_32v5
  149. select CPU_ABRT_EV4T
  150. select CPU_CACHE_V4WT
  151. select CPU_CACHE_VIVT
  152. select CPU_CP15_MMU
  153. select CPU_COPY_V4WB if MMU
  154. select CPU_TLB_V4WBI if MMU
  155. depends on n
  156. # ARM1022E
  157. config CPU_ARM1022
  158. bool "Support ARM1022E processor"
  159. depends on ARCH_INTEGRATOR
  160. select CPU_32v5
  161. select CPU_ABRT_EV4T
  162. select CPU_CACHE_VIVT
  163. select CPU_CP15_MMU
  164. select CPU_COPY_V4WB if MMU # can probably do better
  165. select CPU_TLB_V4WBI if MMU
  166. help
  167. The ARM1022E is an implementation of the ARMv5TE architecture
  168. based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
  169. embedded trace macrocell, and a floating-point unit.
  170. Say Y if you want support for the ARM1022E processor.
  171. Otherwise, say N.
  172. # ARM1026EJ-S
  173. config CPU_ARM1026
  174. bool "Support ARM1026EJ-S processor"
  175. depends on ARCH_INTEGRATOR
  176. select CPU_32v5
  177. select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
  178. select CPU_CACHE_VIVT
  179. select CPU_CP15_MMU
  180. select CPU_COPY_V4WB if MMU # can probably do better
  181. select CPU_TLB_V4WBI if MMU
  182. help
  183. The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
  184. based upon the ARM10 integer core.
  185. Say Y if you want support for the ARM1026EJ-S processor.
  186. Otherwise, say N.
  187. # SA110
  188. config CPU_SA110
  189. bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
  190. default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
  191. select CPU_32v3 if ARCH_RPC
  192. select CPU_32v4 if !ARCH_RPC
  193. select CPU_ABRT_EV4
  194. select CPU_CACHE_V4WB
  195. select CPU_CACHE_VIVT
  196. select CPU_CP15_MMU
  197. select CPU_COPY_V4WB if MMU
  198. select CPU_TLB_V4WB if MMU
  199. help
  200. The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
  201. is available at five speeds ranging from 100 MHz to 233 MHz.
  202. More information is available at
  203. <http://developer.intel.com/design/strong/sa110.htm>.
  204. Say Y if you want support for the SA-110 processor.
  205. Otherwise, say N.
  206. # SA1100
  207. config CPU_SA1100
  208. bool
  209. depends on ARCH_SA1100
  210. default y
  211. select CPU_32v4
  212. select CPU_ABRT_EV4
  213. select CPU_CACHE_V4WB
  214. select CPU_CACHE_VIVT
  215. select CPU_CP15_MMU
  216. select CPU_TLB_V4WB if MMU
  217. # XScale
  218. config CPU_XSCALE
  219. bool
  220. depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
  221. default y
  222. select CPU_32v5
  223. select CPU_ABRT_EV5T
  224. select CPU_CACHE_VIVT
  225. select CPU_CP15_MMU
  226. select CPU_TLB_V4WBI if MMU
  227. # XScale Core Version 3
  228. config CPU_XSC3
  229. bool
  230. depends on ARCH_IXP23XX
  231. default y
  232. select CPU_32v5
  233. select CPU_ABRT_EV5T
  234. select CPU_CACHE_VIVT
  235. select CPU_CP15_MMU
  236. select CPU_TLB_V4WBI if MMU
  237. select IO_36
  238. # ARMv6
  239. config CPU_V6
  240. bool "Support ARM V6 processor"
  241. depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
  242. select CPU_32v6
  243. select CPU_ABRT_EV6
  244. select CPU_CACHE_V6
  245. select CPU_CACHE_VIPT
  246. select CPU_CP15_MMU
  247. select CPU_COPY_V6 if MMU
  248. select CPU_TLB_V6 if MMU
  249. # ARMv6k
  250. config CPU_32v6K
  251. bool "Support ARM V6K processor extensions" if !SMP
  252. depends on CPU_V6
  253. default y if SMP
  254. help
  255. Say Y here if your ARMv6 processor supports the 'K' extension.
  256. This enables the kernel to use some instructions not present
  257. on previous processors, and as such a kernel build with this
  258. enabled will not boot on processors with do not support these
  259. instructions.
  260. # Figure out what processor architecture version we should be using.
  261. # This defines the compiler instruction set which depends on the machine type.
  262. config CPU_32v3
  263. bool
  264. select TLS_REG_EMUL if SMP || !MMU
  265. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  266. config CPU_32v4
  267. bool
  268. select TLS_REG_EMUL if SMP || !MMU
  269. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  270. config CPU_32v4T
  271. bool
  272. select TLS_REG_EMUL if SMP || !MMU
  273. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  274. config CPU_32v5
  275. bool
  276. select TLS_REG_EMUL if SMP || !MMU
  277. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  278. config CPU_32v6
  279. bool
  280. # The abort model
  281. config CPU_ABRT_EV4
  282. bool
  283. config CPU_ABRT_EV4T
  284. bool
  285. config CPU_ABRT_LV4T
  286. bool
  287. config CPU_ABRT_EV5T
  288. bool
  289. config CPU_ABRT_EV5TJ
  290. bool
  291. config CPU_ABRT_EV6
  292. bool
  293. # The cache model
  294. config CPU_CACHE_V3
  295. bool
  296. config CPU_CACHE_V4
  297. bool
  298. config CPU_CACHE_V4WT
  299. bool
  300. config CPU_CACHE_V4WB
  301. bool
  302. config CPU_CACHE_V6
  303. bool
  304. config CPU_CACHE_VIVT
  305. bool
  306. config CPU_CACHE_VIPT
  307. bool
  308. if MMU
  309. # The copy-page model
  310. config CPU_COPY_V3
  311. bool
  312. config CPU_COPY_V4WT
  313. bool
  314. config CPU_COPY_V4WB
  315. bool
  316. config CPU_COPY_V6
  317. bool
  318. # This selects the TLB model
  319. config CPU_TLB_V3
  320. bool
  321. help
  322. ARM Architecture Version 3 TLB.
  323. config CPU_TLB_V4WT
  324. bool
  325. help
  326. ARM Architecture Version 4 TLB with writethrough cache.
  327. config CPU_TLB_V4WB
  328. bool
  329. help
  330. ARM Architecture Version 4 TLB with writeback cache.
  331. config CPU_TLB_V4WBI
  332. bool
  333. help
  334. ARM Architecture Version 4 TLB with writeback cache and invalidate
  335. instruction cache entry.
  336. config CPU_TLB_V6
  337. bool
  338. endif
  339. config CPU_CP15
  340. bool
  341. help
  342. Processor has the CP15 register.
  343. config CPU_CP15_MMU
  344. bool
  345. select CPU_CP15
  346. help
  347. Processor has the CP15 register, which has MMU related registers.
  348. config CPU_CP15_MPU
  349. bool
  350. select CPU_CP15
  351. help
  352. Processor has the CP15 register, which has MPU related registers.
  353. #
  354. # CPU supports 36-bit I/O
  355. #
  356. config IO_36
  357. bool
  358. comment "Processor Features"
  359. config ARM_THUMB
  360. bool "Support Thumb user binaries"
  361. depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
  362. default y
  363. help
  364. Say Y if you want to include kernel support for running user space
  365. Thumb binaries.
  366. The Thumb instruction set is a compressed form of the standard ARM
  367. instruction set resulting in smaller binaries at the expense of
  368. slightly less efficient code.
  369. If you don't know what this all is, saying Y is a safe choice.
  370. config CPU_BIG_ENDIAN
  371. bool "Build big-endian kernel"
  372. depends on ARCH_SUPPORTS_BIG_ENDIAN
  373. help
  374. Say Y if you plan on running a kernel in big-endian mode.
  375. Note that your board must be properly built and your board
  376. port must properly enable any big-endian related features
  377. of your chipset/board/processor.
  378. config CPU_ICACHE_DISABLE
  379. bool "Disable I-Cache"
  380. depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
  381. help
  382. Say Y here to disable the processor instruction cache. Unless
  383. you have a reason not to or are unsure, say N.
  384. config CPU_DCACHE_DISABLE
  385. bool "Disable D-Cache"
  386. depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
  387. help
  388. Say Y here to disable the processor data cache. Unless
  389. you have a reason not to or are unsure, say N.
  390. config CPU_DCACHE_WRITETHROUGH
  391. bool "Force write through D-cache"
  392. depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
  393. default y if CPU_ARM925T
  394. help
  395. Say Y here to use the data cache in writethrough mode. Unless you
  396. specifically require this or are unsure, say N.
  397. config CPU_CACHE_ROUND_ROBIN
  398. bool "Round robin I and D cache replacement algorithm"
  399. depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
  400. help
  401. Say Y here to use the predictable round-robin cache replacement
  402. policy. Unless you specifically require this or are unsure, say N.
  403. config CPU_BPREDICT_DISABLE
  404. bool "Disable branch prediction"
  405. depends on CPU_ARM1020 || CPU_V6
  406. help
  407. Say Y here to disable branch prediction. If unsure, say N.
  408. config TLS_REG_EMUL
  409. bool
  410. help
  411. An SMP system using a pre-ARMv6 processor (there are apparently
  412. a few prototypes like that in existence) and therefore access to
  413. that required register must be emulated.
  414. config HAS_TLS_REG
  415. bool
  416. depends on !TLS_REG_EMUL
  417. default y if SMP || CPU_32v7
  418. help
  419. This selects support for the CP15 thread register.
  420. It is defined to be available on some ARMv6 processors (including
  421. all SMP capable ARMv6's) or later processors. User space may
  422. assume directly accessing that register and always obtain the
  423. expected value only on ARMv7 and above.
  424. config NEEDS_SYSCALL_FOR_CMPXCHG
  425. bool
  426. help
  427. SMP on a pre-ARMv6 processor? Well OK then.
  428. Forget about fast user space cmpxchg support.
  429. It is just not possible.