m66592-udc.c 42 KB

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  1. /*
  2. * M66592 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2007 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/usb/ch9.h>
  28. #include <linux/usb/gadget.h>
  29. #include "m66592-udc.h"
  30. MODULE_DESCRIPTION("M66592 USB gadget driver");
  31. MODULE_LICENSE("GPL");
  32. MODULE_AUTHOR("Yoshihiro Shimoda");
  33. #define DRIVER_VERSION "18 Oct 2007"
  34. /* module parameters */
  35. #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
  36. static unsigned short endian = M66592_LITTLE;
  37. module_param(endian, ushort, 0644);
  38. MODULE_PARM_DESC(endian, "data endian: big=0, little=0 (default=0)");
  39. #else
  40. static unsigned short clock = M66592_XTAL24;
  41. module_param(clock, ushort, 0644);
  42. MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
  43. "(default=16384)");
  44. static unsigned short vif = M66592_LDRV;
  45. module_param(vif, ushort, 0644);
  46. MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0 (default=32768)");
  47. static unsigned short endian;
  48. module_param(endian, ushort, 0644);
  49. MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)");
  50. static unsigned short irq_sense = M66592_INTL;
  51. module_param(irq_sense, ushort, 0644);
  52. MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0 "
  53. "(default=2)");
  54. #endif
  55. static const char udc_name[] = "m66592_udc";
  56. static const char *m66592_ep_name[] = {
  57. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
  58. };
  59. static void disable_controller(struct m66592 *m66592);
  60. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
  61. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
  62. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  63. gfp_t gfp_flags);
  64. static void transfer_complete(struct m66592_ep *ep,
  65. struct m66592_request *req, int status);
  66. /*-------------------------------------------------------------------------*/
  67. static inline u16 get_usb_speed(struct m66592 *m66592)
  68. {
  69. return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
  70. }
  71. static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  72. unsigned long reg)
  73. {
  74. u16 tmp;
  75. tmp = m66592_read(m66592, M66592_INTENB0);
  76. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  77. M66592_INTENB0);
  78. m66592_bset(m66592, (1 << pipenum), reg);
  79. m66592_write(m66592, tmp, M66592_INTENB0);
  80. }
  81. static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  82. unsigned long reg)
  83. {
  84. u16 tmp;
  85. tmp = m66592_read(m66592, M66592_INTENB0);
  86. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  87. M66592_INTENB0);
  88. m66592_bclr(m66592, (1 << pipenum), reg);
  89. m66592_write(m66592, tmp, M66592_INTENB0);
  90. }
  91. static void m66592_usb_connect(struct m66592 *m66592)
  92. {
  93. m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
  94. m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  95. M66592_INTENB0);
  96. m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  97. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  98. }
  99. static void m66592_usb_disconnect(struct m66592 *m66592)
  100. __releases(m66592->lock)
  101. __acquires(m66592->lock)
  102. {
  103. m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
  104. m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  105. M66592_INTENB0);
  106. m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  107. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  108. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  109. spin_unlock(&m66592->lock);
  110. m66592->driver->disconnect(&m66592->gadget);
  111. spin_lock(&m66592->lock);
  112. disable_controller(m66592);
  113. INIT_LIST_HEAD(&m66592->ep[0].queue);
  114. }
  115. static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
  116. {
  117. u16 pid = 0;
  118. unsigned long offset;
  119. if (pipenum == 0)
  120. pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
  121. else if (pipenum < M66592_MAX_NUM_PIPE) {
  122. offset = get_pipectr_addr(pipenum);
  123. pid = m66592_read(m66592, offset) & M66592_PID;
  124. } else
  125. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  126. return pid;
  127. }
  128. static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
  129. u16 pid)
  130. {
  131. unsigned long offset;
  132. if (pipenum == 0)
  133. m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
  134. else if (pipenum < M66592_MAX_NUM_PIPE) {
  135. offset = get_pipectr_addr(pipenum);
  136. m66592_mdfy(m66592, pid, M66592_PID, offset);
  137. } else
  138. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  139. }
  140. static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
  141. {
  142. control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
  143. }
  144. static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
  145. {
  146. control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
  147. }
  148. static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
  149. {
  150. control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
  151. }
  152. static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
  153. {
  154. u16 ret = 0;
  155. unsigned long offset;
  156. if (pipenum == 0)
  157. ret = m66592_read(m66592, M66592_DCPCTR);
  158. else if (pipenum < M66592_MAX_NUM_PIPE) {
  159. offset = get_pipectr_addr(pipenum);
  160. ret = m66592_read(m66592, offset);
  161. } else
  162. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  163. return ret;
  164. }
  165. static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
  166. {
  167. unsigned long offset;
  168. pipe_stop(m66592, pipenum);
  169. if (pipenum == 0)
  170. m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
  171. else if (pipenum < M66592_MAX_NUM_PIPE) {
  172. offset = get_pipectr_addr(pipenum);
  173. m66592_bset(m66592, M66592_SQCLR, offset);
  174. } else
  175. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  176. }
  177. static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
  178. {
  179. u16 tmp;
  180. int size;
  181. if (pipenum == 0) {
  182. tmp = m66592_read(m66592, M66592_DCPCFG);
  183. if ((tmp & M66592_CNTMD) != 0)
  184. size = 256;
  185. else {
  186. tmp = m66592_read(m66592, M66592_DCPMAXP);
  187. size = tmp & M66592_MAXP;
  188. }
  189. } else {
  190. m66592_write(m66592, pipenum, M66592_PIPESEL);
  191. tmp = m66592_read(m66592, M66592_PIPECFG);
  192. if ((tmp & M66592_CNTMD) != 0) {
  193. tmp = m66592_read(m66592, M66592_PIPEBUF);
  194. size = ((tmp >> 10) + 1) * 64;
  195. } else {
  196. tmp = m66592_read(m66592, M66592_PIPEMAXP);
  197. size = tmp & M66592_MXPS;
  198. }
  199. }
  200. return size;
  201. }
  202. static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
  203. {
  204. struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
  205. if (ep->use_dma)
  206. return;
  207. m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
  208. ndelay(450);
  209. m66592_bset(m66592, M66592_MBW, ep->fifosel);
  210. }
  211. static int pipe_buffer_setting(struct m66592 *m66592,
  212. struct m66592_pipe_info *info)
  213. {
  214. u16 bufnum = 0, buf_bsize = 0;
  215. u16 pipecfg = 0;
  216. if (info->pipe == 0)
  217. return -EINVAL;
  218. m66592_write(m66592, info->pipe, M66592_PIPESEL);
  219. if (info->dir_in)
  220. pipecfg |= M66592_DIR;
  221. pipecfg |= info->type;
  222. pipecfg |= info->epnum;
  223. switch (info->type) {
  224. case M66592_INT:
  225. bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
  226. buf_bsize = 0;
  227. break;
  228. case M66592_BULK:
  229. bufnum = m66592->bi_bufnum +
  230. (info->pipe - M66592_BASE_PIPENUM_BULK) * 16;
  231. m66592->bi_bufnum += 16;
  232. buf_bsize = 7;
  233. pipecfg |= M66592_DBLB;
  234. if (!info->dir_in)
  235. pipecfg |= M66592_SHTNAK;
  236. break;
  237. case M66592_ISO:
  238. bufnum = m66592->bi_bufnum +
  239. (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
  240. m66592->bi_bufnum += 16;
  241. buf_bsize = 7;
  242. break;
  243. }
  244. if (m66592->bi_bufnum > M66592_MAX_BUFNUM) {
  245. printk(KERN_ERR "m66592 pipe memory is insufficient(%d)\n",
  246. m66592->bi_bufnum);
  247. return -ENOMEM;
  248. }
  249. m66592_write(m66592, pipecfg, M66592_PIPECFG);
  250. m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
  251. m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
  252. if (info->interval)
  253. info->interval--;
  254. m66592_write(m66592, info->interval, M66592_PIPEPERI);
  255. return 0;
  256. }
  257. static void pipe_buffer_release(struct m66592 *m66592,
  258. struct m66592_pipe_info *info)
  259. {
  260. if (info->pipe == 0)
  261. return;
  262. switch (info->type) {
  263. case M66592_BULK:
  264. if (is_bulk_pipe(info->pipe))
  265. m66592->bi_bufnum -= 16;
  266. break;
  267. case M66592_ISO:
  268. if (is_isoc_pipe(info->pipe))
  269. m66592->bi_bufnum -= 16;
  270. break;
  271. }
  272. if (is_bulk_pipe(info->pipe)) {
  273. m66592->bulk--;
  274. } else if (is_interrupt_pipe(info->pipe))
  275. m66592->interrupt--;
  276. else if (is_isoc_pipe(info->pipe)) {
  277. m66592->isochronous--;
  278. if (info->type == M66592_BULK)
  279. m66592->bulk--;
  280. } else
  281. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  282. info->pipe);
  283. }
  284. static void pipe_initialize(struct m66592_ep *ep)
  285. {
  286. struct m66592 *m66592 = ep->m66592;
  287. m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
  288. m66592_write(m66592, M66592_ACLRM, ep->pipectr);
  289. m66592_write(m66592, 0, ep->pipectr);
  290. m66592_write(m66592, M66592_SQCLR, ep->pipectr);
  291. if (ep->use_dma) {
  292. m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
  293. ndelay(450);
  294. m66592_bset(m66592, M66592_MBW, ep->fifosel);
  295. }
  296. }
  297. static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
  298. const struct usb_endpoint_descriptor *desc,
  299. u16 pipenum, int dma)
  300. {
  301. if ((pipenum != 0) && dma) {
  302. if (m66592->num_dma == 0) {
  303. m66592->num_dma++;
  304. ep->use_dma = 1;
  305. ep->fifoaddr = M66592_D0FIFO;
  306. ep->fifosel = M66592_D0FIFOSEL;
  307. ep->fifoctr = M66592_D0FIFOCTR;
  308. ep->fifotrn = M66592_D0FIFOTRN;
  309. #if !defined(CONFIG_SUPERH_BUILT_IN_M66592)
  310. } else if (m66592->num_dma == 1) {
  311. m66592->num_dma++;
  312. ep->use_dma = 1;
  313. ep->fifoaddr = M66592_D1FIFO;
  314. ep->fifosel = M66592_D1FIFOSEL;
  315. ep->fifoctr = M66592_D1FIFOCTR;
  316. ep->fifotrn = M66592_D1FIFOTRN;
  317. #endif
  318. } else {
  319. ep->use_dma = 0;
  320. ep->fifoaddr = M66592_CFIFO;
  321. ep->fifosel = M66592_CFIFOSEL;
  322. ep->fifoctr = M66592_CFIFOCTR;
  323. ep->fifotrn = 0;
  324. }
  325. } else {
  326. ep->use_dma = 0;
  327. ep->fifoaddr = M66592_CFIFO;
  328. ep->fifosel = M66592_CFIFOSEL;
  329. ep->fifoctr = M66592_CFIFOCTR;
  330. ep->fifotrn = 0;
  331. }
  332. ep->pipectr = get_pipectr_addr(pipenum);
  333. ep->pipenum = pipenum;
  334. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  335. m66592->pipenum2ep[pipenum] = ep;
  336. m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
  337. INIT_LIST_HEAD(&ep->queue);
  338. }
  339. static void m66592_ep_release(struct m66592_ep *ep)
  340. {
  341. struct m66592 *m66592 = ep->m66592;
  342. u16 pipenum = ep->pipenum;
  343. if (pipenum == 0)
  344. return;
  345. if (ep->use_dma)
  346. m66592->num_dma--;
  347. ep->pipenum = 0;
  348. ep->busy = 0;
  349. ep->use_dma = 0;
  350. }
  351. static int alloc_pipe_config(struct m66592_ep *ep,
  352. const struct usb_endpoint_descriptor *desc)
  353. {
  354. struct m66592 *m66592 = ep->m66592;
  355. struct m66592_pipe_info info;
  356. int dma = 0;
  357. int *counter;
  358. int ret;
  359. ep->desc = desc;
  360. BUG_ON(ep->pipenum);
  361. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  362. case USB_ENDPOINT_XFER_BULK:
  363. if (m66592->bulk >= M66592_MAX_NUM_BULK) {
  364. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  365. printk(KERN_ERR "bulk pipe is insufficient\n");
  366. return -ENODEV;
  367. } else {
  368. info.pipe = M66592_BASE_PIPENUM_ISOC
  369. + m66592->isochronous;
  370. counter = &m66592->isochronous;
  371. }
  372. } else {
  373. info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
  374. counter = &m66592->bulk;
  375. }
  376. info.type = M66592_BULK;
  377. dma = 1;
  378. break;
  379. case USB_ENDPOINT_XFER_INT:
  380. if (m66592->interrupt >= M66592_MAX_NUM_INT) {
  381. printk(KERN_ERR "interrupt pipe is insufficient\n");
  382. return -ENODEV;
  383. }
  384. info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
  385. info.type = M66592_INT;
  386. counter = &m66592->interrupt;
  387. break;
  388. case USB_ENDPOINT_XFER_ISOC:
  389. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  390. printk(KERN_ERR "isochronous pipe is insufficient\n");
  391. return -ENODEV;
  392. }
  393. info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
  394. info.type = M66592_ISO;
  395. counter = &m66592->isochronous;
  396. break;
  397. default:
  398. printk(KERN_ERR "unexpect xfer type\n");
  399. return -EINVAL;
  400. }
  401. ep->type = info.type;
  402. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  403. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  404. info.interval = desc->bInterval;
  405. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  406. info.dir_in = 1;
  407. else
  408. info.dir_in = 0;
  409. ret = pipe_buffer_setting(m66592, &info);
  410. if (ret < 0) {
  411. printk(KERN_ERR "pipe_buffer_setting fail\n");
  412. return ret;
  413. }
  414. (*counter)++;
  415. if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
  416. m66592->bulk++;
  417. m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
  418. pipe_initialize(ep);
  419. return 0;
  420. }
  421. static int free_pipe_config(struct m66592_ep *ep)
  422. {
  423. struct m66592 *m66592 = ep->m66592;
  424. struct m66592_pipe_info info;
  425. info.pipe = ep->pipenum;
  426. info.type = ep->type;
  427. pipe_buffer_release(m66592, &info);
  428. m66592_ep_release(ep);
  429. return 0;
  430. }
  431. /*-------------------------------------------------------------------------*/
  432. static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
  433. {
  434. enable_irq_ready(m66592, pipenum);
  435. enable_irq_nrdy(m66592, pipenum);
  436. }
  437. static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
  438. {
  439. disable_irq_ready(m66592, pipenum);
  440. disable_irq_nrdy(m66592, pipenum);
  441. }
  442. /* if complete is true, gadget driver complete function is not call */
  443. static void control_end(struct m66592 *m66592, unsigned ccpl)
  444. {
  445. m66592->ep[0].internal_ccpl = ccpl;
  446. pipe_start(m66592, 0);
  447. m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
  448. }
  449. static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  450. {
  451. struct m66592 *m66592 = ep->m66592;
  452. pipe_change(m66592, ep->pipenum);
  453. m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
  454. (M66592_ISEL | M66592_CURPIPE),
  455. M66592_CFIFOSEL);
  456. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  457. if (req->req.length == 0) {
  458. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  459. pipe_start(m66592, 0);
  460. transfer_complete(ep, req, 0);
  461. } else {
  462. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  463. irq_ep0_write(ep, req);
  464. }
  465. }
  466. static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  467. {
  468. struct m66592 *m66592 = ep->m66592;
  469. u16 tmp;
  470. pipe_change(m66592, ep->pipenum);
  471. disable_irq_empty(m66592, ep->pipenum);
  472. pipe_start(m66592, ep->pipenum);
  473. tmp = m66592_read(m66592, ep->fifoctr);
  474. if (unlikely((tmp & M66592_FRDY) == 0))
  475. pipe_irq_enable(m66592, ep->pipenum);
  476. else
  477. irq_packet_write(ep, req);
  478. }
  479. static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  480. {
  481. struct m66592 *m66592 = ep->m66592;
  482. u16 pipenum = ep->pipenum;
  483. if (ep->pipenum == 0) {
  484. m66592_mdfy(m66592, M66592_PIPE0,
  485. (M66592_ISEL | M66592_CURPIPE),
  486. M66592_CFIFOSEL);
  487. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  488. pipe_start(m66592, pipenum);
  489. pipe_irq_enable(m66592, pipenum);
  490. } else {
  491. if (ep->use_dma) {
  492. m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
  493. pipe_change(m66592, pipenum);
  494. m66592_bset(m66592, M66592_TRENB, ep->fifosel);
  495. m66592_write(m66592,
  496. (req->req.length + ep->ep.maxpacket - 1)
  497. / ep->ep.maxpacket,
  498. ep->fifotrn);
  499. }
  500. pipe_start(m66592, pipenum); /* trigger once */
  501. pipe_irq_enable(m66592, pipenum);
  502. }
  503. }
  504. static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
  505. {
  506. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  507. start_packet_write(ep, req);
  508. else
  509. start_packet_read(ep, req);
  510. }
  511. static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
  512. {
  513. u16 ctsq;
  514. ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
  515. switch (ctsq) {
  516. case M66592_CS_RDDS:
  517. start_ep0_write(ep, req);
  518. break;
  519. case M66592_CS_WRDS:
  520. start_packet_read(ep, req);
  521. break;
  522. case M66592_CS_WRND:
  523. control_end(ep->m66592, 0);
  524. break;
  525. default:
  526. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  527. break;
  528. }
  529. }
  530. #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
  531. static void init_controller(struct m66592 *m66592)
  532. {
  533. usbf_start_clock();
  534. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  535. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  536. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  537. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  538. /* This is a workaound for SH7722 2nd cut */
  539. m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
  540. m66592_bset(m66592, 0x1000, M66592_TESTMODE);
  541. m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
  542. m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
  543. m66592_write(m66592, 0, M66592_CFBCFG);
  544. m66592_write(m66592, 0, M66592_D0FBCFG);
  545. m66592_bset(m66592, endian, M66592_CFBCFG);
  546. m66592_bset(m66592, endian, M66592_D0FBCFG);
  547. }
  548. #else /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
  549. static void init_controller(struct m66592 *m66592)
  550. {
  551. m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND),
  552. M66592_PINCFG);
  553. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  554. m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG);
  555. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  556. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  557. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  558. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  559. msleep(3);
  560. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  561. msleep(1);
  562. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  563. m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
  564. m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
  565. M66592_DMA0CFG);
  566. }
  567. #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
  568. static void disable_controller(struct m66592 *m66592)
  569. {
  570. #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
  571. usbf_stop_clock();
  572. #else
  573. m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
  574. udelay(1);
  575. m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
  576. udelay(1);
  577. m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
  578. udelay(1);
  579. m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
  580. #endif
  581. }
  582. static void m66592_start_xclock(struct m66592 *m66592)
  583. {
  584. #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
  585. usbf_start_clock();
  586. #else
  587. u16 tmp;
  588. tmp = m66592_read(m66592, M66592_SYSCFG);
  589. if (!(tmp & M66592_XCKE))
  590. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  591. #endif
  592. }
  593. /*-------------------------------------------------------------------------*/
  594. static void transfer_complete(struct m66592_ep *ep,
  595. struct m66592_request *req, int status)
  596. __releases(m66592->lock)
  597. __acquires(m66592->lock)
  598. {
  599. int restart = 0;
  600. if (unlikely(ep->pipenum == 0)) {
  601. if (ep->internal_ccpl) {
  602. ep->internal_ccpl = 0;
  603. return;
  604. }
  605. }
  606. list_del_init(&req->queue);
  607. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  608. req->req.status = -ESHUTDOWN;
  609. else
  610. req->req.status = status;
  611. if (!list_empty(&ep->queue))
  612. restart = 1;
  613. spin_unlock(&ep->m66592->lock);
  614. req->req.complete(&ep->ep, &req->req);
  615. spin_lock(&ep->m66592->lock);
  616. if (restart) {
  617. req = list_entry(ep->queue.next, struct m66592_request, queue);
  618. if (ep->desc)
  619. start_packet(ep, req);
  620. }
  621. }
  622. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  623. {
  624. int i;
  625. u16 tmp;
  626. unsigned bufsize;
  627. size_t size;
  628. void *buf;
  629. u16 pipenum = ep->pipenum;
  630. struct m66592 *m66592 = ep->m66592;
  631. pipe_change(m66592, pipenum);
  632. m66592_bset(m66592, M66592_ISEL, ep->fifosel);
  633. i = 0;
  634. do {
  635. tmp = m66592_read(m66592, ep->fifoctr);
  636. if (i++ > 100000) {
  637. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus "
  638. "conflict. please power off this controller.");
  639. return;
  640. }
  641. ndelay(1);
  642. } while ((tmp & M66592_FRDY) == 0);
  643. /* prepare parameters */
  644. bufsize = get_buffer_size(m66592, pipenum);
  645. buf = req->req.buf + req->req.actual;
  646. size = min(bufsize, req->req.length - req->req.actual);
  647. /* write fifo */
  648. if (req->req.buf) {
  649. if (size > 0)
  650. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  651. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  652. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  653. }
  654. /* update parameters */
  655. req->req.actual += size;
  656. /* check transfer finish */
  657. if ((!req->req.zero && (req->req.actual == req->req.length))
  658. || (size % ep->ep.maxpacket)
  659. || (size == 0)) {
  660. disable_irq_ready(m66592, pipenum);
  661. disable_irq_empty(m66592, pipenum);
  662. } else {
  663. disable_irq_ready(m66592, pipenum);
  664. enable_irq_empty(m66592, pipenum);
  665. }
  666. pipe_start(m66592, pipenum);
  667. }
  668. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  669. {
  670. u16 tmp;
  671. unsigned bufsize;
  672. size_t size;
  673. void *buf;
  674. u16 pipenum = ep->pipenum;
  675. struct m66592 *m66592 = ep->m66592;
  676. pipe_change(m66592, pipenum);
  677. tmp = m66592_read(m66592, ep->fifoctr);
  678. if (unlikely((tmp & M66592_FRDY) == 0)) {
  679. pipe_stop(m66592, pipenum);
  680. pipe_irq_disable(m66592, pipenum);
  681. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  682. return;
  683. }
  684. /* prepare parameters */
  685. bufsize = get_buffer_size(m66592, pipenum);
  686. buf = req->req.buf + req->req.actual;
  687. size = min(bufsize, req->req.length - req->req.actual);
  688. /* write fifo */
  689. if (req->req.buf) {
  690. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  691. if ((size == 0)
  692. || ((size % ep->ep.maxpacket) != 0)
  693. || ((bufsize != ep->ep.maxpacket)
  694. && (bufsize > size)))
  695. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  696. }
  697. /* update parameters */
  698. req->req.actual += size;
  699. /* check transfer finish */
  700. if ((!req->req.zero && (req->req.actual == req->req.length))
  701. || (size % ep->ep.maxpacket)
  702. || (size == 0)) {
  703. disable_irq_ready(m66592, pipenum);
  704. enable_irq_empty(m66592, pipenum);
  705. } else {
  706. disable_irq_empty(m66592, pipenum);
  707. pipe_irq_enable(m66592, pipenum);
  708. }
  709. }
  710. static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  711. {
  712. u16 tmp;
  713. int rcv_len, bufsize, req_len;
  714. int size;
  715. void *buf;
  716. u16 pipenum = ep->pipenum;
  717. struct m66592 *m66592 = ep->m66592;
  718. int finish = 0;
  719. pipe_change(m66592, pipenum);
  720. tmp = m66592_read(m66592, ep->fifoctr);
  721. if (unlikely((tmp & M66592_FRDY) == 0)) {
  722. req->req.status = -EPIPE;
  723. pipe_stop(m66592, pipenum);
  724. pipe_irq_disable(m66592, pipenum);
  725. printk(KERN_ERR "read fifo not ready");
  726. return;
  727. }
  728. /* prepare parameters */
  729. rcv_len = tmp & M66592_DTLN;
  730. bufsize = get_buffer_size(m66592, pipenum);
  731. buf = req->req.buf + req->req.actual;
  732. req_len = req->req.length - req->req.actual;
  733. if (rcv_len < bufsize)
  734. size = min(rcv_len, req_len);
  735. else
  736. size = min(bufsize, req_len);
  737. /* update parameters */
  738. req->req.actual += size;
  739. /* check transfer finish */
  740. if ((!req->req.zero && (req->req.actual == req->req.length))
  741. || (size % ep->ep.maxpacket)
  742. || (size == 0)) {
  743. pipe_stop(m66592, pipenum);
  744. pipe_irq_disable(m66592, pipenum);
  745. finish = 1;
  746. }
  747. /* read fifo */
  748. if (req->req.buf) {
  749. if (size == 0)
  750. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  751. else
  752. m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
  753. }
  754. if ((ep->pipenum != 0) && finish)
  755. transfer_complete(ep, req, 0);
  756. }
  757. static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
  758. {
  759. u16 check;
  760. u16 pipenum;
  761. struct m66592_ep *ep;
  762. struct m66592_request *req;
  763. if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
  764. m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
  765. m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
  766. M66592_CFIFOSEL);
  767. ep = &m66592->ep[0];
  768. req = list_entry(ep->queue.next, struct m66592_request, queue);
  769. irq_packet_read(ep, req);
  770. } else {
  771. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  772. check = 1 << pipenum;
  773. if ((status & check) && (enb & check)) {
  774. m66592_write(m66592, ~check, M66592_BRDYSTS);
  775. ep = m66592->pipenum2ep[pipenum];
  776. req = list_entry(ep->queue.next,
  777. struct m66592_request, queue);
  778. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  779. irq_packet_write(ep, req);
  780. else
  781. irq_packet_read(ep, req);
  782. }
  783. }
  784. }
  785. }
  786. static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
  787. {
  788. u16 tmp;
  789. u16 check;
  790. u16 pipenum;
  791. struct m66592_ep *ep;
  792. struct m66592_request *req;
  793. if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
  794. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  795. ep = &m66592->ep[0];
  796. req = list_entry(ep->queue.next, struct m66592_request, queue);
  797. irq_ep0_write(ep, req);
  798. } else {
  799. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  800. check = 1 << pipenum;
  801. if ((status & check) && (enb & check)) {
  802. m66592_write(m66592, ~check, M66592_BEMPSTS);
  803. tmp = control_reg_get(m66592, pipenum);
  804. if ((tmp & M66592_INBUFM) == 0) {
  805. disable_irq_empty(m66592, pipenum);
  806. pipe_irq_disable(m66592, pipenum);
  807. pipe_stop(m66592, pipenum);
  808. ep = m66592->pipenum2ep[pipenum];
  809. req = list_entry(ep->queue.next,
  810. struct m66592_request,
  811. queue);
  812. if (!list_empty(&ep->queue))
  813. transfer_complete(ep, req, 0);
  814. }
  815. }
  816. }
  817. }
  818. }
  819. static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  820. __releases(m66592->lock)
  821. __acquires(m66592->lock)
  822. {
  823. struct m66592_ep *ep;
  824. u16 pid;
  825. u16 status = 0;
  826. u16 w_index = le16_to_cpu(ctrl->wIndex);
  827. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  828. case USB_RECIP_DEVICE:
  829. status = 1 << USB_DEVICE_SELF_POWERED;
  830. break;
  831. case USB_RECIP_INTERFACE:
  832. status = 0;
  833. break;
  834. case USB_RECIP_ENDPOINT:
  835. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  836. pid = control_reg_get_pid(m66592, ep->pipenum);
  837. if (pid == M66592_PID_STALL)
  838. status = 1 << USB_ENDPOINT_HALT;
  839. else
  840. status = 0;
  841. break;
  842. default:
  843. pipe_stall(m66592, 0);
  844. return; /* exit */
  845. }
  846. m66592->ep0_data = cpu_to_le16(status);
  847. m66592->ep0_req->buf = &m66592->ep0_data;
  848. m66592->ep0_req->length = 2;
  849. /* AV: what happens if we get called again before that gets through? */
  850. spin_unlock(&m66592->lock);
  851. m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
  852. spin_lock(&m66592->lock);
  853. }
  854. static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  855. {
  856. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  857. case USB_RECIP_DEVICE:
  858. control_end(m66592, 1);
  859. break;
  860. case USB_RECIP_INTERFACE:
  861. control_end(m66592, 1);
  862. break;
  863. case USB_RECIP_ENDPOINT: {
  864. struct m66592_ep *ep;
  865. struct m66592_request *req;
  866. u16 w_index = le16_to_cpu(ctrl->wIndex);
  867. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  868. pipe_stop(m66592, ep->pipenum);
  869. control_reg_sqclr(m66592, ep->pipenum);
  870. control_end(m66592, 1);
  871. req = list_entry(ep->queue.next,
  872. struct m66592_request, queue);
  873. if (ep->busy) {
  874. ep->busy = 0;
  875. if (list_empty(&ep->queue))
  876. break;
  877. start_packet(ep, req);
  878. } else if (!list_empty(&ep->queue))
  879. pipe_start(m66592, ep->pipenum);
  880. }
  881. break;
  882. default:
  883. pipe_stall(m66592, 0);
  884. break;
  885. }
  886. }
  887. static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  888. {
  889. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  890. case USB_RECIP_DEVICE:
  891. control_end(m66592, 1);
  892. break;
  893. case USB_RECIP_INTERFACE:
  894. control_end(m66592, 1);
  895. break;
  896. case USB_RECIP_ENDPOINT: {
  897. struct m66592_ep *ep;
  898. u16 w_index = le16_to_cpu(ctrl->wIndex);
  899. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  900. pipe_stall(m66592, ep->pipenum);
  901. control_end(m66592, 1);
  902. }
  903. break;
  904. default:
  905. pipe_stall(m66592, 0);
  906. break;
  907. }
  908. }
  909. /* if return value is true, call class driver's setup() */
  910. static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  911. {
  912. u16 *p = (u16 *)ctrl;
  913. unsigned long offset = M66592_USBREQ;
  914. int i, ret = 0;
  915. /* read fifo */
  916. m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
  917. for (i = 0; i < 4; i++)
  918. p[i] = m66592_read(m66592, offset + i*2);
  919. /* check request */
  920. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  921. switch (ctrl->bRequest) {
  922. case USB_REQ_GET_STATUS:
  923. get_status(m66592, ctrl);
  924. break;
  925. case USB_REQ_CLEAR_FEATURE:
  926. clear_feature(m66592, ctrl);
  927. break;
  928. case USB_REQ_SET_FEATURE:
  929. set_feature(m66592, ctrl);
  930. break;
  931. default:
  932. ret = 1;
  933. break;
  934. }
  935. } else
  936. ret = 1;
  937. return ret;
  938. }
  939. static void m66592_update_usb_speed(struct m66592 *m66592)
  940. {
  941. u16 speed = get_usb_speed(m66592);
  942. switch (speed) {
  943. case M66592_HSMODE:
  944. m66592->gadget.speed = USB_SPEED_HIGH;
  945. break;
  946. case M66592_FSMODE:
  947. m66592->gadget.speed = USB_SPEED_FULL;
  948. break;
  949. default:
  950. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  951. printk(KERN_ERR "USB speed unknown\n");
  952. }
  953. }
  954. static void irq_device_state(struct m66592 *m66592)
  955. {
  956. u16 dvsq;
  957. dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
  958. m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
  959. if (dvsq == M66592_DS_DFLT) { /* bus reset */
  960. m66592->driver->disconnect(&m66592->gadget);
  961. m66592_update_usb_speed(m66592);
  962. }
  963. if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
  964. m66592_update_usb_speed(m66592);
  965. if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
  966. && m66592->gadget.speed == USB_SPEED_UNKNOWN)
  967. m66592_update_usb_speed(m66592);
  968. m66592->old_dvsq = dvsq;
  969. }
  970. static void irq_control_stage(struct m66592 *m66592)
  971. __releases(m66592->lock)
  972. __acquires(m66592->lock)
  973. {
  974. struct usb_ctrlrequest ctrl;
  975. u16 ctsq;
  976. ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
  977. m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
  978. switch (ctsq) {
  979. case M66592_CS_IDST: {
  980. struct m66592_ep *ep;
  981. struct m66592_request *req;
  982. ep = &m66592->ep[0];
  983. req = list_entry(ep->queue.next, struct m66592_request, queue);
  984. transfer_complete(ep, req, 0);
  985. }
  986. break;
  987. case M66592_CS_RDDS:
  988. case M66592_CS_WRDS:
  989. case M66592_CS_WRND:
  990. if (setup_packet(m66592, &ctrl)) {
  991. spin_unlock(&m66592->lock);
  992. if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
  993. pipe_stall(m66592, 0);
  994. spin_lock(&m66592->lock);
  995. }
  996. break;
  997. case M66592_CS_RDSS:
  998. case M66592_CS_WRSS:
  999. control_end(m66592, 0);
  1000. break;
  1001. default:
  1002. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  1003. break;
  1004. }
  1005. }
  1006. static irqreturn_t m66592_irq(int irq, void *_m66592)
  1007. {
  1008. struct m66592 *m66592 = _m66592;
  1009. u16 intsts0;
  1010. u16 intenb0;
  1011. u16 brdysts, nrdysts, bempsts;
  1012. u16 brdyenb, nrdyenb, bempenb;
  1013. u16 savepipe;
  1014. u16 mask0;
  1015. spin_lock(&m66592->lock);
  1016. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1017. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1018. #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
  1019. if (!intsts0 && !intenb0) {
  1020. /*
  1021. * When USB clock stops, it cannot read register. Even if a
  1022. * clock stops, the interrupt occurs. So this driver turn on
  1023. * a clock by this timing and do re-reading of register.
  1024. */
  1025. m66592_start_xclock(m66592);
  1026. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1027. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1028. }
  1029. #endif
  1030. savepipe = m66592_read(m66592, M66592_CFIFOSEL);
  1031. mask0 = intsts0 & intenb0;
  1032. if (mask0) {
  1033. brdysts = m66592_read(m66592, M66592_BRDYSTS);
  1034. nrdysts = m66592_read(m66592, M66592_NRDYSTS);
  1035. bempsts = m66592_read(m66592, M66592_BEMPSTS);
  1036. brdyenb = m66592_read(m66592, M66592_BRDYENB);
  1037. nrdyenb = m66592_read(m66592, M66592_NRDYENB);
  1038. bempenb = m66592_read(m66592, M66592_BEMPENB);
  1039. if (mask0 & M66592_VBINT) {
  1040. m66592_write(m66592, 0xffff & ~M66592_VBINT,
  1041. M66592_INTSTS0);
  1042. m66592_start_xclock(m66592);
  1043. /* start vbus sampling */
  1044. m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
  1045. & M66592_VBSTS;
  1046. m66592->scount = M66592_MAX_SAMPLING;
  1047. mod_timer(&m66592->timer,
  1048. jiffies + msecs_to_jiffies(50));
  1049. }
  1050. if (intsts0 & M66592_DVSQ)
  1051. irq_device_state(m66592);
  1052. if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
  1053. && (brdysts & brdyenb)) {
  1054. irq_pipe_ready(m66592, brdysts, brdyenb);
  1055. }
  1056. if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
  1057. && (bempsts & bempenb)) {
  1058. irq_pipe_empty(m66592, bempsts, bempenb);
  1059. }
  1060. if (intsts0 & M66592_CTRT)
  1061. irq_control_stage(m66592);
  1062. }
  1063. m66592_write(m66592, savepipe, M66592_CFIFOSEL);
  1064. spin_unlock(&m66592->lock);
  1065. return IRQ_HANDLED;
  1066. }
  1067. static void m66592_timer(unsigned long _m66592)
  1068. {
  1069. struct m66592 *m66592 = (struct m66592 *)_m66592;
  1070. unsigned long flags;
  1071. u16 tmp;
  1072. spin_lock_irqsave(&m66592->lock, flags);
  1073. tmp = m66592_read(m66592, M66592_SYSCFG);
  1074. if (!(tmp & M66592_RCKE)) {
  1075. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  1076. udelay(10);
  1077. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  1078. }
  1079. if (m66592->scount > 0) {
  1080. tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
  1081. if (tmp == m66592->old_vbus) {
  1082. m66592->scount--;
  1083. if (m66592->scount == 0) {
  1084. if (tmp == M66592_VBSTS)
  1085. m66592_usb_connect(m66592);
  1086. else
  1087. m66592_usb_disconnect(m66592);
  1088. } else {
  1089. mod_timer(&m66592->timer,
  1090. jiffies + msecs_to_jiffies(50));
  1091. }
  1092. } else {
  1093. m66592->scount = M66592_MAX_SAMPLING;
  1094. m66592->old_vbus = tmp;
  1095. mod_timer(&m66592->timer,
  1096. jiffies + msecs_to_jiffies(50));
  1097. }
  1098. }
  1099. spin_unlock_irqrestore(&m66592->lock, flags);
  1100. }
  1101. /*-------------------------------------------------------------------------*/
  1102. static int m66592_enable(struct usb_ep *_ep,
  1103. const struct usb_endpoint_descriptor *desc)
  1104. {
  1105. struct m66592_ep *ep;
  1106. ep = container_of(_ep, struct m66592_ep, ep);
  1107. return alloc_pipe_config(ep, desc);
  1108. }
  1109. static int m66592_disable(struct usb_ep *_ep)
  1110. {
  1111. struct m66592_ep *ep;
  1112. struct m66592_request *req;
  1113. unsigned long flags;
  1114. ep = container_of(_ep, struct m66592_ep, ep);
  1115. BUG_ON(!ep);
  1116. while (!list_empty(&ep->queue)) {
  1117. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1118. spin_lock_irqsave(&ep->m66592->lock, flags);
  1119. transfer_complete(ep, req, -ECONNRESET);
  1120. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1121. }
  1122. pipe_irq_disable(ep->m66592, ep->pipenum);
  1123. return free_pipe_config(ep);
  1124. }
  1125. static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
  1126. gfp_t gfp_flags)
  1127. {
  1128. struct m66592_request *req;
  1129. req = kzalloc(sizeof(struct m66592_request), gfp_flags);
  1130. if (!req)
  1131. return NULL;
  1132. INIT_LIST_HEAD(&req->queue);
  1133. return &req->req;
  1134. }
  1135. static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1136. {
  1137. struct m66592_request *req;
  1138. req = container_of(_req, struct m66592_request, req);
  1139. kfree(req);
  1140. }
  1141. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  1142. gfp_t gfp_flags)
  1143. {
  1144. struct m66592_ep *ep;
  1145. struct m66592_request *req;
  1146. unsigned long flags;
  1147. int request = 0;
  1148. ep = container_of(_ep, struct m66592_ep, ep);
  1149. req = container_of(_req, struct m66592_request, req);
  1150. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  1151. return -ESHUTDOWN;
  1152. spin_lock_irqsave(&ep->m66592->lock, flags);
  1153. if (list_empty(&ep->queue))
  1154. request = 1;
  1155. list_add_tail(&req->queue, &ep->queue);
  1156. req->req.actual = 0;
  1157. req->req.status = -EINPROGRESS;
  1158. if (ep->desc == NULL) /* control */
  1159. start_ep0(ep, req);
  1160. else {
  1161. if (request && !ep->busy)
  1162. start_packet(ep, req);
  1163. }
  1164. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1165. return 0;
  1166. }
  1167. static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1168. {
  1169. struct m66592_ep *ep;
  1170. struct m66592_request *req;
  1171. unsigned long flags;
  1172. ep = container_of(_ep, struct m66592_ep, ep);
  1173. req = container_of(_req, struct m66592_request, req);
  1174. spin_lock_irqsave(&ep->m66592->lock, flags);
  1175. if (!list_empty(&ep->queue))
  1176. transfer_complete(ep, req, -ECONNRESET);
  1177. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1178. return 0;
  1179. }
  1180. static int m66592_set_halt(struct usb_ep *_ep, int value)
  1181. {
  1182. struct m66592_ep *ep;
  1183. struct m66592_request *req;
  1184. unsigned long flags;
  1185. int ret = 0;
  1186. ep = container_of(_ep, struct m66592_ep, ep);
  1187. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1188. spin_lock_irqsave(&ep->m66592->lock, flags);
  1189. if (!list_empty(&ep->queue)) {
  1190. ret = -EAGAIN;
  1191. goto out;
  1192. }
  1193. if (value) {
  1194. ep->busy = 1;
  1195. pipe_stall(ep->m66592, ep->pipenum);
  1196. } else {
  1197. ep->busy = 0;
  1198. pipe_stop(ep->m66592, ep->pipenum);
  1199. }
  1200. out:
  1201. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1202. return ret;
  1203. }
  1204. static void m66592_fifo_flush(struct usb_ep *_ep)
  1205. {
  1206. struct m66592_ep *ep;
  1207. unsigned long flags;
  1208. ep = container_of(_ep, struct m66592_ep, ep);
  1209. spin_lock_irqsave(&ep->m66592->lock, flags);
  1210. if (list_empty(&ep->queue) && !ep->busy) {
  1211. pipe_stop(ep->m66592, ep->pipenum);
  1212. m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
  1213. }
  1214. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1215. }
  1216. static struct usb_ep_ops m66592_ep_ops = {
  1217. .enable = m66592_enable,
  1218. .disable = m66592_disable,
  1219. .alloc_request = m66592_alloc_request,
  1220. .free_request = m66592_free_request,
  1221. .queue = m66592_queue,
  1222. .dequeue = m66592_dequeue,
  1223. .set_halt = m66592_set_halt,
  1224. .fifo_flush = m66592_fifo_flush,
  1225. };
  1226. /*-------------------------------------------------------------------------*/
  1227. static struct m66592 *the_controller;
  1228. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1229. {
  1230. struct m66592 *m66592 = the_controller;
  1231. int retval;
  1232. if (!driver
  1233. || driver->speed != USB_SPEED_HIGH
  1234. || !driver->bind
  1235. || !driver->setup)
  1236. return -EINVAL;
  1237. if (!m66592)
  1238. return -ENODEV;
  1239. if (m66592->driver)
  1240. return -EBUSY;
  1241. /* hook up the driver */
  1242. driver->driver.bus = NULL;
  1243. m66592->driver = driver;
  1244. m66592->gadget.dev.driver = &driver->driver;
  1245. retval = device_add(&m66592->gadget.dev);
  1246. if (retval) {
  1247. printk(KERN_ERR "device_add error (%d)\n", retval);
  1248. goto error;
  1249. }
  1250. retval = driver->bind (&m66592->gadget);
  1251. if (retval) {
  1252. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1253. device_del(&m66592->gadget.dev);
  1254. goto error;
  1255. }
  1256. m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1257. if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
  1258. m66592_start_xclock(m66592);
  1259. /* start vbus sampling */
  1260. m66592->old_vbus = m66592_read(m66592,
  1261. M66592_INTSTS0) & M66592_VBSTS;
  1262. m66592->scount = M66592_MAX_SAMPLING;
  1263. mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
  1264. }
  1265. return 0;
  1266. error:
  1267. m66592->driver = NULL;
  1268. m66592->gadget.dev.driver = NULL;
  1269. return retval;
  1270. }
  1271. EXPORT_SYMBOL(usb_gadget_register_driver);
  1272. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1273. {
  1274. struct m66592 *m66592 = the_controller;
  1275. unsigned long flags;
  1276. if (driver != m66592->driver || !driver->unbind)
  1277. return -EINVAL;
  1278. spin_lock_irqsave(&m66592->lock, flags);
  1279. if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
  1280. m66592_usb_disconnect(m66592);
  1281. spin_unlock_irqrestore(&m66592->lock, flags);
  1282. m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1283. driver->unbind(&m66592->gadget);
  1284. init_controller(m66592);
  1285. disable_controller(m66592);
  1286. device_del(&m66592->gadget.dev);
  1287. m66592->driver = NULL;
  1288. return 0;
  1289. }
  1290. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1291. /*-------------------------------------------------------------------------*/
  1292. static int m66592_get_frame(struct usb_gadget *_gadget)
  1293. {
  1294. struct m66592 *m66592 = gadget_to_m66592(_gadget);
  1295. return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
  1296. }
  1297. static struct usb_gadget_ops m66592_gadget_ops = {
  1298. .get_frame = m66592_get_frame,
  1299. };
  1300. static int __exit m66592_remove(struct platform_device *pdev)
  1301. {
  1302. struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
  1303. del_timer_sync(&m66592->timer);
  1304. iounmap(m66592->reg);
  1305. free_irq(platform_get_irq(pdev, 0), m66592);
  1306. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1307. usbf_stop_clock();
  1308. kfree(m66592);
  1309. return 0;
  1310. }
  1311. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1312. {
  1313. }
  1314. #define resource_len(r) (((r)->end - (r)->start) + 1)
  1315. static int __init m66592_probe(struct platform_device *pdev)
  1316. {
  1317. struct resource *res;
  1318. int irq;
  1319. void __iomem *reg = NULL;
  1320. struct m66592 *m66592 = NULL;
  1321. int ret = 0;
  1322. int i;
  1323. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1324. (char *)udc_name);
  1325. if (!res) {
  1326. ret = -ENODEV;
  1327. printk(KERN_ERR "platform_get_resource_byname error.\n");
  1328. goto clean_up;
  1329. }
  1330. irq = platform_get_irq(pdev, 0);
  1331. if (irq < 0) {
  1332. ret = -ENODEV;
  1333. printk(KERN_ERR "platform_get_irq error.\n");
  1334. goto clean_up;
  1335. }
  1336. reg = ioremap(res->start, resource_len(res));
  1337. if (reg == NULL) {
  1338. ret = -ENOMEM;
  1339. printk(KERN_ERR "ioremap error.\n");
  1340. goto clean_up;
  1341. }
  1342. /* initialize ucd */
  1343. m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
  1344. if (m66592 == NULL) {
  1345. printk(KERN_ERR "kzalloc error\n");
  1346. goto clean_up;
  1347. }
  1348. spin_lock_init(&m66592->lock);
  1349. dev_set_drvdata(&pdev->dev, m66592);
  1350. m66592->gadget.ops = &m66592_gadget_ops;
  1351. device_initialize(&m66592->gadget.dev);
  1352. strcpy(m66592->gadget.dev.bus_id, "gadget");
  1353. m66592->gadget.is_dualspeed = 1;
  1354. m66592->gadget.dev.parent = &pdev->dev;
  1355. m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1356. m66592->gadget.dev.release = pdev->dev.release;
  1357. m66592->gadget.name = udc_name;
  1358. init_timer(&m66592->timer);
  1359. m66592->timer.function = m66592_timer;
  1360. m66592->timer.data = (unsigned long)m66592;
  1361. m66592->reg = reg;
  1362. m66592->bi_bufnum = M66592_BASE_BUFNUM;
  1363. ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
  1364. udc_name, m66592);
  1365. if (ret < 0) {
  1366. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1367. goto clean_up;
  1368. }
  1369. INIT_LIST_HEAD(&m66592->gadget.ep_list);
  1370. m66592->gadget.ep0 = &m66592->ep[0].ep;
  1371. INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
  1372. for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
  1373. struct m66592_ep *ep = &m66592->ep[i];
  1374. if (i != 0) {
  1375. INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
  1376. list_add_tail(&m66592->ep[i].ep.ep_list,
  1377. &m66592->gadget.ep_list);
  1378. }
  1379. ep->m66592 = m66592;
  1380. INIT_LIST_HEAD(&ep->queue);
  1381. ep->ep.name = m66592_ep_name[i];
  1382. ep->ep.ops = &m66592_ep_ops;
  1383. ep->ep.maxpacket = 512;
  1384. }
  1385. m66592->ep[0].ep.maxpacket = 64;
  1386. m66592->ep[0].pipenum = 0;
  1387. m66592->ep[0].fifoaddr = M66592_CFIFO;
  1388. m66592->ep[0].fifosel = M66592_CFIFOSEL;
  1389. m66592->ep[0].fifoctr = M66592_CFIFOCTR;
  1390. m66592->ep[0].fifotrn = 0;
  1391. m66592->ep[0].pipectr = get_pipectr_addr(0);
  1392. m66592->pipenum2ep[0] = &m66592->ep[0];
  1393. m66592->epaddr2ep[0] = &m66592->ep[0];
  1394. the_controller = m66592;
  1395. m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
  1396. if (m66592->ep0_req == NULL)
  1397. goto clean_up2;
  1398. m66592->ep0_req->complete = nop_completion;
  1399. init_controller(m66592);
  1400. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1401. return 0;
  1402. clean_up2:
  1403. free_irq(irq, m66592);
  1404. clean_up:
  1405. if (m66592) {
  1406. if (m66592->ep0_req)
  1407. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1408. kfree(m66592);
  1409. }
  1410. if (reg)
  1411. iounmap(reg);
  1412. return ret;
  1413. }
  1414. /*-------------------------------------------------------------------------*/
  1415. static struct platform_driver m66592_driver = {
  1416. .remove = __exit_p(m66592_remove),
  1417. .driver = {
  1418. .name = (char *) udc_name,
  1419. },
  1420. };
  1421. static int __init m66592_udc_init(void)
  1422. {
  1423. return platform_driver_probe(&m66592_driver, m66592_probe);
  1424. }
  1425. module_init(m66592_udc_init);
  1426. static void __exit m66592_udc_cleanup(void)
  1427. {
  1428. platform_driver_unregister(&m66592_driver);
  1429. }
  1430. module_exit(m66592_udc_cleanup);