fsi.c 33 KB

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  1. /*
  2. * Fifo-attached Serial Interface (FSI) support for SH7724
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on ssi.c
  8. * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/io.h>
  17. #include <linux/slab.h>
  18. #include <linux/module.h>
  19. #include <sound/soc.h>
  20. #include <sound/sh_fsi.h>
  21. /* PortA/PortB register */
  22. #define REG_DO_FMT 0x0000
  23. #define REG_DOFF_CTL 0x0004
  24. #define REG_DOFF_ST 0x0008
  25. #define REG_DI_FMT 0x000C
  26. #define REG_DIFF_CTL 0x0010
  27. #define REG_DIFF_ST 0x0014
  28. #define REG_CKG1 0x0018
  29. #define REG_CKG2 0x001C
  30. #define REG_DIDT 0x0020
  31. #define REG_DODT 0x0024
  32. #define REG_MUTE_ST 0x0028
  33. #define REG_OUT_DMAC 0x002C
  34. #define REG_OUT_SEL 0x0030
  35. #define REG_IN_DMAC 0x0038
  36. /* master register */
  37. #define MST_CLK_RST 0x0210
  38. #define MST_SOFT_RST 0x0214
  39. #define MST_FIFO_SZ 0x0218
  40. /* core register (depend on FSI version) */
  41. #define A_MST_CTLR 0x0180
  42. #define B_MST_CTLR 0x01A0
  43. #define CPU_INT_ST 0x01F4
  44. #define CPU_IEMSK 0x01F8
  45. #define CPU_IMSK 0x01FC
  46. #define INT_ST 0x0200
  47. #define IEMSK 0x0204
  48. #define IMSK 0x0208
  49. /* DO_FMT */
  50. /* DI_FMT */
  51. #define CR_BWS_24 (0x0 << 20) /* FSI2 */
  52. #define CR_BWS_16 (0x1 << 20) /* FSI2 */
  53. #define CR_BWS_20 (0x2 << 20) /* FSI2 */
  54. #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
  55. #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
  56. #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
  57. #define CR_MONO (0x0 << 4)
  58. #define CR_MONO_D (0x1 << 4)
  59. #define CR_PCM (0x2 << 4)
  60. #define CR_I2S (0x3 << 4)
  61. #define CR_TDM (0x4 << 4)
  62. #define CR_TDM_D (0x5 << 4)
  63. /* DOFF_CTL */
  64. /* DIFF_CTL */
  65. #define IRQ_HALF 0x00100000
  66. #define FIFO_CLR 0x00000001
  67. /* DOFF_ST */
  68. #define ERR_OVER 0x00000010
  69. #define ERR_UNDER 0x00000001
  70. #define ST_ERR (ERR_OVER | ERR_UNDER)
  71. /* CKG1 */
  72. #define ACKMD_MASK 0x00007000
  73. #define BPFMD_MASK 0x00000700
  74. #define DIMD (1 << 4)
  75. #define DOMD (1 << 0)
  76. /* A/B MST_CTLR */
  77. #define BP (1 << 4) /* Fix the signal of Biphase output */
  78. #define SE (1 << 0) /* Fix the master clock */
  79. /* CLK_RST */
  80. #define CRB (1 << 4)
  81. #define CRA (1 << 0)
  82. /* IO SHIFT / MACRO */
  83. #define BI_SHIFT 12
  84. #define BO_SHIFT 8
  85. #define AI_SHIFT 4
  86. #define AO_SHIFT 0
  87. #define AB_IO(param, shift) (param << shift)
  88. /* SOFT_RST */
  89. #define PBSR (1 << 12) /* Port B Software Reset */
  90. #define PASR (1 << 8) /* Port A Software Reset */
  91. #define IR (1 << 4) /* Interrupt Reset */
  92. #define FSISR (1 << 0) /* Software Reset */
  93. /* OUT_SEL (FSI2) */
  94. #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
  95. /* 1: Biphase and serial */
  96. /* FIFO_SZ */
  97. #define FIFO_SZ_MASK 0x7
  98. #define FSI_RATES SNDRV_PCM_RATE_8000_96000
  99. #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
  100. typedef int (*set_rate_func)(struct device *dev, int rate, int enable);
  101. /*
  102. * FSI driver use below type name for variable
  103. *
  104. * xxx_num : number of data
  105. * xxx_pos : position of data
  106. * xxx_capa : capacity of data
  107. */
  108. /*
  109. * period/frame/sample image
  110. *
  111. * ex) PCM (2ch)
  112. *
  113. * period pos period pos
  114. * [n] [n + 1]
  115. * |<-------------------- period--------------------->|
  116. * ==|============================================ ... =|==
  117. * | |
  118. * ||<----- frame ----->|<------ frame ----->| ... |
  119. * |+--------------------+--------------------+- ... |
  120. * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
  121. * |+--------------------+--------------------+- ... |
  122. * ==|============================================ ... =|==
  123. */
  124. /*
  125. * FSI FIFO image
  126. *
  127. * | |
  128. * | |
  129. * | [ sample ] |
  130. * | [ sample ] |
  131. * | [ sample ] |
  132. * | [ sample ] |
  133. * --> go to codecs
  134. */
  135. /*
  136. * struct
  137. */
  138. struct fsi_stream_handler;
  139. struct fsi_stream {
  140. /*
  141. * these are initialized by fsi_stream_init()
  142. */
  143. struct snd_pcm_substream *substream;
  144. int fifo_sample_capa; /* sample capacity of FSI FIFO */
  145. int buff_sample_capa; /* sample capacity of ALSA buffer */
  146. int buff_sample_pos; /* sample position of ALSA buffer */
  147. int period_samples; /* sample number / 1 period */
  148. int period_pos; /* current period position */
  149. int sample_width; /* sample width */
  150. int uerr_num;
  151. int oerr_num;
  152. /*
  153. * thse are initialized by fsi_handler_init()
  154. */
  155. struct fsi_stream_handler *handler;
  156. struct fsi_priv *priv;
  157. };
  158. struct fsi_priv {
  159. void __iomem *base;
  160. struct fsi_master *master;
  161. struct sh_fsi_port_info *info;
  162. struct fsi_stream playback;
  163. struct fsi_stream capture;
  164. u32 do_fmt;
  165. u32 di_fmt;
  166. int chan_num:16;
  167. int clk_master:1;
  168. int spdif:1;
  169. long rate;
  170. };
  171. struct fsi_stream_handler {
  172. int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io);
  173. int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
  174. int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
  175. void (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
  176. int enable);
  177. };
  178. #define fsi_stream_handler_call(io, func, args...) \
  179. (!(io) ? -ENODEV : \
  180. !((io)->handler->func) ? 0 : \
  181. (io)->handler->func(args))
  182. struct fsi_core {
  183. int ver;
  184. u32 int_st;
  185. u32 iemsk;
  186. u32 imsk;
  187. u32 a_mclk;
  188. u32 b_mclk;
  189. };
  190. struct fsi_master {
  191. void __iomem *base;
  192. int irq;
  193. struct fsi_priv fsia;
  194. struct fsi_priv fsib;
  195. struct fsi_core *core;
  196. spinlock_t lock;
  197. };
  198. static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
  199. /*
  200. * basic read write function
  201. */
  202. static void __fsi_reg_write(u32 __iomem *reg, u32 data)
  203. {
  204. /* valid data area is 24bit */
  205. data &= 0x00ffffff;
  206. __raw_writel(data, reg);
  207. }
  208. static u32 __fsi_reg_read(u32 __iomem *reg)
  209. {
  210. return __raw_readl(reg);
  211. }
  212. static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
  213. {
  214. u32 val = __fsi_reg_read(reg);
  215. val &= ~mask;
  216. val |= data & mask;
  217. __fsi_reg_write(reg, val);
  218. }
  219. #define fsi_reg_write(p, r, d)\
  220. __fsi_reg_write((p->base + REG_##r), d)
  221. #define fsi_reg_read(p, r)\
  222. __fsi_reg_read((p->base + REG_##r))
  223. #define fsi_reg_mask_set(p, r, m, d)\
  224. __fsi_reg_mask_set((p->base + REG_##r), m, d)
  225. #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
  226. #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
  227. static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
  228. {
  229. u32 ret;
  230. unsigned long flags;
  231. spin_lock_irqsave(&master->lock, flags);
  232. ret = __fsi_reg_read(master->base + reg);
  233. spin_unlock_irqrestore(&master->lock, flags);
  234. return ret;
  235. }
  236. #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
  237. #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
  238. static void _fsi_master_mask_set(struct fsi_master *master,
  239. u32 reg, u32 mask, u32 data)
  240. {
  241. unsigned long flags;
  242. spin_lock_irqsave(&master->lock, flags);
  243. __fsi_reg_mask_set(master->base + reg, mask, data);
  244. spin_unlock_irqrestore(&master->lock, flags);
  245. }
  246. /*
  247. * basic function
  248. */
  249. static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
  250. {
  251. return fsi->master;
  252. }
  253. static int fsi_is_clk_master(struct fsi_priv *fsi)
  254. {
  255. return fsi->clk_master;
  256. }
  257. static int fsi_is_port_a(struct fsi_priv *fsi)
  258. {
  259. return fsi->master->base == fsi->base;
  260. }
  261. static int fsi_is_spdif(struct fsi_priv *fsi)
  262. {
  263. return fsi->spdif;
  264. }
  265. static int fsi_is_play(struct snd_pcm_substream *substream)
  266. {
  267. return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  268. }
  269. static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
  270. {
  271. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  272. return rtd->cpu_dai;
  273. }
  274. static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
  275. {
  276. struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
  277. if (dai->id == 0)
  278. return &master->fsia;
  279. else
  280. return &master->fsib;
  281. }
  282. static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
  283. {
  284. return fsi_get_priv_frm_dai(fsi_get_dai(substream));
  285. }
  286. static set_rate_func fsi_get_info_set_rate(struct fsi_priv *fsi)
  287. {
  288. if (!fsi->info)
  289. return NULL;
  290. return fsi->info->set_rate;
  291. }
  292. static u32 fsi_get_info_flags(struct fsi_priv *fsi)
  293. {
  294. if (!fsi->info)
  295. return 0;
  296. return fsi->info->flags;
  297. }
  298. static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
  299. {
  300. int is_play = fsi_stream_is_play(fsi, io);
  301. int is_porta = fsi_is_port_a(fsi);
  302. u32 shift;
  303. if (is_porta)
  304. shift = is_play ? AO_SHIFT : AI_SHIFT;
  305. else
  306. shift = is_play ? BO_SHIFT : BI_SHIFT;
  307. return shift;
  308. }
  309. static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
  310. {
  311. return frames * fsi->chan_num;
  312. }
  313. static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
  314. {
  315. return samples / fsi->chan_num;
  316. }
  317. static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
  318. struct fsi_stream *io)
  319. {
  320. int is_play = fsi_stream_is_play(fsi, io);
  321. u32 status;
  322. int frames;
  323. status = is_play ?
  324. fsi_reg_read(fsi, DOFF_ST) :
  325. fsi_reg_read(fsi, DIFF_ST);
  326. frames = 0x1ff & (status >> 8);
  327. return fsi_frame2sample(fsi, frames);
  328. }
  329. static void fsi_count_fifo_err(struct fsi_priv *fsi)
  330. {
  331. u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
  332. u32 istatus = fsi_reg_read(fsi, DIFF_ST);
  333. if (ostatus & ERR_OVER)
  334. fsi->playback.oerr_num++;
  335. if (ostatus & ERR_UNDER)
  336. fsi->playback.uerr_num++;
  337. if (istatus & ERR_OVER)
  338. fsi->capture.oerr_num++;
  339. if (istatus & ERR_UNDER)
  340. fsi->capture.uerr_num++;
  341. fsi_reg_write(fsi, DOFF_ST, 0);
  342. fsi_reg_write(fsi, DIFF_ST, 0);
  343. }
  344. /*
  345. * fsi_stream_xx() function
  346. */
  347. static inline int fsi_stream_is_play(struct fsi_priv *fsi,
  348. struct fsi_stream *io)
  349. {
  350. return &fsi->playback == io;
  351. }
  352. static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
  353. struct snd_pcm_substream *substream)
  354. {
  355. return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
  356. }
  357. static int fsi_stream_is_working(struct fsi_priv *fsi,
  358. struct fsi_stream *io)
  359. {
  360. struct fsi_master *master = fsi_get_master(fsi);
  361. unsigned long flags;
  362. int ret;
  363. spin_lock_irqsave(&master->lock, flags);
  364. ret = !!(io->substream && io->substream->runtime);
  365. spin_unlock_irqrestore(&master->lock, flags);
  366. return ret;
  367. }
  368. static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
  369. {
  370. return io->priv;
  371. }
  372. static void fsi_stream_init(struct fsi_priv *fsi,
  373. struct fsi_stream *io,
  374. struct snd_pcm_substream *substream)
  375. {
  376. struct snd_pcm_runtime *runtime = substream->runtime;
  377. struct fsi_master *master = fsi_get_master(fsi);
  378. unsigned long flags;
  379. spin_lock_irqsave(&master->lock, flags);
  380. io->substream = substream;
  381. io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
  382. io->buff_sample_pos = 0;
  383. io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
  384. io->period_pos = 0;
  385. io->sample_width = samples_to_bytes(runtime, 1);
  386. io->oerr_num = -1; /* ignore 1st err */
  387. io->uerr_num = -1; /* ignore 1st err */
  388. spin_unlock_irqrestore(&master->lock, flags);
  389. }
  390. static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
  391. {
  392. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  393. struct fsi_master *master = fsi_get_master(fsi);
  394. unsigned long flags;
  395. spin_lock_irqsave(&master->lock, flags);
  396. if (io->oerr_num > 0)
  397. dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
  398. if (io->uerr_num > 0)
  399. dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
  400. io->substream = NULL;
  401. io->buff_sample_capa = 0;
  402. io->buff_sample_pos = 0;
  403. io->period_samples = 0;
  404. io->period_pos = 0;
  405. io->sample_width = 0;
  406. io->oerr_num = 0;
  407. io->uerr_num = 0;
  408. spin_unlock_irqrestore(&master->lock, flags);
  409. }
  410. static int fsi_stream_transfer(struct fsi_stream *io)
  411. {
  412. struct fsi_priv *fsi = fsi_stream_to_priv(io);
  413. if (!fsi)
  414. return -EIO;
  415. return fsi_stream_handler_call(io, transfer, fsi, io);
  416. }
  417. #define fsi_stream_start(fsi, io)\
  418. fsi_stream_handler_call(io, start_stop, fsi, io, 1)
  419. #define fsi_stream_stop(fsi, io)\
  420. fsi_stream_handler_call(io, start_stop, fsi, io, 0)
  421. static int fsi_stream_probe(struct fsi_priv *fsi)
  422. {
  423. struct fsi_stream *io;
  424. int ret1, ret2;
  425. io = &fsi->playback;
  426. ret1 = fsi_stream_handler_call(io, probe, fsi, io);
  427. io = &fsi->capture;
  428. ret2 = fsi_stream_handler_call(io, probe, fsi, io);
  429. if (ret1 < 0)
  430. return ret1;
  431. if (ret2 < 0)
  432. return ret2;
  433. return 0;
  434. }
  435. static int fsi_stream_remove(struct fsi_priv *fsi)
  436. {
  437. struct fsi_stream *io;
  438. int ret1, ret2;
  439. io = &fsi->playback;
  440. ret1 = fsi_stream_handler_call(io, remove, fsi, io);
  441. io = &fsi->capture;
  442. ret2 = fsi_stream_handler_call(io, remove, fsi, io);
  443. if (ret1 < 0)
  444. return ret1;
  445. if (ret2 < 0)
  446. return ret2;
  447. return 0;
  448. }
  449. /*
  450. * irq function
  451. */
  452. static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
  453. {
  454. u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
  455. struct fsi_master *master = fsi_get_master(fsi);
  456. fsi_core_mask_set(master, imsk, data, data);
  457. fsi_core_mask_set(master, iemsk, data, data);
  458. }
  459. static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
  460. {
  461. u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
  462. struct fsi_master *master = fsi_get_master(fsi);
  463. fsi_core_mask_set(master, imsk, data, 0);
  464. fsi_core_mask_set(master, iemsk, data, 0);
  465. }
  466. static u32 fsi_irq_get_status(struct fsi_master *master)
  467. {
  468. return fsi_core_read(master, int_st);
  469. }
  470. static void fsi_irq_clear_status(struct fsi_priv *fsi)
  471. {
  472. u32 data = 0;
  473. struct fsi_master *master = fsi_get_master(fsi);
  474. data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
  475. data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
  476. /* clear interrupt factor */
  477. fsi_core_mask_set(master, int_st, data, 0);
  478. }
  479. /*
  480. * SPDIF master clock function
  481. *
  482. * These functions are used later FSI2
  483. */
  484. static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
  485. {
  486. struct fsi_master *master = fsi_get_master(fsi);
  487. u32 mask, val;
  488. if (master->core->ver < 2) {
  489. pr_err("fsi: register access err (%s)\n", __func__);
  490. return;
  491. }
  492. mask = BP | SE;
  493. val = enable ? mask : 0;
  494. fsi_is_port_a(fsi) ?
  495. fsi_core_mask_set(master, a_mclk, mask, val) :
  496. fsi_core_mask_set(master, b_mclk, mask, val);
  497. }
  498. /*
  499. * clock function
  500. */
  501. static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi,
  502. long rate, int enable)
  503. {
  504. struct fsi_master *master = fsi_get_master(fsi);
  505. set_rate_func set_rate = fsi_get_info_set_rate(fsi);
  506. int fsi_ver = master->core->ver;
  507. int ret;
  508. if (!set_rate)
  509. return 0;
  510. ret = set_rate(dev, rate, enable);
  511. if (ret < 0) /* error */
  512. return ret;
  513. if (!enable)
  514. return 0;
  515. if (ret > 0) {
  516. u32 data = 0;
  517. switch (ret & SH_FSI_ACKMD_MASK) {
  518. default:
  519. /* FALL THROUGH */
  520. case SH_FSI_ACKMD_512:
  521. data |= (0x0 << 12);
  522. break;
  523. case SH_FSI_ACKMD_256:
  524. data |= (0x1 << 12);
  525. break;
  526. case SH_FSI_ACKMD_128:
  527. data |= (0x2 << 12);
  528. break;
  529. case SH_FSI_ACKMD_64:
  530. data |= (0x3 << 12);
  531. break;
  532. case SH_FSI_ACKMD_32:
  533. if (fsi_ver < 2)
  534. dev_err(dev, "unsupported ACKMD\n");
  535. else
  536. data |= (0x4 << 12);
  537. break;
  538. }
  539. switch (ret & SH_FSI_BPFMD_MASK) {
  540. default:
  541. /* FALL THROUGH */
  542. case SH_FSI_BPFMD_32:
  543. data |= (0x0 << 8);
  544. break;
  545. case SH_FSI_BPFMD_64:
  546. data |= (0x1 << 8);
  547. break;
  548. case SH_FSI_BPFMD_128:
  549. data |= (0x2 << 8);
  550. break;
  551. case SH_FSI_BPFMD_256:
  552. data |= (0x3 << 8);
  553. break;
  554. case SH_FSI_BPFMD_512:
  555. data |= (0x4 << 8);
  556. break;
  557. case SH_FSI_BPFMD_16:
  558. if (fsi_ver < 2)
  559. dev_err(dev, "unsupported ACKMD\n");
  560. else
  561. data |= (0x7 << 8);
  562. break;
  563. }
  564. fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
  565. udelay(10);
  566. ret = 0;
  567. }
  568. return ret;
  569. }
  570. /*
  571. * pio data transfer handler
  572. */
  573. static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
  574. {
  575. u16 *buf = (u16 *)_buf;
  576. int i;
  577. for (i = 0; i < samples; i++)
  578. fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
  579. }
  580. static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
  581. {
  582. u16 *buf = (u16 *)_buf;
  583. int i;
  584. for (i = 0; i < samples; i++)
  585. *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
  586. }
  587. static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
  588. {
  589. u32 *buf = (u32 *)_buf;
  590. int i;
  591. for (i = 0; i < samples; i++)
  592. fsi_reg_write(fsi, DODT, *(buf + i));
  593. }
  594. static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
  595. {
  596. u32 *buf = (u32 *)_buf;
  597. int i;
  598. for (i = 0; i < samples; i++)
  599. *(buf + i) = fsi_reg_read(fsi, DIDT);
  600. }
  601. static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
  602. {
  603. struct snd_pcm_runtime *runtime = io->substream->runtime;
  604. return runtime->dma_area +
  605. samples_to_bytes(runtime, io->buff_sample_pos);
  606. }
  607. static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
  608. void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
  609. void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
  610. int samples)
  611. {
  612. struct snd_pcm_runtime *runtime;
  613. struct snd_pcm_substream *substream;
  614. u8 *buf;
  615. int over_period;
  616. if (!fsi_stream_is_working(fsi, io))
  617. return -EINVAL;
  618. over_period = 0;
  619. substream = io->substream;
  620. runtime = substream->runtime;
  621. /* FSI FIFO has limit.
  622. * So, this driver can not send periods data at a time
  623. */
  624. if (io->buff_sample_pos >=
  625. io->period_samples * (io->period_pos + 1)) {
  626. over_period = 1;
  627. io->period_pos = (io->period_pos + 1) % runtime->periods;
  628. if (0 == io->period_pos)
  629. io->buff_sample_pos = 0;
  630. }
  631. buf = fsi_pio_get_area(fsi, io);
  632. switch (io->sample_width) {
  633. case 2:
  634. run16(fsi, buf, samples);
  635. break;
  636. case 4:
  637. run32(fsi, buf, samples);
  638. break;
  639. default:
  640. return -EINVAL;
  641. }
  642. /* update buff_sample_pos */
  643. io->buff_sample_pos += samples;
  644. if (over_period)
  645. snd_pcm_period_elapsed(substream);
  646. return 0;
  647. }
  648. static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
  649. {
  650. int sample_residues; /* samples in FSI fifo */
  651. int sample_space; /* ALSA free samples space */
  652. int samples;
  653. sample_residues = fsi_get_current_fifo_samples(fsi, io);
  654. sample_space = io->buff_sample_capa - io->buff_sample_pos;
  655. samples = min(sample_residues, sample_space);
  656. return fsi_pio_transfer(fsi, io,
  657. fsi_pio_pop16,
  658. fsi_pio_pop32,
  659. samples);
  660. }
  661. static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
  662. {
  663. int sample_residues; /* ALSA residue samples */
  664. int sample_space; /* FSI fifo free samples space */
  665. int samples;
  666. sample_residues = io->buff_sample_capa - io->buff_sample_pos;
  667. sample_space = io->fifo_sample_capa -
  668. fsi_get_current_fifo_samples(fsi, io);
  669. samples = min(sample_residues, sample_space);
  670. return fsi_pio_transfer(fsi, io,
  671. fsi_pio_push16,
  672. fsi_pio_push32,
  673. samples);
  674. }
  675. static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
  676. int enable)
  677. {
  678. struct fsi_master *master = fsi_get_master(fsi);
  679. u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
  680. if (enable)
  681. fsi_irq_enable(fsi, io);
  682. else
  683. fsi_irq_disable(fsi, io);
  684. if (fsi_is_clk_master(fsi))
  685. fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
  686. }
  687. static struct fsi_stream_handler fsi_pio_push_handler = {
  688. .transfer = fsi_pio_push,
  689. .start_stop = fsi_pio_start_stop,
  690. };
  691. static struct fsi_stream_handler fsi_pio_pop_handler = {
  692. .transfer = fsi_pio_pop,
  693. .start_stop = fsi_pio_start_stop,
  694. };
  695. static irqreturn_t fsi_interrupt(int irq, void *data)
  696. {
  697. struct fsi_master *master = data;
  698. u32 int_st = fsi_irq_get_status(master);
  699. /* clear irq status */
  700. fsi_master_mask_set(master, SOFT_RST, IR, 0);
  701. fsi_master_mask_set(master, SOFT_RST, IR, IR);
  702. if (int_st & AB_IO(1, AO_SHIFT))
  703. fsi_stream_transfer(&master->fsia.playback);
  704. if (int_st & AB_IO(1, BO_SHIFT))
  705. fsi_stream_transfer(&master->fsib.playback);
  706. if (int_st & AB_IO(1, AI_SHIFT))
  707. fsi_stream_transfer(&master->fsia.capture);
  708. if (int_st & AB_IO(1, BI_SHIFT))
  709. fsi_stream_transfer(&master->fsib.capture);
  710. fsi_count_fifo_err(&master->fsia);
  711. fsi_count_fifo_err(&master->fsib);
  712. fsi_irq_clear_status(&master->fsia);
  713. fsi_irq_clear_status(&master->fsib);
  714. return IRQ_HANDLED;
  715. }
  716. /*
  717. * dai ops
  718. */
  719. static void fsi_fifo_init(struct fsi_priv *fsi,
  720. struct fsi_stream *io,
  721. struct device *dev)
  722. {
  723. struct fsi_master *master = fsi_get_master(fsi);
  724. int is_play = fsi_stream_is_play(fsi, io);
  725. u32 shift, i;
  726. int frame_capa;
  727. /* get on-chip RAM capacity */
  728. shift = fsi_master_read(master, FIFO_SZ);
  729. shift >>= fsi_get_port_shift(fsi, io);
  730. shift &= FIFO_SZ_MASK;
  731. frame_capa = 256 << shift;
  732. dev_dbg(dev, "fifo = %d words\n", frame_capa);
  733. /*
  734. * The maximum number of sample data varies depending
  735. * on the number of channels selected for the format.
  736. *
  737. * FIFOs are used in 4-channel units in 3-channel mode
  738. * and in 8-channel units in 5- to 7-channel mode
  739. * meaning that more FIFOs than the required size of DPRAM
  740. * are used.
  741. *
  742. * ex) if 256 words of DP-RAM is connected
  743. * 1 channel: 256 (256 x 1 = 256)
  744. * 2 channels: 128 (128 x 2 = 256)
  745. * 3 channels: 64 ( 64 x 3 = 192)
  746. * 4 channels: 64 ( 64 x 4 = 256)
  747. * 5 channels: 32 ( 32 x 5 = 160)
  748. * 6 channels: 32 ( 32 x 6 = 192)
  749. * 7 channels: 32 ( 32 x 7 = 224)
  750. * 8 channels: 32 ( 32 x 8 = 256)
  751. */
  752. for (i = 1; i < fsi->chan_num; i <<= 1)
  753. frame_capa >>= 1;
  754. dev_dbg(dev, "%d channel %d store\n",
  755. fsi->chan_num, frame_capa);
  756. io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
  757. /*
  758. * set interrupt generation factor
  759. * clear FIFO
  760. */
  761. if (is_play) {
  762. fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
  763. fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
  764. } else {
  765. fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
  766. fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
  767. }
  768. }
  769. static int fsi_hw_startup(struct fsi_priv *fsi,
  770. struct fsi_stream *io,
  771. struct device *dev)
  772. {
  773. struct fsi_master *master = fsi_get_master(fsi);
  774. int fsi_ver = master->core->ver;
  775. u32 flags = fsi_get_info_flags(fsi);
  776. u32 data = 0;
  777. /* clock setting */
  778. if (fsi_is_clk_master(fsi))
  779. data = DIMD | DOMD;
  780. fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
  781. /* clock inversion (CKG2) */
  782. data = 0;
  783. if (SH_FSI_LRM_INV & flags)
  784. data |= 1 << 12;
  785. if (SH_FSI_BRM_INV & flags)
  786. data |= 1 << 8;
  787. if (SH_FSI_LRS_INV & flags)
  788. data |= 1 << 4;
  789. if (SH_FSI_BRS_INV & flags)
  790. data |= 1 << 0;
  791. fsi_reg_write(fsi, CKG2, data);
  792. /* set format */
  793. fsi_reg_write(fsi, DO_FMT, fsi->do_fmt);
  794. fsi_reg_write(fsi, DI_FMT, fsi->di_fmt);
  795. /* spdif ? */
  796. if (fsi_is_spdif(fsi)) {
  797. fsi_spdif_clk_ctrl(fsi, 1);
  798. fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
  799. }
  800. /*
  801. * FIXME
  802. *
  803. * FSI driver assumed that data package is in-back.
  804. * FSI2 chip can select it.
  805. */
  806. if (fsi_ver >= 2) {
  807. fsi_reg_write(fsi, OUT_DMAC, (1 << 4));
  808. fsi_reg_write(fsi, IN_DMAC, (1 << 4));
  809. }
  810. /* irq clear */
  811. fsi_irq_disable(fsi, io);
  812. fsi_irq_clear_status(fsi);
  813. /* fifo init */
  814. fsi_fifo_init(fsi, io, dev);
  815. return 0;
  816. }
  817. static void fsi_hw_shutdown(struct fsi_priv *fsi,
  818. struct device *dev)
  819. {
  820. if (fsi_is_clk_master(fsi))
  821. fsi_set_master_clk(dev, fsi, fsi->rate, 0);
  822. }
  823. static int fsi_dai_startup(struct snd_pcm_substream *substream,
  824. struct snd_soc_dai *dai)
  825. {
  826. struct fsi_priv *fsi = fsi_get_priv(substream);
  827. return fsi_hw_startup(fsi, fsi_stream_get(fsi, substream), dai->dev);
  828. }
  829. static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
  830. struct snd_soc_dai *dai)
  831. {
  832. struct fsi_priv *fsi = fsi_get_priv(substream);
  833. fsi_hw_shutdown(fsi, dai->dev);
  834. fsi->rate = 0;
  835. }
  836. static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  837. struct snd_soc_dai *dai)
  838. {
  839. struct fsi_priv *fsi = fsi_get_priv(substream);
  840. struct fsi_stream *io = fsi_stream_get(fsi, substream);
  841. int ret = 0;
  842. switch (cmd) {
  843. case SNDRV_PCM_TRIGGER_START:
  844. fsi_stream_init(fsi, io, substream);
  845. ret = fsi_stream_transfer(io);
  846. if (0 == ret)
  847. fsi_stream_start(fsi, io);
  848. break;
  849. case SNDRV_PCM_TRIGGER_STOP:
  850. fsi_stream_stop(fsi, io);
  851. fsi_stream_quit(fsi, io);
  852. break;
  853. }
  854. return ret;
  855. }
  856. static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
  857. {
  858. u32 data = 0;
  859. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  860. case SND_SOC_DAIFMT_I2S:
  861. data = CR_I2S;
  862. fsi->chan_num = 2;
  863. break;
  864. case SND_SOC_DAIFMT_LEFT_J:
  865. data = CR_PCM;
  866. fsi->chan_num = 2;
  867. break;
  868. default:
  869. return -EINVAL;
  870. }
  871. fsi->do_fmt = data;
  872. fsi->di_fmt = data;
  873. return 0;
  874. }
  875. static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
  876. {
  877. struct fsi_master *master = fsi_get_master(fsi);
  878. u32 data = 0;
  879. if (master->core->ver < 2)
  880. return -EINVAL;
  881. data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
  882. fsi->chan_num = 2;
  883. fsi->spdif = 1;
  884. fsi->do_fmt = data;
  885. fsi->di_fmt = data;
  886. return 0;
  887. }
  888. static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  889. {
  890. struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
  891. set_rate_func set_rate = fsi_get_info_set_rate(fsi);
  892. u32 flags = fsi_get_info_flags(fsi);
  893. int ret;
  894. /* set master/slave audio interface */
  895. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  896. case SND_SOC_DAIFMT_CBM_CFM:
  897. fsi->clk_master = 1;
  898. break;
  899. case SND_SOC_DAIFMT_CBS_CFS:
  900. break;
  901. default:
  902. return -EINVAL;
  903. }
  904. if (fsi_is_clk_master(fsi) && !set_rate) {
  905. dev_err(dai->dev, "platform doesn't have set_rate\n");
  906. return -EINVAL;
  907. }
  908. /* set format */
  909. switch (flags & SH_FSI_FMT_MASK) {
  910. case SH_FSI_FMT_DAI:
  911. ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  912. break;
  913. case SH_FSI_FMT_SPDIF:
  914. ret = fsi_set_fmt_spdif(fsi);
  915. break;
  916. default:
  917. ret = -EINVAL;
  918. }
  919. return ret;
  920. }
  921. static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
  922. struct snd_pcm_hw_params *params,
  923. struct snd_soc_dai *dai)
  924. {
  925. struct fsi_priv *fsi = fsi_get_priv(substream);
  926. long rate = params_rate(params);
  927. int ret;
  928. if (!fsi_is_clk_master(fsi))
  929. return 0;
  930. ret = fsi_set_master_clk(dai->dev, fsi, rate, 1);
  931. if (ret < 0)
  932. return ret;
  933. fsi->rate = rate;
  934. return ret;
  935. }
  936. static const struct snd_soc_dai_ops fsi_dai_ops = {
  937. .startup = fsi_dai_startup,
  938. .shutdown = fsi_dai_shutdown,
  939. .trigger = fsi_dai_trigger,
  940. .set_fmt = fsi_dai_set_fmt,
  941. .hw_params = fsi_dai_hw_params,
  942. };
  943. /*
  944. * pcm ops
  945. */
  946. static struct snd_pcm_hardware fsi_pcm_hardware = {
  947. .info = SNDRV_PCM_INFO_INTERLEAVED |
  948. SNDRV_PCM_INFO_MMAP |
  949. SNDRV_PCM_INFO_MMAP_VALID |
  950. SNDRV_PCM_INFO_PAUSE,
  951. .formats = FSI_FMTS,
  952. .rates = FSI_RATES,
  953. .rate_min = 8000,
  954. .rate_max = 192000,
  955. .channels_min = 1,
  956. .channels_max = 2,
  957. .buffer_bytes_max = 64 * 1024,
  958. .period_bytes_min = 32,
  959. .period_bytes_max = 8192,
  960. .periods_min = 1,
  961. .periods_max = 32,
  962. .fifo_size = 256,
  963. };
  964. static int fsi_pcm_open(struct snd_pcm_substream *substream)
  965. {
  966. struct snd_pcm_runtime *runtime = substream->runtime;
  967. int ret = 0;
  968. snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
  969. ret = snd_pcm_hw_constraint_integer(runtime,
  970. SNDRV_PCM_HW_PARAM_PERIODS);
  971. return ret;
  972. }
  973. static int fsi_hw_params(struct snd_pcm_substream *substream,
  974. struct snd_pcm_hw_params *hw_params)
  975. {
  976. return snd_pcm_lib_malloc_pages(substream,
  977. params_buffer_bytes(hw_params));
  978. }
  979. static int fsi_hw_free(struct snd_pcm_substream *substream)
  980. {
  981. return snd_pcm_lib_free_pages(substream);
  982. }
  983. static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
  984. {
  985. struct fsi_priv *fsi = fsi_get_priv(substream);
  986. struct fsi_stream *io = fsi_stream_get(fsi, substream);
  987. int samples_pos = io->buff_sample_pos - 1;
  988. if (samples_pos < 0)
  989. samples_pos = 0;
  990. return fsi_sample2frame(fsi, samples_pos);
  991. }
  992. static struct snd_pcm_ops fsi_pcm_ops = {
  993. .open = fsi_pcm_open,
  994. .ioctl = snd_pcm_lib_ioctl,
  995. .hw_params = fsi_hw_params,
  996. .hw_free = fsi_hw_free,
  997. .pointer = fsi_pointer,
  998. };
  999. /*
  1000. * snd_soc_platform
  1001. */
  1002. #define PREALLOC_BUFFER (32 * 1024)
  1003. #define PREALLOC_BUFFER_MAX (32 * 1024)
  1004. static void fsi_pcm_free(struct snd_pcm *pcm)
  1005. {
  1006. snd_pcm_lib_preallocate_free_for_all(pcm);
  1007. }
  1008. static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
  1009. {
  1010. struct snd_pcm *pcm = rtd->pcm;
  1011. /*
  1012. * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
  1013. * in MMAP mode (i.e. aplay -M)
  1014. */
  1015. return snd_pcm_lib_preallocate_pages_for_all(
  1016. pcm,
  1017. SNDRV_DMA_TYPE_CONTINUOUS,
  1018. snd_dma_continuous_data(GFP_KERNEL),
  1019. PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
  1020. }
  1021. /*
  1022. * alsa struct
  1023. */
  1024. static struct snd_soc_dai_driver fsi_soc_dai[] = {
  1025. {
  1026. .name = "fsia-dai",
  1027. .playback = {
  1028. .rates = FSI_RATES,
  1029. .formats = FSI_FMTS,
  1030. .channels_min = 1,
  1031. .channels_max = 8,
  1032. },
  1033. .capture = {
  1034. .rates = FSI_RATES,
  1035. .formats = FSI_FMTS,
  1036. .channels_min = 1,
  1037. .channels_max = 8,
  1038. },
  1039. .ops = &fsi_dai_ops,
  1040. },
  1041. {
  1042. .name = "fsib-dai",
  1043. .playback = {
  1044. .rates = FSI_RATES,
  1045. .formats = FSI_FMTS,
  1046. .channels_min = 1,
  1047. .channels_max = 8,
  1048. },
  1049. .capture = {
  1050. .rates = FSI_RATES,
  1051. .formats = FSI_FMTS,
  1052. .channels_min = 1,
  1053. .channels_max = 8,
  1054. },
  1055. .ops = &fsi_dai_ops,
  1056. },
  1057. };
  1058. static struct snd_soc_platform_driver fsi_soc_platform = {
  1059. .ops = &fsi_pcm_ops,
  1060. .pcm_new = fsi_pcm_new,
  1061. .pcm_free = fsi_pcm_free,
  1062. };
  1063. /*
  1064. * platform function
  1065. */
  1066. static void fsi_handler_init(struct fsi_priv *fsi)
  1067. {
  1068. fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
  1069. fsi->playback.priv = fsi;
  1070. fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
  1071. fsi->capture.priv = fsi;
  1072. }
  1073. static int fsi_probe(struct platform_device *pdev)
  1074. {
  1075. struct fsi_master *master;
  1076. const struct platform_device_id *id_entry;
  1077. struct sh_fsi_platform_info *info = pdev->dev.platform_data;
  1078. struct resource *res;
  1079. unsigned int irq;
  1080. int ret;
  1081. id_entry = pdev->id_entry;
  1082. if (!id_entry) {
  1083. dev_err(&pdev->dev, "unknown fsi device\n");
  1084. return -ENODEV;
  1085. }
  1086. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1087. irq = platform_get_irq(pdev, 0);
  1088. if (!res || (int)irq <= 0) {
  1089. dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
  1090. ret = -ENODEV;
  1091. goto exit;
  1092. }
  1093. master = kzalloc(sizeof(*master), GFP_KERNEL);
  1094. if (!master) {
  1095. dev_err(&pdev->dev, "Could not allocate master\n");
  1096. ret = -ENOMEM;
  1097. goto exit;
  1098. }
  1099. master->base = ioremap_nocache(res->start, resource_size(res));
  1100. if (!master->base) {
  1101. ret = -ENXIO;
  1102. dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
  1103. goto exit_kfree;
  1104. }
  1105. /* master setting */
  1106. master->irq = irq;
  1107. master->core = (struct fsi_core *)id_entry->driver_data;
  1108. spin_lock_init(&master->lock);
  1109. /* FSI A setting */
  1110. master->fsia.base = master->base;
  1111. master->fsia.master = master;
  1112. master->fsia.info = &info->port_a;
  1113. fsi_handler_init(&master->fsia);
  1114. ret = fsi_stream_probe(&master->fsia);
  1115. if (ret < 0) {
  1116. dev_err(&pdev->dev, "FSIA stream probe failed\n");
  1117. goto exit_iounmap;
  1118. }
  1119. /* FSI B setting */
  1120. master->fsib.base = master->base + 0x40;
  1121. master->fsib.master = master;
  1122. master->fsib.info = &info->port_b;
  1123. fsi_handler_init(&master->fsib);
  1124. ret = fsi_stream_probe(&master->fsib);
  1125. if (ret < 0) {
  1126. dev_err(&pdev->dev, "FSIB stream probe failed\n");
  1127. goto exit_fsia;
  1128. }
  1129. pm_runtime_enable(&pdev->dev);
  1130. dev_set_drvdata(&pdev->dev, master);
  1131. ret = request_irq(irq, &fsi_interrupt, 0,
  1132. id_entry->name, master);
  1133. if (ret) {
  1134. dev_err(&pdev->dev, "irq request err\n");
  1135. goto exit_fsib;
  1136. }
  1137. ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
  1138. if (ret < 0) {
  1139. dev_err(&pdev->dev, "cannot snd soc register\n");
  1140. goto exit_free_irq;
  1141. }
  1142. ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
  1143. ARRAY_SIZE(fsi_soc_dai));
  1144. if (ret < 0) {
  1145. dev_err(&pdev->dev, "cannot snd dai register\n");
  1146. goto exit_snd_soc;
  1147. }
  1148. return ret;
  1149. exit_snd_soc:
  1150. snd_soc_unregister_platform(&pdev->dev);
  1151. exit_free_irq:
  1152. free_irq(irq, master);
  1153. exit_fsib:
  1154. fsi_stream_remove(&master->fsib);
  1155. exit_fsia:
  1156. fsi_stream_remove(&master->fsia);
  1157. exit_iounmap:
  1158. iounmap(master->base);
  1159. pm_runtime_disable(&pdev->dev);
  1160. exit_kfree:
  1161. kfree(master);
  1162. master = NULL;
  1163. exit:
  1164. return ret;
  1165. }
  1166. static int fsi_remove(struct platform_device *pdev)
  1167. {
  1168. struct fsi_master *master;
  1169. master = dev_get_drvdata(&pdev->dev);
  1170. free_irq(master->irq, master);
  1171. pm_runtime_disable(&pdev->dev);
  1172. snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
  1173. snd_soc_unregister_platform(&pdev->dev);
  1174. fsi_stream_remove(&master->fsia);
  1175. fsi_stream_remove(&master->fsib);
  1176. iounmap(master->base);
  1177. kfree(master);
  1178. return 0;
  1179. }
  1180. static void __fsi_suspend(struct fsi_priv *fsi,
  1181. struct fsi_stream *io,
  1182. struct device *dev)
  1183. {
  1184. if (!fsi_stream_is_working(fsi, io))
  1185. return;
  1186. fsi_stream_stop(fsi, io);
  1187. fsi_hw_shutdown(fsi, dev);
  1188. }
  1189. static void __fsi_resume(struct fsi_priv *fsi,
  1190. struct fsi_stream *io,
  1191. struct device *dev)
  1192. {
  1193. if (!fsi_stream_is_working(fsi, io))
  1194. return;
  1195. fsi_hw_startup(fsi, io, dev);
  1196. if (fsi_is_clk_master(fsi) && fsi->rate)
  1197. fsi_set_master_clk(dev, fsi, fsi->rate, 1);
  1198. fsi_stream_start(fsi, io);
  1199. }
  1200. static int fsi_suspend(struct device *dev)
  1201. {
  1202. struct fsi_master *master = dev_get_drvdata(dev);
  1203. struct fsi_priv *fsia = &master->fsia;
  1204. struct fsi_priv *fsib = &master->fsib;
  1205. __fsi_suspend(fsia, &fsia->playback, dev);
  1206. __fsi_suspend(fsia, &fsia->capture, dev);
  1207. __fsi_suspend(fsib, &fsib->playback, dev);
  1208. __fsi_suspend(fsib, &fsib->capture, dev);
  1209. return 0;
  1210. }
  1211. static int fsi_resume(struct device *dev)
  1212. {
  1213. struct fsi_master *master = dev_get_drvdata(dev);
  1214. struct fsi_priv *fsia = &master->fsia;
  1215. struct fsi_priv *fsib = &master->fsib;
  1216. __fsi_resume(fsia, &fsia->playback, dev);
  1217. __fsi_resume(fsia, &fsia->capture, dev);
  1218. __fsi_resume(fsib, &fsib->playback, dev);
  1219. __fsi_resume(fsib, &fsib->capture, dev);
  1220. return 0;
  1221. }
  1222. static struct dev_pm_ops fsi_pm_ops = {
  1223. .suspend = fsi_suspend,
  1224. .resume = fsi_resume,
  1225. };
  1226. static struct fsi_core fsi1_core = {
  1227. .ver = 1,
  1228. /* Interrupt */
  1229. .int_st = INT_ST,
  1230. .iemsk = IEMSK,
  1231. .imsk = IMSK,
  1232. };
  1233. static struct fsi_core fsi2_core = {
  1234. .ver = 2,
  1235. /* Interrupt */
  1236. .int_st = CPU_INT_ST,
  1237. .iemsk = CPU_IEMSK,
  1238. .imsk = CPU_IMSK,
  1239. .a_mclk = A_MST_CTLR,
  1240. .b_mclk = B_MST_CTLR,
  1241. };
  1242. static struct platform_device_id fsi_id_table[] = {
  1243. { "sh_fsi", (kernel_ulong_t)&fsi1_core },
  1244. { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
  1245. {},
  1246. };
  1247. MODULE_DEVICE_TABLE(platform, fsi_id_table);
  1248. static struct platform_driver fsi_driver = {
  1249. .driver = {
  1250. .name = "fsi-pcm-audio",
  1251. .pm = &fsi_pm_ops,
  1252. },
  1253. .probe = fsi_probe,
  1254. .remove = fsi_remove,
  1255. .id_table = fsi_id_table,
  1256. };
  1257. module_platform_driver(fsi_driver);
  1258. MODULE_LICENSE("GPL");
  1259. MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
  1260. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
  1261. MODULE_ALIAS("platform:fsi-pcm-audio");