wm8350-core.c 17 KB

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  1. /*
  2. * wm8350-core.c -- Device access for Wolfson WM8350
  3. *
  4. * Copyright 2007, 2008 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Liam Girdwood, Mark Brown
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/bug.h>
  18. #include <linux/device.h>
  19. #include <linux/delay.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/mfd/wm8350/core.h>
  23. #include <linux/mfd/wm8350/audio.h>
  24. #include <linux/mfd/wm8350/comparator.h>
  25. #include <linux/mfd/wm8350/gpio.h>
  26. #include <linux/mfd/wm8350/pmic.h>
  27. #include <linux/mfd/wm8350/rtc.h>
  28. #include <linux/mfd/wm8350/supply.h>
  29. #include <linux/mfd/wm8350/wdt.h>
  30. #define WM8350_UNLOCK_KEY 0x0013
  31. #define WM8350_LOCK_KEY 0x0000
  32. #define WM8350_CLOCK_CONTROL_1 0x28
  33. #define WM8350_AIF_TEST 0x74
  34. /* debug */
  35. #define WM8350_BUS_DEBUG 0
  36. #if WM8350_BUS_DEBUG
  37. #define dump(regs, src) do { \
  38. int i_; \
  39. u16 *src_ = src; \
  40. printk(KERN_DEBUG); \
  41. for (i_ = 0; i_ < regs; i_++) \
  42. printk(" 0x%4.4x", *src_++); \
  43. printk("\n"); \
  44. } while (0);
  45. #else
  46. #define dump(bytes, src)
  47. #endif
  48. #define WM8350_LOCK_DEBUG 0
  49. #if WM8350_LOCK_DEBUG
  50. #define ldbg(format, arg...) printk(format, ## arg)
  51. #else
  52. #define ldbg(format, arg...)
  53. #endif
  54. /*
  55. * WM8350 Device IO
  56. */
  57. static DEFINE_MUTEX(io_mutex);
  58. static DEFINE_MUTEX(reg_lock_mutex);
  59. /* Perform a physical read from the device.
  60. */
  61. static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
  62. u16 *dest)
  63. {
  64. int i, ret;
  65. int bytes = num_regs * 2;
  66. dev_dbg(wm8350->dev, "volatile read\n");
  67. ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
  68. for (i = reg; i < reg + num_regs; i++) {
  69. /* Cache is CPU endian */
  70. dest[i - reg] = be16_to_cpu(dest[i - reg]);
  71. /* Mask out non-readable bits */
  72. dest[i - reg] &= wm8350_reg_io_map[i].readable;
  73. }
  74. dump(num_regs, dest);
  75. return ret;
  76. }
  77. static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
  78. {
  79. int i;
  80. int end = reg + num_regs;
  81. int ret = 0;
  82. int bytes = num_regs * 2;
  83. if (wm8350->read_dev == NULL)
  84. return -ENODEV;
  85. if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
  86. dev_err(wm8350->dev, "invalid reg %x\n",
  87. reg + num_regs - 1);
  88. return -EINVAL;
  89. }
  90. dev_dbg(wm8350->dev,
  91. "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
  92. #if WM8350_BUS_DEBUG
  93. /* we can _safely_ read any register, but warn if read not supported */
  94. for (i = reg; i < end; i++) {
  95. if (!wm8350_reg_io_map[i].readable)
  96. dev_warn(wm8350->dev,
  97. "reg R%d is not readable\n", i);
  98. }
  99. #endif
  100. /* if any volatile registers are required, then read back all */
  101. for (i = reg; i < end; i++)
  102. if (wm8350_reg_io_map[i].vol)
  103. return wm8350_phys_read(wm8350, reg, num_regs, dest);
  104. /* no volatiles, then cache is good */
  105. dev_dbg(wm8350->dev, "cache read\n");
  106. memcpy(dest, &wm8350->reg_cache[reg], bytes);
  107. dump(num_regs, dest);
  108. return ret;
  109. }
  110. static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
  111. {
  112. if (reg == WM8350_SECURITY ||
  113. wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
  114. return 0;
  115. if ((reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
  116. reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
  117. (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
  118. reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
  119. return 1;
  120. return 0;
  121. }
  122. static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
  123. {
  124. int i;
  125. int end = reg + num_regs;
  126. int bytes = num_regs * 2;
  127. if (wm8350->write_dev == NULL)
  128. return -ENODEV;
  129. if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
  130. dev_err(wm8350->dev, "invalid reg %x\n",
  131. reg + num_regs - 1);
  132. return -EINVAL;
  133. }
  134. /* it's generally not a good idea to write to RO or locked registers */
  135. for (i = reg; i < end; i++) {
  136. if (!wm8350_reg_io_map[i].writable) {
  137. dev_err(wm8350->dev,
  138. "attempted write to read only reg R%d\n", i);
  139. return -EINVAL;
  140. }
  141. if (is_reg_locked(wm8350, i)) {
  142. dev_err(wm8350->dev,
  143. "attempted write to locked reg R%d\n", i);
  144. return -EINVAL;
  145. }
  146. src[i - reg] &= wm8350_reg_io_map[i].writable;
  147. wm8350->reg_cache[i] =
  148. (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
  149. | src[i - reg];
  150. src[i - reg] = cpu_to_be16(src[i - reg]);
  151. }
  152. /* Actually write it out */
  153. return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
  154. }
  155. /*
  156. * Safe read, modify, write methods
  157. */
  158. int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
  159. {
  160. u16 data;
  161. int err;
  162. mutex_lock(&io_mutex);
  163. err = wm8350_read(wm8350, reg, 1, &data);
  164. if (err) {
  165. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  166. goto out;
  167. }
  168. data &= ~mask;
  169. err = wm8350_write(wm8350, reg, 1, &data);
  170. if (err)
  171. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  172. out:
  173. mutex_unlock(&io_mutex);
  174. return err;
  175. }
  176. EXPORT_SYMBOL_GPL(wm8350_clear_bits);
  177. int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
  178. {
  179. u16 data;
  180. int err;
  181. mutex_lock(&io_mutex);
  182. err = wm8350_read(wm8350, reg, 1, &data);
  183. if (err) {
  184. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  185. goto out;
  186. }
  187. data |= mask;
  188. err = wm8350_write(wm8350, reg, 1, &data);
  189. if (err)
  190. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  191. out:
  192. mutex_unlock(&io_mutex);
  193. return err;
  194. }
  195. EXPORT_SYMBOL_GPL(wm8350_set_bits);
  196. u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
  197. {
  198. u16 data;
  199. int err;
  200. mutex_lock(&io_mutex);
  201. err = wm8350_read(wm8350, reg, 1, &data);
  202. if (err)
  203. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  204. mutex_unlock(&io_mutex);
  205. return data;
  206. }
  207. EXPORT_SYMBOL_GPL(wm8350_reg_read);
  208. int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
  209. {
  210. int ret;
  211. u16 data = val;
  212. mutex_lock(&io_mutex);
  213. ret = wm8350_write(wm8350, reg, 1, &data);
  214. if (ret)
  215. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  216. mutex_unlock(&io_mutex);
  217. return ret;
  218. }
  219. EXPORT_SYMBOL_GPL(wm8350_reg_write);
  220. int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
  221. u16 *dest)
  222. {
  223. int err = 0;
  224. mutex_lock(&io_mutex);
  225. err = wm8350_read(wm8350, start_reg, regs, dest);
  226. if (err)
  227. dev_err(wm8350->dev, "block read starting from R%d failed\n",
  228. start_reg);
  229. mutex_unlock(&io_mutex);
  230. return err;
  231. }
  232. EXPORT_SYMBOL_GPL(wm8350_block_read);
  233. int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
  234. u16 *src)
  235. {
  236. int ret = 0;
  237. mutex_lock(&io_mutex);
  238. ret = wm8350_write(wm8350, start_reg, regs, src);
  239. if (ret)
  240. dev_err(wm8350->dev, "block write starting at R%d failed\n",
  241. start_reg);
  242. mutex_unlock(&io_mutex);
  243. return ret;
  244. }
  245. EXPORT_SYMBOL_GPL(wm8350_block_write);
  246. /**
  247. * wm8350_reg_lock()
  248. *
  249. * The WM8350 has a hardware lock which can be used to prevent writes to
  250. * some registers (generally those which can cause particularly serious
  251. * problems if misused). This function enables that lock.
  252. */
  253. int wm8350_reg_lock(struct wm8350 *wm8350)
  254. {
  255. u16 key = WM8350_LOCK_KEY;
  256. int ret;
  257. ldbg(__func__);
  258. mutex_lock(&io_mutex);
  259. ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
  260. if (ret)
  261. dev_err(wm8350->dev, "lock failed\n");
  262. mutex_unlock(&io_mutex);
  263. return ret;
  264. }
  265. EXPORT_SYMBOL_GPL(wm8350_reg_lock);
  266. /**
  267. * wm8350_reg_unlock()
  268. *
  269. * The WM8350 has a hardware lock which can be used to prevent writes to
  270. * some registers (generally those which can cause particularly serious
  271. * problems if misused). This function disables that lock so updates
  272. * can be performed. For maximum safety this should be done only when
  273. * required.
  274. */
  275. int wm8350_reg_unlock(struct wm8350 *wm8350)
  276. {
  277. u16 key = WM8350_UNLOCK_KEY;
  278. int ret;
  279. ldbg(__func__);
  280. mutex_lock(&io_mutex);
  281. ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
  282. if (ret)
  283. dev_err(wm8350->dev, "unlock failed\n");
  284. mutex_unlock(&io_mutex);
  285. return ret;
  286. }
  287. EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
  288. int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref)
  289. {
  290. u16 reg, result = 0;
  291. int tries = 5;
  292. if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP)
  293. return -EINVAL;
  294. if (channel >= WM8350_AUXADC_USB && channel <= WM8350_AUXADC_TEMP
  295. && (scale != 0 || vref != 0))
  296. return -EINVAL;
  297. mutex_lock(&wm8350->auxadc_mutex);
  298. /* Turn on the ADC */
  299. reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
  300. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA);
  301. if (scale || vref) {
  302. reg = scale << 13;
  303. reg |= vref << 12;
  304. wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg);
  305. }
  306. reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
  307. reg |= 1 << channel | WM8350_AUXADC_POLL;
  308. wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg);
  309. do {
  310. schedule_timeout_interruptible(1);
  311. reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
  312. } while ((reg & WM8350_AUXADC_POLL) && --tries);
  313. if (!tries)
  314. dev_err(wm8350->dev, "adc chn %d read timeout\n", channel);
  315. else
  316. result = wm8350_reg_read(wm8350,
  317. WM8350_AUX1_READBACK + channel);
  318. /* Turn off the ADC */
  319. reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
  320. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5,
  321. reg & ~WM8350_AUXADC_ENA);
  322. mutex_unlock(&wm8350->auxadc_mutex);
  323. return result & WM8350_AUXADC_DATA1_MASK;
  324. }
  325. EXPORT_SYMBOL_GPL(wm8350_read_auxadc);
  326. /*
  327. * Cache is always host endian.
  328. */
  329. static int wm8350_create_cache(struct wm8350 *wm8350, int type, int mode)
  330. {
  331. int i, ret = 0;
  332. u16 value;
  333. const u16 *reg_map;
  334. switch (type) {
  335. case 0:
  336. switch (mode) {
  337. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
  338. case 0:
  339. reg_map = wm8350_mode0_defaults;
  340. break;
  341. #endif
  342. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
  343. case 1:
  344. reg_map = wm8350_mode1_defaults;
  345. break;
  346. #endif
  347. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
  348. case 2:
  349. reg_map = wm8350_mode2_defaults;
  350. break;
  351. #endif
  352. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
  353. case 3:
  354. reg_map = wm8350_mode3_defaults;
  355. break;
  356. #endif
  357. default:
  358. dev_err(wm8350->dev,
  359. "WM8350 configuration mode %d not supported\n",
  360. mode);
  361. return -EINVAL;
  362. }
  363. break;
  364. case 1:
  365. switch (mode) {
  366. #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
  367. case 0:
  368. reg_map = wm8351_mode0_defaults;
  369. break;
  370. #endif
  371. #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
  372. case 1:
  373. reg_map = wm8351_mode1_defaults;
  374. break;
  375. #endif
  376. #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
  377. case 2:
  378. reg_map = wm8351_mode2_defaults;
  379. break;
  380. #endif
  381. #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
  382. case 3:
  383. reg_map = wm8351_mode3_defaults;
  384. break;
  385. #endif
  386. default:
  387. dev_err(wm8350->dev,
  388. "WM8351 configuration mode %d not supported\n",
  389. mode);
  390. return -EINVAL;
  391. }
  392. break;
  393. case 2:
  394. switch (mode) {
  395. #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
  396. case 0:
  397. reg_map = wm8352_mode0_defaults;
  398. break;
  399. #endif
  400. #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
  401. case 1:
  402. reg_map = wm8352_mode1_defaults;
  403. break;
  404. #endif
  405. #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
  406. case 2:
  407. reg_map = wm8352_mode2_defaults;
  408. break;
  409. #endif
  410. #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
  411. case 3:
  412. reg_map = wm8352_mode3_defaults;
  413. break;
  414. #endif
  415. default:
  416. dev_err(wm8350->dev,
  417. "WM8352 configuration mode %d not supported\n",
  418. mode);
  419. return -EINVAL;
  420. }
  421. break;
  422. default:
  423. dev_err(wm8350->dev,
  424. "WM835x configuration mode %d not supported\n",
  425. mode);
  426. return -EINVAL;
  427. }
  428. wm8350->reg_cache =
  429. kmalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
  430. if (wm8350->reg_cache == NULL)
  431. return -ENOMEM;
  432. /* Read the initial cache state back from the device - this is
  433. * a PMIC so the device many not be in a virgin state and we
  434. * can't rely on the silicon values.
  435. */
  436. ret = wm8350->read_dev(wm8350, 0,
  437. sizeof(u16) * (WM8350_MAX_REGISTER + 1),
  438. wm8350->reg_cache);
  439. if (ret < 0) {
  440. dev_err(wm8350->dev,
  441. "failed to read initial cache values\n");
  442. goto out;
  443. }
  444. /* Mask out uncacheable/unreadable bits and the audio. */
  445. for (i = 0; i < WM8350_MAX_REGISTER; i++) {
  446. if (wm8350_reg_io_map[i].readable &&
  447. (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
  448. value = be16_to_cpu(wm8350->reg_cache[i]);
  449. value &= wm8350_reg_io_map[i].readable;
  450. wm8350->reg_cache[i] = value;
  451. } else
  452. wm8350->reg_cache[i] = reg_map[i];
  453. }
  454. out:
  455. return ret;
  456. }
  457. /*
  458. * Register a client device. This is non-fatal since there is no need to
  459. * fail the entire device init due to a single platform device failing.
  460. */
  461. static void wm8350_client_dev_register(struct wm8350 *wm8350,
  462. const char *name,
  463. struct platform_device **pdev)
  464. {
  465. int ret;
  466. *pdev = platform_device_alloc(name, -1);
  467. if (*pdev == NULL) {
  468. dev_err(wm8350->dev, "Failed to allocate %s\n", name);
  469. return;
  470. }
  471. (*pdev)->dev.parent = wm8350->dev;
  472. platform_set_drvdata(*pdev, wm8350);
  473. ret = platform_device_add(*pdev);
  474. if (ret != 0) {
  475. dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
  476. platform_device_put(*pdev);
  477. *pdev = NULL;
  478. }
  479. }
  480. int wm8350_device_init(struct wm8350 *wm8350, int irq,
  481. struct wm8350_platform_data *pdata)
  482. {
  483. int ret;
  484. u16 id1, id2, mask_rev;
  485. u16 cust_id, mode, chip_rev;
  486. /* get WM8350 revision and config mode */
  487. ret = wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
  488. if (ret != 0) {
  489. dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
  490. goto err;
  491. }
  492. ret = wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
  493. if (ret != 0) {
  494. dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
  495. goto err;
  496. }
  497. ret = wm8350->read_dev(wm8350, WM8350_REVISION, sizeof(mask_rev),
  498. &mask_rev);
  499. if (ret != 0) {
  500. dev_err(wm8350->dev, "Failed to read revision: %d\n", ret);
  501. goto err;
  502. }
  503. id1 = be16_to_cpu(id1);
  504. id2 = be16_to_cpu(id2);
  505. mask_rev = be16_to_cpu(mask_rev);
  506. if (id1 != 0x6143) {
  507. dev_err(wm8350->dev,
  508. "Device with ID %x is not a WM8350\n", id1);
  509. ret = -ENODEV;
  510. goto err;
  511. }
  512. mode = id2 & WM8350_CONF_STS_MASK >> 10;
  513. cust_id = id2 & WM8350_CUST_ID_MASK;
  514. chip_rev = (id2 & WM8350_CHIP_REV_MASK) >> 12;
  515. dev_info(wm8350->dev,
  516. "CONF_STS %d, CUST_ID %d, MASK_REV %d, CHIP_REV %d\n",
  517. mode, cust_id, mask_rev, chip_rev);
  518. if (cust_id != 0) {
  519. dev_err(wm8350->dev, "Unsupported CUST_ID\n");
  520. ret = -ENODEV;
  521. goto err;
  522. }
  523. switch (mask_rev) {
  524. case 0:
  525. wm8350->pmic.max_dcdc = WM8350_DCDC_6;
  526. wm8350->pmic.max_isink = WM8350_ISINK_B;
  527. switch (chip_rev) {
  528. case WM8350_REV_E:
  529. dev_info(wm8350->dev, "WM8350 Rev E\n");
  530. break;
  531. case WM8350_REV_F:
  532. dev_info(wm8350->dev, "WM8350 Rev F\n");
  533. break;
  534. case WM8350_REV_G:
  535. dev_info(wm8350->dev, "WM8350 Rev G\n");
  536. wm8350->power.rev_g_coeff = 1;
  537. break;
  538. case WM8350_REV_H:
  539. dev_info(wm8350->dev, "WM8350 Rev H\n");
  540. wm8350->power.rev_g_coeff = 1;
  541. break;
  542. default:
  543. /* For safety we refuse to run on unknown hardware */
  544. dev_err(wm8350->dev, "Unknown WM8350 CHIP_REV\n");
  545. ret = -ENODEV;
  546. goto err;
  547. }
  548. break;
  549. case 1:
  550. wm8350->pmic.max_dcdc = WM8350_DCDC_4;
  551. wm8350->pmic.max_isink = WM8350_ISINK_A;
  552. switch (chip_rev) {
  553. case 0:
  554. dev_info(wm8350->dev, "WM8351 Rev A\n");
  555. wm8350->power.rev_g_coeff = 1;
  556. break;
  557. case 1:
  558. dev_info(wm8350->dev, "WM8351 Rev B\n");
  559. wm8350->power.rev_g_coeff = 1;
  560. break;
  561. default:
  562. dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n");
  563. ret = -ENODEV;
  564. goto err;
  565. }
  566. break;
  567. case 2:
  568. wm8350->pmic.max_dcdc = WM8350_DCDC_6;
  569. wm8350->pmic.max_isink = WM8350_ISINK_B;
  570. switch (chip_rev) {
  571. case 0:
  572. dev_info(wm8350->dev, "WM8352 Rev A\n");
  573. wm8350->power.rev_g_coeff = 1;
  574. break;
  575. default:
  576. dev_err(wm8350->dev, "Unknown WM8352 CHIP_REV\n");
  577. ret = -ENODEV;
  578. goto err;
  579. }
  580. break;
  581. default:
  582. dev_err(wm8350->dev, "Unknown MASK_REV\n");
  583. ret = -ENODEV;
  584. goto err;
  585. }
  586. ret = wm8350_create_cache(wm8350, mask_rev, mode);
  587. if (ret < 0) {
  588. dev_err(wm8350->dev, "Failed to create register cache\n");
  589. return ret;
  590. }
  591. mutex_init(&wm8350->auxadc_mutex);
  592. ret = wm8350_irq_init(wm8350, irq, pdata);
  593. if (ret < 0)
  594. goto err;
  595. if (pdata && pdata->init) {
  596. ret = pdata->init(wm8350);
  597. if (ret != 0) {
  598. dev_err(wm8350->dev, "Platform init() failed: %d\n",
  599. ret);
  600. goto err_irq;
  601. }
  602. }
  603. wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
  604. wm8350_client_dev_register(wm8350, "wm8350-codec",
  605. &(wm8350->codec.pdev));
  606. wm8350_client_dev_register(wm8350, "wm8350-gpio",
  607. &(wm8350->gpio.pdev));
  608. wm8350_client_dev_register(wm8350, "wm8350-hwmon",
  609. &(wm8350->hwmon.pdev));
  610. wm8350_client_dev_register(wm8350, "wm8350-power",
  611. &(wm8350->power.pdev));
  612. wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
  613. wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
  614. return 0;
  615. err_irq:
  616. wm8350_irq_exit(wm8350);
  617. err:
  618. kfree(wm8350->reg_cache);
  619. return ret;
  620. }
  621. EXPORT_SYMBOL_GPL(wm8350_device_init);
  622. void wm8350_device_exit(struct wm8350 *wm8350)
  623. {
  624. int i;
  625. for (i = 0; i < ARRAY_SIZE(wm8350->pmic.led); i++)
  626. platform_device_unregister(wm8350->pmic.led[i].pdev);
  627. for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
  628. platform_device_unregister(wm8350->pmic.pdev[i]);
  629. platform_device_unregister(wm8350->wdt.pdev);
  630. platform_device_unregister(wm8350->rtc.pdev);
  631. platform_device_unregister(wm8350->power.pdev);
  632. platform_device_unregister(wm8350->hwmon.pdev);
  633. platform_device_unregister(wm8350->gpio.pdev);
  634. platform_device_unregister(wm8350->codec.pdev);
  635. wm8350_irq_exit(wm8350);
  636. kfree(wm8350->reg_cache);
  637. }
  638. EXPORT_SYMBOL_GPL(wm8350_device_exit);
  639. MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
  640. MODULE_LICENSE("GPL");