common.c 4.1 KB

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  1. /*
  2. * arch/arm/mach-tegra/common.c
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. *
  6. * Author:
  7. * Colin Cross <ccross@android.com>
  8. *
  9. * This software is licensed under the terms of the GNU General Public
  10. * License version 2, as published by the Free Software Foundation, and
  11. * may be copied, distributed, and modified under those terms.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. */
  19. #include <linux/init.h>
  20. #include <linux/io.h>
  21. #include <linux/clk.h>
  22. #include <linux/delay.h>
  23. #include <linux/of_irq.h>
  24. #include <asm/hardware/cache-l2x0.h>
  25. #include <asm/hardware/gic.h>
  26. #include <mach/powergate.h>
  27. #include "board.h"
  28. #include "clock.h"
  29. #include "common.h"
  30. #include "fuse.h"
  31. #include "iomap.h"
  32. #include "pmc.h"
  33. #include "apbio.h"
  34. #include "sleep.h"
  35. /*
  36. * Storage for debug-macro.S's state.
  37. *
  38. * This must be in .data not .bss so that it gets initialized each time the
  39. * kernel is loaded. The data is declared here rather than debug-macro.S so
  40. * that multiple inclusions of debug-macro.S point at the same data.
  41. */
  42. #define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
  43. u32 tegra_uart_config[3] = {
  44. /* Debug UART initialization required */
  45. 1,
  46. /* Debug UART physical address */
  47. (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
  48. /* Debug UART virtual address */
  49. (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
  50. };
  51. #ifdef CONFIG_OF
  52. static const struct of_device_id tegra_dt_irq_match[] __initconst = {
  53. { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
  54. { }
  55. };
  56. void __init tegra_dt_init_irq(void)
  57. {
  58. tegra_init_irq();
  59. of_irq_init(tegra_dt_irq_match);
  60. }
  61. #endif
  62. void tegra_assert_system_reset(char mode, const char *cmd)
  63. {
  64. void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
  65. u32 reg;
  66. reg = readl_relaxed(reset);
  67. reg |= 0x10;
  68. writel_relaxed(reg, reset);
  69. }
  70. #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  71. static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
  72. /* name parent rate enabled */
  73. { "clk_m", NULL, 0, true },
  74. { "pll_p", "clk_m", 216000000, true },
  75. { "pll_p_out1", "pll_p", 28800000, true },
  76. { "pll_p_out2", "pll_p", 48000000, true },
  77. { "pll_p_out3", "pll_p", 72000000, true },
  78. { "pll_p_out4", "pll_p", 24000000, true },
  79. { "pll_c", "clk_m", 600000000, true },
  80. { "pll_c_out1", "pll_c", 120000000, true },
  81. { "sclk", "pll_c_out1", 120000000, true },
  82. { "hclk", "sclk", 120000000, true },
  83. { "pclk", "hclk", 60000000, true },
  84. { "csite", NULL, 0, true },
  85. { "emc", NULL, 0, true },
  86. { "cpu", NULL, 0, true },
  87. { NULL, NULL, 0, 0},
  88. };
  89. #endif
  90. #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  91. static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
  92. /* name parent rate enabled */
  93. { "clk_m", NULL, 0, true },
  94. { "pll_p", "clk_m", 408000000, true },
  95. { "pll_p_out1", "pll_p", 9600000, true },
  96. { "pll_p_out4", "pll_p", 102000000, true },
  97. { "sclk", "pll_p_out4", 102000000, true },
  98. { "hclk", "sclk", 102000000, true },
  99. { "pclk", "hclk", 51000000, true },
  100. { "csite", NULL, 0, true },
  101. { NULL, NULL, 0, 0},
  102. };
  103. #endif
  104. static void __init tegra_init_cache(void)
  105. {
  106. #ifdef CONFIG_CACHE_L2X0
  107. void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
  108. u32 aux_ctrl, cache_type;
  109. cache_type = readl(p + L2X0_CACHE_TYPE);
  110. aux_ctrl = (cache_type & 0x700) << (17-8);
  111. aux_ctrl |= 0x7C400001;
  112. l2x0_of_init(aux_ctrl, 0x8200c3fe);
  113. #endif
  114. }
  115. #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  116. void __init tegra20_init_early(void)
  117. {
  118. tegra_apb_io_init();
  119. tegra_init_fuse();
  120. tegra2_init_clocks();
  121. tegra_clk_init_from_table(tegra20_clk_init_table);
  122. tegra_init_cache();
  123. tegra_pmc_init();
  124. tegra_powergate_init();
  125. tegra20_hotplug_init();
  126. }
  127. #endif
  128. #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  129. void __init tegra30_init_early(void)
  130. {
  131. tegra_apb_io_init();
  132. tegra_init_fuse();
  133. tegra30_init_clocks();
  134. tegra_clk_init_from_table(tegra30_clk_init_table);
  135. tegra_init_cache();
  136. tegra_pmc_init();
  137. tegra_powergate_init();
  138. tegra30_hotplug_init();
  139. }
  140. #endif
  141. void __init tegra_init_late(void)
  142. {
  143. tegra_powergate_debugfs_init();
  144. }