iwl-4965.c 130 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #define IWL 4965
  39. #include "iwlwifi.h"
  40. #include "iwl-4965.h"
  41. #include "iwl-helpers.h"
  42. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  43. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  44. IWL_RATE_SISO_##s##M_PLCP, \
  45. IWL_RATE_MIMO_##s##M_PLCP, \
  46. IWL_RATE_##r##M_IEEE, \
  47. IWL_RATE_##ip##M_INDEX, \
  48. IWL_RATE_##in##M_INDEX, \
  49. IWL_RATE_##rp##M_INDEX, \
  50. IWL_RATE_##rn##M_INDEX, \
  51. IWL_RATE_##pp##M_INDEX, \
  52. IWL_RATE_##np##M_INDEX }
  53. /*
  54. * Parameter order:
  55. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  56. *
  57. * If there isn't a valid next or previous rate then INV is used which
  58. * maps to IWL_RATE_INVALID
  59. *
  60. */
  61. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  62. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  63. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  64. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  65. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  66. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  67. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  68. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  69. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  70. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  71. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  72. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  73. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  74. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  75. };
  76. static int is_fat_channel(__le32 rxon_flags)
  77. {
  78. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  79. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  80. }
  81. static u8 is_single_stream(struct iwl_priv *priv)
  82. {
  83. #ifdef CONFIG_IWLWIFI_HT
  84. if (!priv->is_ht_enabled || !priv->current_assoc_ht.is_ht ||
  85. (priv->active_rate_ht[1] == 0) ||
  86. (priv->ps_mode == IWL_MIMO_PS_STATIC))
  87. return 1;
  88. #else
  89. return 1;
  90. #endif /*CONFIG_IWLWIFI_HT */
  91. return 0;
  92. }
  93. /*
  94. * Determine how many receiver/antenna chains to use.
  95. * More provides better reception via diversity. Fewer saves power.
  96. * MIMO (dual stream) requires at least 2, but works better with 3.
  97. * This does not determine *which* chains to use, just how many.
  98. */
  99. static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
  100. u8 *idle_state, u8 *rx_state)
  101. {
  102. u8 is_single = is_single_stream(priv);
  103. u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
  104. /* # of Rx chains to use when expecting MIMO. */
  105. if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
  106. *rx_state = 2;
  107. else
  108. *rx_state = 3;
  109. /* # Rx chains when idling and maybe trying to save power */
  110. switch (priv->ps_mode) {
  111. case IWL_MIMO_PS_STATIC:
  112. case IWL_MIMO_PS_DYNAMIC:
  113. *idle_state = (is_cam) ? 2 : 1;
  114. break;
  115. case IWL_MIMO_PS_NONE:
  116. *idle_state = (is_cam) ? *rx_state : 1;
  117. break;
  118. default:
  119. *idle_state = 1;
  120. break;
  121. }
  122. return 0;
  123. }
  124. int iwl_hw_rxq_stop(struct iwl_priv *priv)
  125. {
  126. int rc;
  127. unsigned long flags;
  128. spin_lock_irqsave(&priv->lock, flags);
  129. rc = iwl_grab_restricted_access(priv);
  130. if (rc) {
  131. spin_unlock_irqrestore(&priv->lock, flags);
  132. return rc;
  133. }
  134. /* stop HW */
  135. iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  136. rc = iwl_poll_restricted_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  137. (1 << 24), 1000);
  138. if (rc < 0)
  139. IWL_ERROR("Can't stop Rx DMA.\n");
  140. iwl_release_restricted_access(priv);
  141. spin_unlock_irqrestore(&priv->lock, flags);
  142. return 0;
  143. }
  144. u8 iwl_hw_find_station(struct iwl_priv *priv, const u8 *addr)
  145. {
  146. int i;
  147. int start = 0;
  148. int ret = IWL_INVALID_STATION;
  149. unsigned long flags;
  150. DECLARE_MAC_BUF(mac);
  151. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
  152. (priv->iw_mode == IEEE80211_IF_TYPE_AP))
  153. start = IWL_STA_ID;
  154. if (is_broadcast_ether_addr(addr))
  155. return IWL4965_BROADCAST_ID;
  156. spin_lock_irqsave(&priv->sta_lock, flags);
  157. for (i = start; i < priv->hw_setting.max_stations; i++)
  158. if ((priv->stations[i].used) &&
  159. (!compare_ether_addr
  160. (priv->stations[i].sta.sta.addr, addr))) {
  161. ret = i;
  162. goto out;
  163. }
  164. IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
  165. print_mac(mac, addr), priv->num_stations);
  166. out:
  167. spin_unlock_irqrestore(&priv->sta_lock, flags);
  168. return ret;
  169. }
  170. static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
  171. {
  172. int rc = 0;
  173. unsigned long flags;
  174. spin_lock_irqsave(&priv->lock, flags);
  175. rc = iwl_grab_restricted_access(priv);
  176. if (rc) {
  177. spin_unlock_irqrestore(&priv->lock, flags);
  178. return rc;
  179. }
  180. if (!pwr_max) {
  181. u32 val;
  182. rc = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  183. &val);
  184. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
  185. iwl_set_bits_mask_restricted_reg(
  186. priv, APMG_PS_CTRL_REG,
  187. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  188. ~APMG_PS_CTRL_MSK_PWR_SRC);
  189. } else
  190. iwl_set_bits_mask_restricted_reg(
  191. priv, APMG_PS_CTRL_REG,
  192. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  193. ~APMG_PS_CTRL_MSK_PWR_SRC);
  194. iwl_release_restricted_access(priv);
  195. spin_unlock_irqrestore(&priv->lock, flags);
  196. return rc;
  197. }
  198. static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  199. {
  200. int rc;
  201. unsigned long flags;
  202. spin_lock_irqsave(&priv->lock, flags);
  203. rc = iwl_grab_restricted_access(priv);
  204. if (rc) {
  205. spin_unlock_irqrestore(&priv->lock, flags);
  206. return rc;
  207. }
  208. /* stop HW */
  209. iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  210. iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  211. iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  212. rxq->dma_addr >> 8);
  213. iwl_write_restricted(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  214. (priv->hw_setting.shared_phys +
  215. offsetof(struct iwl_shared, val0)) >> 4);
  216. iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  217. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  218. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  219. IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K |
  220. /*0x10 << 4 | */
  221. (RX_QUEUE_SIZE_LOG <<
  222. FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
  223. /*
  224. * iwl_write32(priv,CSR_INT_COAL_REG,0);
  225. */
  226. iwl_release_restricted_access(priv);
  227. spin_unlock_irqrestore(&priv->lock, flags);
  228. return 0;
  229. }
  230. static int iwl4965_kw_init(struct iwl_priv *priv)
  231. {
  232. unsigned long flags;
  233. int rc;
  234. spin_lock_irqsave(&priv->lock, flags);
  235. rc = iwl_grab_restricted_access(priv);
  236. if (rc)
  237. goto out;
  238. iwl_write_restricted(priv, IWL_FH_KW_MEM_ADDR_REG,
  239. priv->kw.dma_addr >> 4);
  240. iwl_release_restricted_access(priv);
  241. out:
  242. spin_unlock_irqrestore(&priv->lock, flags);
  243. return rc;
  244. }
  245. static int iwl4965_kw_alloc(struct iwl_priv *priv)
  246. {
  247. struct pci_dev *dev = priv->pci_dev;
  248. struct iwl_kw *kw = &priv->kw;
  249. kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
  250. kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
  251. if (!kw->v_addr)
  252. return -ENOMEM;
  253. return 0;
  254. }
  255. #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
  256. ? # x " " : "")
  257. int iwl4965_set_fat_chan_info(struct iwl_priv *priv, int phymode, u16 channel,
  258. const struct iwl_eeprom_channel *eeprom_ch,
  259. u8 fat_extension_channel)
  260. {
  261. struct iwl_channel_info *ch_info;
  262. ch_info = (struct iwl_channel_info *)
  263. iwl_get_channel_info(priv, phymode, channel);
  264. if (!is_channel_valid(ch_info))
  265. return -1;
  266. IWL_DEBUG_INFO("FAT Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  267. " %ddBm): Ad-Hoc %ssupported\n",
  268. ch_info->channel,
  269. is_channel_a_band(ch_info) ?
  270. "5.2" : "2.4",
  271. CHECK_AND_PRINT(IBSS),
  272. CHECK_AND_PRINT(ACTIVE),
  273. CHECK_AND_PRINT(RADAR),
  274. CHECK_AND_PRINT(WIDE),
  275. CHECK_AND_PRINT(NARROW),
  276. CHECK_AND_PRINT(DFS),
  277. eeprom_ch->flags,
  278. eeprom_ch->max_power_avg,
  279. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
  280. && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
  281. "" : "not ");
  282. ch_info->fat_eeprom = *eeprom_ch;
  283. ch_info->fat_max_power_avg = eeprom_ch->max_power_avg;
  284. ch_info->fat_curr_txpow = eeprom_ch->max_power_avg;
  285. ch_info->fat_min_power = 0;
  286. ch_info->fat_scan_power = eeprom_ch->max_power_avg;
  287. ch_info->fat_flags = eeprom_ch->flags;
  288. ch_info->fat_extension_channel = fat_extension_channel;
  289. return 0;
  290. }
  291. static void iwl4965_kw_free(struct iwl_priv *priv)
  292. {
  293. struct pci_dev *dev = priv->pci_dev;
  294. struct iwl_kw *kw = &priv->kw;
  295. if (kw->v_addr) {
  296. pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
  297. memset(kw, 0, sizeof(*kw));
  298. }
  299. }
  300. /**
  301. * iwl4965_txq_ctx_reset - Reset TX queue context
  302. * Destroys all DMA structures and initialise them again
  303. *
  304. * @param priv
  305. * @return error code
  306. */
  307. static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
  308. {
  309. int rc = 0;
  310. int txq_id, slots_num;
  311. unsigned long flags;
  312. iwl4965_kw_free(priv);
  313. iwl_hw_txq_ctx_free(priv);
  314. /* Tx CMD queue */
  315. rc = iwl4965_kw_alloc(priv);
  316. if (rc) {
  317. IWL_ERROR("Keep Warm allocation failed");
  318. goto error_kw;
  319. }
  320. spin_lock_irqsave(&priv->lock, flags);
  321. rc = iwl_grab_restricted_access(priv);
  322. if (unlikely(rc)) {
  323. IWL_ERROR("TX reset failed");
  324. spin_unlock_irqrestore(&priv->lock, flags);
  325. goto error_reset;
  326. }
  327. iwl_write_restricted_reg(priv, SCD_TXFACT, 0);
  328. iwl_release_restricted_access(priv);
  329. spin_unlock_irqrestore(&priv->lock, flags);
  330. rc = iwl4965_kw_init(priv);
  331. if (rc) {
  332. IWL_ERROR("kw_init failed\n");
  333. goto error_reset;
  334. }
  335. /* Tx queue(s) */
  336. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  337. slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
  338. TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
  339. rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
  340. txq_id);
  341. if (rc) {
  342. IWL_ERROR("Tx %d queue init failed\n", txq_id);
  343. goto error;
  344. }
  345. }
  346. return rc;
  347. error:
  348. iwl_hw_txq_ctx_free(priv);
  349. error_reset:
  350. iwl4965_kw_free(priv);
  351. error_kw:
  352. return rc;
  353. }
  354. int iwl_hw_nic_init(struct iwl_priv *priv)
  355. {
  356. int rc;
  357. unsigned long flags;
  358. struct iwl_rx_queue *rxq = &priv->rxq;
  359. u8 rev_id;
  360. u32 val;
  361. u8 val_link;
  362. iwl_power_init_handle(priv);
  363. /* nic_init */
  364. spin_lock_irqsave(&priv->lock, flags);
  365. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  366. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  367. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  368. rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
  369. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  370. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  371. if (rc < 0) {
  372. spin_unlock_irqrestore(&priv->lock, flags);
  373. IWL_DEBUG_INFO("Failed to init the card\n");
  374. return rc;
  375. }
  376. rc = iwl_grab_restricted_access(priv);
  377. if (rc) {
  378. spin_unlock_irqrestore(&priv->lock, flags);
  379. return rc;
  380. }
  381. iwl_read_restricted_reg(priv, APMG_CLK_CTRL_REG);
  382. iwl_write_restricted_reg(priv, APMG_CLK_CTRL_REG,
  383. APMG_CLK_VAL_DMA_CLK_RQT |
  384. APMG_CLK_VAL_BSM_CLK_RQT);
  385. iwl_read_restricted_reg(priv, APMG_CLK_CTRL_REG);
  386. udelay(20);
  387. iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG,
  388. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  389. iwl_release_restricted_access(priv);
  390. iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
  391. spin_unlock_irqrestore(&priv->lock, flags);
  392. /* Determine HW type */
  393. rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
  394. if (rc)
  395. return rc;
  396. IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
  397. iwl4965_nic_set_pwr_src(priv, 1);
  398. spin_lock_irqsave(&priv->lock, flags);
  399. if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
  400. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  401. /* Enable No Snoop field */
  402. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  403. val & ~(1 << 11));
  404. }
  405. spin_unlock_irqrestore(&priv->lock, flags);
  406. /* Read the EEPROM */
  407. rc = iwl_eeprom_init(priv);
  408. if (rc)
  409. return rc;
  410. if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
  411. IWL_ERROR("Older EEPROM detected! Aborting.\n");
  412. return -EINVAL;
  413. }
  414. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  415. /* disable L1 entry -- workaround for pre-B1 */
  416. pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
  417. spin_lock_irqsave(&priv->lock, flags);
  418. /* set CSR_HW_CONFIG_REG for uCode use */
  419. iwl_set_bit(priv, CSR_SW_VER, CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R |
  420. CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  421. CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  422. rc = iwl_grab_restricted_access(priv);
  423. if (rc < 0) {
  424. spin_unlock_irqrestore(&priv->lock, flags);
  425. IWL_DEBUG_INFO("Failed to init the card\n");
  426. return rc;
  427. }
  428. iwl_read_restricted_reg(priv, APMG_PS_CTRL_REG);
  429. iwl_set_bits_restricted_reg(priv, APMG_PS_CTRL_REG,
  430. APMG_PS_CTRL_VAL_RESET_REQ);
  431. udelay(5);
  432. iwl_clear_bits_restricted_reg(priv, APMG_PS_CTRL_REG,
  433. APMG_PS_CTRL_VAL_RESET_REQ);
  434. iwl_release_restricted_access(priv);
  435. spin_unlock_irqrestore(&priv->lock, flags);
  436. iwl_hw_card_show_info(priv);
  437. /* end nic_init */
  438. /* Allocate the RX queue, or reset if it is already allocated */
  439. if (!rxq->bd) {
  440. rc = iwl_rx_queue_alloc(priv);
  441. if (rc) {
  442. IWL_ERROR("Unable to initialize Rx queue\n");
  443. return -ENOMEM;
  444. }
  445. } else
  446. iwl_rx_queue_reset(priv, rxq);
  447. iwl_rx_replenish(priv);
  448. iwl4965_rx_init(priv, rxq);
  449. spin_lock_irqsave(&priv->lock, flags);
  450. rxq->need_update = 1;
  451. iwl_rx_queue_update_write_ptr(priv, rxq);
  452. spin_unlock_irqrestore(&priv->lock, flags);
  453. rc = iwl4965_txq_ctx_reset(priv);
  454. if (rc)
  455. return rc;
  456. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
  457. IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
  458. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
  459. IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
  460. set_bit(STATUS_INIT, &priv->status);
  461. return 0;
  462. }
  463. int iwl_hw_nic_stop_master(struct iwl_priv *priv)
  464. {
  465. int rc = 0;
  466. u32 reg_val;
  467. unsigned long flags;
  468. spin_lock_irqsave(&priv->lock, flags);
  469. /* set stop master bit */
  470. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  471. reg_val = iwl_read32(priv, CSR_GP_CNTRL);
  472. if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
  473. (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
  474. IWL_DEBUG_INFO("Card in power save, master is already "
  475. "stopped\n");
  476. else {
  477. rc = iwl_poll_bit(priv, CSR_RESET,
  478. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  479. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  480. if (rc < 0) {
  481. spin_unlock_irqrestore(&priv->lock, flags);
  482. return rc;
  483. }
  484. }
  485. spin_unlock_irqrestore(&priv->lock, flags);
  486. IWL_DEBUG_INFO("stop master\n");
  487. return rc;
  488. }
  489. void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
  490. {
  491. int txq_id;
  492. unsigned long flags;
  493. /* reset TFD queues */
  494. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  495. spin_lock_irqsave(&priv->lock, flags);
  496. if (iwl_grab_restricted_access(priv)) {
  497. spin_unlock_irqrestore(&priv->lock, flags);
  498. continue;
  499. }
  500. iwl_write_restricted(priv,
  501. IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
  502. 0x0);
  503. iwl_poll_restricted_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
  504. IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
  505. (txq_id), 200);
  506. iwl_release_restricted_access(priv);
  507. spin_unlock_irqrestore(&priv->lock, flags);
  508. }
  509. iwl_hw_txq_ctx_free(priv);
  510. }
  511. int iwl_hw_nic_reset(struct iwl_priv *priv)
  512. {
  513. int rc = 0;
  514. unsigned long flags;
  515. iwl_hw_nic_stop_master(priv);
  516. spin_lock_irqsave(&priv->lock, flags);
  517. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  518. udelay(10);
  519. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  520. rc = iwl_poll_bit(priv, CSR_RESET,
  521. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  522. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  523. udelay(10);
  524. rc = iwl_grab_restricted_access(priv);
  525. if (!rc) {
  526. iwl_write_restricted_reg(priv, APMG_CLK_EN_REG,
  527. APMG_CLK_VAL_DMA_CLK_RQT |
  528. APMG_CLK_VAL_BSM_CLK_RQT);
  529. udelay(10);
  530. iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG,
  531. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  532. iwl_release_restricted_access(priv);
  533. }
  534. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  535. wake_up_interruptible(&priv->wait_command_queue);
  536. spin_unlock_irqrestore(&priv->lock, flags);
  537. return rc;
  538. }
  539. #define REG_RECALIB_PERIOD (60)
  540. /**
  541. * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
  542. *
  543. * This callback is provided in order to queue the statistics_work
  544. * in work_queue context (v. softirq)
  545. *
  546. * This timer function is continually reset to execute within
  547. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  548. * was received. We need to ensure we receive the statistics in order
  549. * to update the temperature used for calibrating the TXPOWER. However,
  550. * we can't send the statistics command from softirq context (which
  551. * is the context which timers run at) so we have to queue off the
  552. * statistics_work to actually send the command to the hardware.
  553. */
  554. static void iwl4965_bg_statistics_periodic(unsigned long data)
  555. {
  556. struct iwl_priv *priv = (struct iwl_priv *)data;
  557. queue_work(priv->workqueue, &priv->statistics_work);
  558. }
  559. /**
  560. * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
  561. *
  562. * This is queued by iwl_bg_statistics_periodic.
  563. */
  564. static void iwl4965_bg_statistics_work(struct work_struct *work)
  565. {
  566. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  567. statistics_work);
  568. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  569. return;
  570. mutex_lock(&priv->mutex);
  571. iwl_send_statistics_request(priv);
  572. mutex_unlock(&priv->mutex);
  573. }
  574. #define CT_LIMIT_CONST 259
  575. #define TM_CT_KILL_THRESHOLD 110
  576. void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  577. {
  578. struct iwl_ct_kill_config cmd;
  579. u32 R1, R2, R3;
  580. u32 temp_th;
  581. u32 crit_temperature;
  582. unsigned long flags;
  583. int rc = 0;
  584. spin_lock_irqsave(&priv->lock, flags);
  585. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  586. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  587. spin_unlock_irqrestore(&priv->lock, flags);
  588. if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
  589. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  590. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  591. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  592. } else {
  593. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  594. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  595. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  596. }
  597. temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
  598. crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
  599. cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
  600. rc = iwl_send_cmd_pdu(priv,
  601. REPLY_CT_KILL_CONFIG_CMD, sizeof(cmd), &cmd);
  602. if (rc)
  603. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  604. else
  605. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
  606. }
  607. #ifdef CONFIG_IWLWIFI_SENSITIVITY
  608. /* "false alarms" are signals that our DSP tries to lock onto,
  609. * but then determines that they are either noise, or transmissions
  610. * from a distant wireless network (also "noise", really) that get
  611. * "stepped on" by stronger transmissions within our own network.
  612. * This algorithm attempts to set a sensitivity level that is high
  613. * enough to receive all of our own network traffic, but not so
  614. * high that our DSP gets too busy trying to lock onto non-network
  615. * activity/noise. */
  616. static int iwl4965_sens_energy_cck(struct iwl_priv *priv,
  617. u32 norm_fa,
  618. u32 rx_enable_time,
  619. struct statistics_general_data *rx_info)
  620. {
  621. u32 max_nrg_cck = 0;
  622. int i = 0;
  623. u8 max_silence_rssi = 0;
  624. u32 silence_ref = 0;
  625. u8 silence_rssi_a = 0;
  626. u8 silence_rssi_b = 0;
  627. u8 silence_rssi_c = 0;
  628. u32 val;
  629. /* "false_alarms" values below are cross-multiplications to assess the
  630. * numbers of false alarms within the measured period of actual Rx
  631. * (Rx is off when we're txing), vs the min/max expected false alarms
  632. * (some should be expected if rx is sensitive enough) in a
  633. * hypothetical listening period of 200 time units (TU), 204.8 msec:
  634. *
  635. * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
  636. *
  637. * */
  638. u32 false_alarms = norm_fa * 200 * 1024;
  639. u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
  640. u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
  641. struct iwl_sensitivity_data *data = NULL;
  642. data = &(priv->sensitivity_data);
  643. data->nrg_auto_corr_silence_diff = 0;
  644. /* Find max silence rssi among all 3 receivers.
  645. * This is background noise, which may include transmissions from other
  646. * networks, measured during silence before our network's beacon */
  647. silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
  648. ALL_BAND_FILTER)>>8);
  649. silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
  650. ALL_BAND_FILTER)>>8);
  651. silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
  652. ALL_BAND_FILTER)>>8);
  653. val = max(silence_rssi_b, silence_rssi_c);
  654. max_silence_rssi = max(silence_rssi_a, (u8) val);
  655. /* Store silence rssi in 20-beacon history table */
  656. data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
  657. data->nrg_silence_idx++;
  658. if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
  659. data->nrg_silence_idx = 0;
  660. /* Find max silence rssi across 20 beacon history */
  661. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
  662. val = data->nrg_silence_rssi[i];
  663. silence_ref = max(silence_ref, val);
  664. }
  665. IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
  666. silence_rssi_a, silence_rssi_b, silence_rssi_c,
  667. silence_ref);
  668. /* Find max rx energy (min value!) among all 3 receivers,
  669. * measured during beacon frame.
  670. * Save it in 10-beacon history table. */
  671. i = data->nrg_energy_idx;
  672. val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
  673. data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
  674. data->nrg_energy_idx++;
  675. if (data->nrg_energy_idx >= 10)
  676. data->nrg_energy_idx = 0;
  677. /* Find min rx energy (max value) across 10 beacon history.
  678. * This is the minimum signal level that we want to receive well.
  679. * Add backoff (margin so we don't miss slightly lower energy frames).
  680. * This establishes an upper bound (min value) for energy threshold. */
  681. max_nrg_cck = data->nrg_value[0];
  682. for (i = 1; i < 10; i++)
  683. max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
  684. max_nrg_cck += 6;
  685. IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
  686. rx_info->beacon_energy_a, rx_info->beacon_energy_b,
  687. rx_info->beacon_energy_c, max_nrg_cck - 6);
  688. /* Count number of consecutive beacons with fewer-than-desired
  689. * false alarms. */
  690. if (false_alarms < min_false_alarms)
  691. data->num_in_cck_no_fa++;
  692. else
  693. data->num_in_cck_no_fa = 0;
  694. IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
  695. data->num_in_cck_no_fa);
  696. /* If we got too many false alarms this time, reduce sensitivity */
  697. if (false_alarms > max_false_alarms) {
  698. IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
  699. false_alarms, max_false_alarms);
  700. IWL_DEBUG_CALIB("... reducing sensitivity\n");
  701. data->nrg_curr_state = IWL_FA_TOO_MANY;
  702. if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
  703. /* Store for "fewer than desired" on later beacon */
  704. data->nrg_silence_ref = silence_ref;
  705. /* increase energy threshold (reduce nrg value)
  706. * to decrease sensitivity */
  707. if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
  708. data->nrg_th_cck = data->nrg_th_cck
  709. - NRG_STEP_CCK;
  710. }
  711. /* increase auto_corr values to decrease sensitivity */
  712. if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
  713. data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
  714. else {
  715. val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
  716. data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
  717. }
  718. val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
  719. data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
  720. /* Else if we got fewer than desired, increase sensitivity */
  721. } else if (false_alarms < min_false_alarms) {
  722. data->nrg_curr_state = IWL_FA_TOO_FEW;
  723. /* Compare silence level with silence level for most recent
  724. * healthy number or too many false alarms */
  725. data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
  726. (s32)silence_ref;
  727. IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
  728. false_alarms, min_false_alarms,
  729. data->nrg_auto_corr_silence_diff);
  730. /* Increase value to increase sensitivity, but only if:
  731. * 1a) previous beacon did *not* have *too many* false alarms
  732. * 1b) AND there's a significant difference in Rx levels
  733. * from a previous beacon with too many, or healthy # FAs
  734. * OR 2) We've seen a lot of beacons (100) with too few
  735. * false alarms */
  736. if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
  737. ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
  738. (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
  739. IWL_DEBUG_CALIB("... increasing sensitivity\n");
  740. /* Increase nrg value to increase sensitivity */
  741. val = data->nrg_th_cck + NRG_STEP_CCK;
  742. data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
  743. /* Decrease auto_corr values to increase sensitivity */
  744. val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
  745. data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
  746. val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
  747. data->auto_corr_cck_mrc =
  748. max((u32)AUTO_CORR_MIN_CCK_MRC, val);
  749. } else
  750. IWL_DEBUG_CALIB("... but not changing sensitivity\n");
  751. /* Else we got a healthy number of false alarms, keep status quo */
  752. } else {
  753. IWL_DEBUG_CALIB(" FA in safe zone\n");
  754. data->nrg_curr_state = IWL_FA_GOOD_RANGE;
  755. /* Store for use in "fewer than desired" with later beacon */
  756. data->nrg_silence_ref = silence_ref;
  757. /* If previous beacon had too many false alarms,
  758. * give it some extra margin by reducing sensitivity again
  759. * (but don't go below measured energy of desired Rx) */
  760. if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
  761. IWL_DEBUG_CALIB("... increasing margin\n");
  762. data->nrg_th_cck -= NRG_MARGIN;
  763. }
  764. }
  765. /* Make sure the energy threshold does not go above the measured
  766. * energy of the desired Rx signals (reduced by backoff margin),
  767. * or else we might start missing Rx frames.
  768. * Lower value is higher energy, so we use max()!
  769. */
  770. data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
  771. IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
  772. data->nrg_prev_state = data->nrg_curr_state;
  773. return 0;
  774. }
  775. static int iwl4965_sens_auto_corr_ofdm(struct iwl_priv *priv,
  776. u32 norm_fa,
  777. u32 rx_enable_time)
  778. {
  779. u32 val;
  780. u32 false_alarms = norm_fa * 200 * 1024;
  781. u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
  782. u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
  783. struct iwl_sensitivity_data *data = NULL;
  784. data = &(priv->sensitivity_data);
  785. /* If we got too many false alarms this time, reduce sensitivity */
  786. if (false_alarms > max_false_alarms) {
  787. IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
  788. false_alarms, max_false_alarms);
  789. val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
  790. data->auto_corr_ofdm =
  791. min((u32)AUTO_CORR_MAX_OFDM, val);
  792. val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
  793. data->auto_corr_ofdm_mrc =
  794. min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
  795. val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
  796. data->auto_corr_ofdm_x1 =
  797. min((u32)AUTO_CORR_MAX_OFDM_X1, val);
  798. val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
  799. data->auto_corr_ofdm_mrc_x1 =
  800. min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
  801. }
  802. /* Else if we got fewer than desired, increase sensitivity */
  803. else if (false_alarms < min_false_alarms) {
  804. IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
  805. false_alarms, min_false_alarms);
  806. val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
  807. data->auto_corr_ofdm =
  808. max((u32)AUTO_CORR_MIN_OFDM, val);
  809. val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
  810. data->auto_corr_ofdm_mrc =
  811. max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
  812. val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
  813. data->auto_corr_ofdm_x1 =
  814. max((u32)AUTO_CORR_MIN_OFDM_X1, val);
  815. val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
  816. data->auto_corr_ofdm_mrc_x1 =
  817. max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
  818. }
  819. else
  820. IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
  821. min_false_alarms, false_alarms, max_false_alarms);
  822. return 0;
  823. }
  824. static int iwl_sensitivity_callback(struct iwl_priv *priv,
  825. struct iwl_cmd *cmd, struct sk_buff *skb)
  826. {
  827. /* We didn't cache the SKB; let the caller free it */
  828. return 1;
  829. }
  830. /* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
  831. static int iwl4965_sensitivity_write(struct iwl_priv *priv, u8 flags)
  832. {
  833. int rc = 0;
  834. struct iwl_sensitivity_cmd cmd ;
  835. struct iwl_sensitivity_data *data = NULL;
  836. struct iwl_host_cmd cmd_out = {
  837. .id = SENSITIVITY_CMD,
  838. .len = sizeof(struct iwl_sensitivity_cmd),
  839. .meta.flags = flags,
  840. .data = &cmd,
  841. };
  842. data = &(priv->sensitivity_data);
  843. memset(&cmd, 0, sizeof(cmd));
  844. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
  845. cpu_to_le16((u16)data->auto_corr_ofdm);
  846. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
  847. cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
  848. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
  849. cpu_to_le16((u16)data->auto_corr_ofdm_x1);
  850. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
  851. cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
  852. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
  853. cpu_to_le16((u16)data->auto_corr_cck);
  854. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
  855. cpu_to_le16((u16)data->auto_corr_cck_mrc);
  856. cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
  857. cpu_to_le16((u16)data->nrg_th_cck);
  858. cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
  859. cpu_to_le16((u16)data->nrg_th_ofdm);
  860. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
  861. __constant_cpu_to_le16(190);
  862. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
  863. __constant_cpu_to_le16(390);
  864. cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
  865. __constant_cpu_to_le16(62);
  866. IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
  867. data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
  868. data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
  869. data->nrg_th_ofdm);
  870. IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
  871. data->auto_corr_cck, data->auto_corr_cck_mrc,
  872. data->nrg_th_cck);
  873. cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
  874. if (flags & CMD_ASYNC)
  875. cmd_out.meta.u.callback = iwl_sensitivity_callback;
  876. /* Don't send command to uCode if nothing has changed */
  877. if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
  878. sizeof(u16)*HD_TABLE_SIZE)) {
  879. IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
  880. return 0;
  881. }
  882. /* Copy table for comparison next time */
  883. memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
  884. sizeof(u16)*HD_TABLE_SIZE);
  885. rc = iwl_send_cmd(priv, &cmd_out);
  886. if (!rc) {
  887. IWL_DEBUG_CALIB("SENSITIVITY_CMD succeeded\n");
  888. return rc;
  889. }
  890. return 0;
  891. }
  892. void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, u8 force)
  893. {
  894. int rc = 0;
  895. int i;
  896. struct iwl_sensitivity_data *data = NULL;
  897. IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
  898. if (force)
  899. memset(&(priv->sensitivity_tbl[0]), 0,
  900. sizeof(u16)*HD_TABLE_SIZE);
  901. /* Clear driver's sensitivity algo data */
  902. data = &(priv->sensitivity_data);
  903. memset(data, 0, sizeof(struct iwl_sensitivity_data));
  904. data->num_in_cck_no_fa = 0;
  905. data->nrg_curr_state = IWL_FA_TOO_MANY;
  906. data->nrg_prev_state = IWL_FA_TOO_MANY;
  907. data->nrg_silence_ref = 0;
  908. data->nrg_silence_idx = 0;
  909. data->nrg_energy_idx = 0;
  910. for (i = 0; i < 10; i++)
  911. data->nrg_value[i] = 0;
  912. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
  913. data->nrg_silence_rssi[i] = 0;
  914. data->auto_corr_ofdm = 90;
  915. data->auto_corr_ofdm_mrc = 170;
  916. data->auto_corr_ofdm_x1 = 105;
  917. data->auto_corr_ofdm_mrc_x1 = 220;
  918. data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
  919. data->auto_corr_cck_mrc = 200;
  920. data->nrg_th_cck = 100;
  921. data->nrg_th_ofdm = 100;
  922. data->last_bad_plcp_cnt_ofdm = 0;
  923. data->last_fa_cnt_ofdm = 0;
  924. data->last_bad_plcp_cnt_cck = 0;
  925. data->last_fa_cnt_cck = 0;
  926. /* Clear prior Sensitivity command data to force send to uCode */
  927. if (force)
  928. memset(&(priv->sensitivity_tbl[0]), 0,
  929. sizeof(u16)*HD_TABLE_SIZE);
  930. rc |= iwl4965_sensitivity_write(priv, flags);
  931. IWL_DEBUG_CALIB("<<return 0x%X\n", rc);
  932. return;
  933. }
  934. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  935. * Called after every association, but this runs only once!
  936. * ... once chain noise is calibrated the first time, it's good forever. */
  937. void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  938. {
  939. struct iwl_chain_noise_data *data = NULL;
  940. int rc = 0;
  941. data = &(priv->chain_noise_data);
  942. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  943. struct iwl_calibration_cmd cmd;
  944. memset(&cmd, 0, sizeof(cmd));
  945. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  946. cmd.diff_gain_a = 0;
  947. cmd.diff_gain_b = 0;
  948. cmd.diff_gain_c = 0;
  949. rc = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  950. sizeof(cmd), &cmd);
  951. msleep(4);
  952. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  953. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  954. }
  955. return;
  956. }
  957. /*
  958. * Accumulate 20 beacons of signal and noise statistics for each of
  959. * 3 receivers/antennas/rx-chains, then figure out:
  960. * 1) Which antennas are connected.
  961. * 2) Differential rx gain settings to balance the 3 receivers.
  962. */
  963. static void iwl4965_noise_calibration(struct iwl_priv *priv,
  964. struct iwl_notif_statistics *stat_resp)
  965. {
  966. struct iwl_chain_noise_data *data = NULL;
  967. int rc = 0;
  968. u32 chain_noise_a;
  969. u32 chain_noise_b;
  970. u32 chain_noise_c;
  971. u32 chain_sig_a;
  972. u32 chain_sig_b;
  973. u32 chain_sig_c;
  974. u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  975. u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  976. u32 max_average_sig;
  977. u16 max_average_sig_antenna_i;
  978. u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
  979. u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
  980. u16 i = 0;
  981. u16 chan_num = INITIALIZATION_VALUE;
  982. u32 band = INITIALIZATION_VALUE;
  983. u32 active_chains = 0;
  984. unsigned long flags;
  985. struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
  986. data = &(priv->chain_noise_data);
  987. /* Accumulate just the first 20 beacons after the first association,
  988. * then we're done forever. */
  989. if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
  990. if (data->state == IWL_CHAIN_NOISE_ALIVE)
  991. IWL_DEBUG_CALIB("Wait for noise calib reset\n");
  992. return;
  993. }
  994. spin_lock_irqsave(&priv->lock, flags);
  995. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  996. IWL_DEBUG_CALIB(" << Interference data unavailable\n");
  997. spin_unlock_irqrestore(&priv->lock, flags);
  998. return;
  999. }
  1000. band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
  1001. chan_num = le16_to_cpu(priv->staging_rxon.channel);
  1002. /* Make sure we accumulate data for just the associated channel
  1003. * (even if scanning). */
  1004. if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
  1005. ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
  1006. (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
  1007. IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
  1008. chan_num, band);
  1009. spin_unlock_irqrestore(&priv->lock, flags);
  1010. return;
  1011. }
  1012. /* Accumulate beacon statistics values across 20 beacons */
  1013. chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
  1014. IN_BAND_FILTER;
  1015. chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
  1016. IN_BAND_FILTER;
  1017. chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
  1018. IN_BAND_FILTER;
  1019. chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
  1020. chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
  1021. chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
  1022. spin_unlock_irqrestore(&priv->lock, flags);
  1023. data->beacon_count++;
  1024. data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
  1025. data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
  1026. data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
  1027. data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
  1028. data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
  1029. data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
  1030. IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
  1031. data->beacon_count);
  1032. IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
  1033. chain_sig_a, chain_sig_b, chain_sig_c);
  1034. IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
  1035. chain_noise_a, chain_noise_b, chain_noise_c);
  1036. /* If this is the 20th beacon, determine:
  1037. * 1) Disconnected antennas (using signal strengths)
  1038. * 2) Differential gain (using silence noise) to balance receivers */
  1039. if (data->beacon_count == CAL_NUM_OF_BEACONS) {
  1040. /* Analyze signal for disconnected antenna */
  1041. average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
  1042. average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
  1043. average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
  1044. if (average_sig[0] >= average_sig[1]) {
  1045. max_average_sig = average_sig[0];
  1046. max_average_sig_antenna_i = 0;
  1047. active_chains = (1 << max_average_sig_antenna_i);
  1048. } else {
  1049. max_average_sig = average_sig[1];
  1050. max_average_sig_antenna_i = 1;
  1051. active_chains = (1 << max_average_sig_antenna_i);
  1052. }
  1053. if (average_sig[2] >= max_average_sig) {
  1054. max_average_sig = average_sig[2];
  1055. max_average_sig_antenna_i = 2;
  1056. active_chains = (1 << max_average_sig_antenna_i);
  1057. }
  1058. IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
  1059. average_sig[0], average_sig[1], average_sig[2]);
  1060. IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
  1061. max_average_sig, max_average_sig_antenna_i);
  1062. /* Compare signal strengths for all 3 receivers. */
  1063. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1064. if (i != max_average_sig_antenna_i) {
  1065. s32 rssi_delta = (max_average_sig -
  1066. average_sig[i]);
  1067. /* If signal is very weak, compared with
  1068. * strongest, mark it as disconnected. */
  1069. if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
  1070. data->disconn_array[i] = 1;
  1071. else
  1072. active_chains |= (1 << i);
  1073. IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
  1074. "disconn_array[i] = %d\n",
  1075. i, rssi_delta, data->disconn_array[i]);
  1076. }
  1077. }
  1078. /*If both chains A & B are disconnected -
  1079. * connect B and leave A as is */
  1080. if (data->disconn_array[CHAIN_A] &&
  1081. data->disconn_array[CHAIN_B]) {
  1082. data->disconn_array[CHAIN_B] = 0;
  1083. active_chains |= (1 << CHAIN_B);
  1084. IWL_DEBUG_CALIB("both A & B chains are disconnected! "
  1085. "W/A - declare B as connected\n");
  1086. }
  1087. IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
  1088. active_chains);
  1089. /* Save for use within RXON, TX, SCAN commands, etc. */
  1090. priv->valid_antenna = active_chains;
  1091. /* Analyze noise for rx balance */
  1092. average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
  1093. average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
  1094. average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
  1095. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1096. if (!(data->disconn_array[i]) &&
  1097. (average_noise[i] <= min_average_noise)) {
  1098. /* This means that chain i is active and has
  1099. * lower noise values so far: */
  1100. min_average_noise = average_noise[i];
  1101. min_average_noise_antenna_i = i;
  1102. }
  1103. }
  1104. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  1105. IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
  1106. average_noise[0], average_noise[1],
  1107. average_noise[2]);
  1108. IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
  1109. min_average_noise, min_average_noise_antenna_i);
  1110. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1111. s32 delta_g = 0;
  1112. if (!(data->disconn_array[i]) &&
  1113. (data->delta_gain_code[i] ==
  1114. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  1115. delta_g = average_noise[i] - min_average_noise;
  1116. data->delta_gain_code[i] = (u8)((delta_g *
  1117. 10) / 15);
  1118. if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
  1119. data->delta_gain_code[i])
  1120. data->delta_gain_code[i] =
  1121. CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
  1122. data->delta_gain_code[i] =
  1123. (data->delta_gain_code[i] | (1 << 2));
  1124. } else
  1125. data->delta_gain_code[i] = 0;
  1126. }
  1127. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  1128. data->delta_gain_code[0],
  1129. data->delta_gain_code[1],
  1130. data->delta_gain_code[2]);
  1131. /* Differential gain gets sent to uCode only once */
  1132. if (!data->radio_write) {
  1133. struct iwl_calibration_cmd cmd;
  1134. data->radio_write = 1;
  1135. memset(&cmd, 0, sizeof(cmd));
  1136. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  1137. cmd.diff_gain_a = data->delta_gain_code[0];
  1138. cmd.diff_gain_b = data->delta_gain_code[1];
  1139. cmd.diff_gain_c = data->delta_gain_code[2];
  1140. rc = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  1141. sizeof(cmd), &cmd);
  1142. if (rc)
  1143. IWL_DEBUG_CALIB("fail sending cmd "
  1144. "REPLY_PHY_CALIBRATION_CMD \n");
  1145. /* TODO we might want recalculate
  1146. * rx_chain in rxon cmd */
  1147. /* Mark so we run this algo only once! */
  1148. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  1149. }
  1150. data->chain_noise_a = 0;
  1151. data->chain_noise_b = 0;
  1152. data->chain_noise_c = 0;
  1153. data->chain_signal_a = 0;
  1154. data->chain_signal_b = 0;
  1155. data->chain_signal_c = 0;
  1156. data->beacon_count = 0;
  1157. }
  1158. return;
  1159. }
  1160. static void iwl4965_sensitivity_calibration(struct iwl_priv *priv,
  1161. struct iwl_notif_statistics *resp)
  1162. {
  1163. int rc = 0;
  1164. u32 rx_enable_time;
  1165. u32 fa_cck;
  1166. u32 fa_ofdm;
  1167. u32 bad_plcp_cck;
  1168. u32 bad_plcp_ofdm;
  1169. u32 norm_fa_ofdm;
  1170. u32 norm_fa_cck;
  1171. struct iwl_sensitivity_data *data = NULL;
  1172. struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
  1173. struct statistics_rx *statistics = &(resp->rx);
  1174. unsigned long flags;
  1175. struct statistics_general_data statis;
  1176. data = &(priv->sensitivity_data);
  1177. if (!iwl_is_associated(priv)) {
  1178. IWL_DEBUG_CALIB("<< - not associated\n");
  1179. return;
  1180. }
  1181. spin_lock_irqsave(&priv->lock, flags);
  1182. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  1183. IWL_DEBUG_CALIB("<< invalid data.\n");
  1184. spin_unlock_irqrestore(&priv->lock, flags);
  1185. return;
  1186. }
  1187. /* Extract Statistics: */
  1188. rx_enable_time = le32_to_cpu(rx_info->channel_load);
  1189. fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
  1190. fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
  1191. bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
  1192. bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
  1193. statis.beacon_silence_rssi_a =
  1194. le32_to_cpu(statistics->general.beacon_silence_rssi_a);
  1195. statis.beacon_silence_rssi_b =
  1196. le32_to_cpu(statistics->general.beacon_silence_rssi_b);
  1197. statis.beacon_silence_rssi_c =
  1198. le32_to_cpu(statistics->general.beacon_silence_rssi_c);
  1199. statis.beacon_energy_a =
  1200. le32_to_cpu(statistics->general.beacon_energy_a);
  1201. statis.beacon_energy_b =
  1202. le32_to_cpu(statistics->general.beacon_energy_b);
  1203. statis.beacon_energy_c =
  1204. le32_to_cpu(statistics->general.beacon_energy_c);
  1205. spin_unlock_irqrestore(&priv->lock, flags);
  1206. IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
  1207. if (!rx_enable_time) {
  1208. IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
  1209. return;
  1210. }
  1211. /* These statistics increase monotonically, and do not reset
  1212. * at each beacon. Calculate difference from last value, or just
  1213. * use the new statistics value if it has reset or wrapped around. */
  1214. if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
  1215. data->last_bad_plcp_cnt_cck = bad_plcp_cck;
  1216. else {
  1217. bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
  1218. data->last_bad_plcp_cnt_cck += bad_plcp_cck;
  1219. }
  1220. if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
  1221. data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
  1222. else {
  1223. bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
  1224. data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
  1225. }
  1226. if (data->last_fa_cnt_ofdm > fa_ofdm)
  1227. data->last_fa_cnt_ofdm = fa_ofdm;
  1228. else {
  1229. fa_ofdm -= data->last_fa_cnt_ofdm;
  1230. data->last_fa_cnt_ofdm += fa_ofdm;
  1231. }
  1232. if (data->last_fa_cnt_cck > fa_cck)
  1233. data->last_fa_cnt_cck = fa_cck;
  1234. else {
  1235. fa_cck -= data->last_fa_cnt_cck;
  1236. data->last_fa_cnt_cck += fa_cck;
  1237. }
  1238. /* Total aborted signal locks */
  1239. norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
  1240. norm_fa_cck = fa_cck + bad_plcp_cck;
  1241. IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
  1242. bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
  1243. iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
  1244. iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
  1245. rc |= iwl4965_sensitivity_write(priv, CMD_ASYNC);
  1246. return;
  1247. }
  1248. static void iwl4965_bg_sensitivity_work(struct work_struct *work)
  1249. {
  1250. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1251. sensitivity_work);
  1252. mutex_lock(&priv->mutex);
  1253. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1254. test_bit(STATUS_SCANNING, &priv->status)) {
  1255. mutex_unlock(&priv->mutex);
  1256. return;
  1257. }
  1258. if (priv->start_calib) {
  1259. iwl4965_noise_calibration(priv, &priv->statistics);
  1260. if (priv->sensitivity_data.state ==
  1261. IWL_SENS_CALIB_NEED_REINIT) {
  1262. iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
  1263. priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
  1264. } else
  1265. iwl4965_sensitivity_calibration(priv,
  1266. &priv->statistics);
  1267. }
  1268. mutex_unlock(&priv->mutex);
  1269. return;
  1270. }
  1271. #endif /*CONFIG_IWLWIFI_SENSITIVITY*/
  1272. static void iwl4965_bg_txpower_work(struct work_struct *work)
  1273. {
  1274. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1275. txpower_work);
  1276. /* If a scan happened to start before we got here
  1277. * then just return; the statistics notification will
  1278. * kick off another scheduled work to compensate for
  1279. * any temperature delta we missed here. */
  1280. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1281. test_bit(STATUS_SCANNING, &priv->status))
  1282. return;
  1283. mutex_lock(&priv->mutex);
  1284. /* Regardless of if we are assocaited, we must reconfigure the
  1285. * TX power since frames can be sent on non-radar channels while
  1286. * not associated */
  1287. iwl_hw_reg_send_txpower(priv);
  1288. /* Update last_temperature to keep is_calib_needed from running
  1289. * when it isn't needed... */
  1290. priv->last_temperature = priv->temperature;
  1291. mutex_unlock(&priv->mutex);
  1292. }
  1293. /*
  1294. * Acquire priv->lock before calling this function !
  1295. */
  1296. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  1297. {
  1298. iwl_write_restricted(priv, HBUS_TARG_WRPTR,
  1299. (index & 0xff) | (txq_id << 8));
  1300. iwl_write_restricted_reg(priv, SCD_QUEUE_RDPTR(txq_id), index);
  1301. }
  1302. /*
  1303. * Acquire priv->lock before calling this function !
  1304. */
  1305. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  1306. struct iwl_tx_queue *txq,
  1307. int tx_fifo_id, int scd_retry)
  1308. {
  1309. int txq_id = txq->q.id;
  1310. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  1311. iwl_write_restricted_reg(priv, SCD_QUEUE_STATUS_BITS(txq_id),
  1312. (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  1313. (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
  1314. (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
  1315. (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  1316. SCD_QUEUE_STTS_REG_MSK);
  1317. txq->sched_retry = scd_retry;
  1318. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  1319. active ? "Activete" : "Deactivate",
  1320. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  1321. }
  1322. static const u16 default_queue_to_tx_fifo[] = {
  1323. IWL_TX_FIFO_AC3,
  1324. IWL_TX_FIFO_AC2,
  1325. IWL_TX_FIFO_AC1,
  1326. IWL_TX_FIFO_AC0,
  1327. IWL_CMD_FIFO_NUM,
  1328. IWL_TX_FIFO_HCCA_1,
  1329. IWL_TX_FIFO_HCCA_2
  1330. };
  1331. static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
  1332. {
  1333. set_bit(txq_id, &priv->txq_ctx_active_msk);
  1334. }
  1335. static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
  1336. {
  1337. clear_bit(txq_id, &priv->txq_ctx_active_msk);
  1338. }
  1339. int iwl4965_alive_notify(struct iwl_priv *priv)
  1340. {
  1341. u32 a;
  1342. int i = 0;
  1343. unsigned long flags;
  1344. int rc;
  1345. spin_lock_irqsave(&priv->lock, flags);
  1346. #ifdef CONFIG_IWLWIFI_SENSITIVITY
  1347. memset(&(priv->sensitivity_data), 0,
  1348. sizeof(struct iwl_sensitivity_data));
  1349. memset(&(priv->chain_noise_data), 0,
  1350. sizeof(struct iwl_chain_noise_data));
  1351. for (i = 0; i < NUM_RX_CHAINS; i++)
  1352. priv->chain_noise_data.delta_gain_code[i] =
  1353. CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
  1354. #endif /* CONFIG_IWLWIFI_SENSITIVITY*/
  1355. rc = iwl_grab_restricted_access(priv);
  1356. if (rc) {
  1357. spin_unlock_irqrestore(&priv->lock, flags);
  1358. return rc;
  1359. }
  1360. priv->scd_base_addr = iwl_read_restricted_reg(priv, SCD_SRAM_BASE_ADDR);
  1361. a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
  1362. for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  1363. iwl_write_restricted_mem(priv, a, 0);
  1364. for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
  1365. iwl_write_restricted_mem(priv, a, 0);
  1366. for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
  1367. iwl_write_restricted_mem(priv, a, 0);
  1368. iwl_write_restricted_reg(priv, SCD_DRAM_BASE_ADDR,
  1369. (priv->hw_setting.shared_phys +
  1370. offsetof(struct iwl_shared, queues_byte_cnt_tbls)) >> 10);
  1371. iwl_write_restricted_reg(priv, SCD_QUEUECHAIN_SEL, 0);
  1372. /* initiate the queues */
  1373. for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
  1374. iwl_write_restricted_reg(priv, SCD_QUEUE_RDPTR(i), 0);
  1375. iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  1376. iwl_write_restricted_mem(priv, priv->scd_base_addr +
  1377. SCD_CONTEXT_QUEUE_OFFSET(i),
  1378. (SCD_WIN_SIZE <<
  1379. SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  1380. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  1381. iwl_write_restricted_mem(priv, priv->scd_base_addr +
  1382. SCD_CONTEXT_QUEUE_OFFSET(i) +
  1383. sizeof(u32),
  1384. (SCD_FRAME_LIMIT <<
  1385. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  1386. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  1387. }
  1388. iwl_write_restricted_reg(priv, SCD_INTERRUPT_MASK,
  1389. (1 << priv->hw_setting.max_txq_num) - 1);
  1390. iwl_write_restricted_reg(priv, SCD_TXFACT,
  1391. SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
  1392. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  1393. /* map qos queues to fifos one-to-one */
  1394. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  1395. int ac = default_queue_to_tx_fifo[i];
  1396. iwl4965_txq_ctx_activate(priv, i);
  1397. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  1398. }
  1399. iwl_release_restricted_access(priv);
  1400. spin_unlock_irqrestore(&priv->lock, flags);
  1401. return 0;
  1402. }
  1403. int iwl_hw_set_hw_setting(struct iwl_priv *priv)
  1404. {
  1405. priv->hw_setting.shared_virt =
  1406. pci_alloc_consistent(priv->pci_dev,
  1407. sizeof(struct iwl_shared),
  1408. &priv->hw_setting.shared_phys);
  1409. if (!priv->hw_setting.shared_virt)
  1410. return -1;
  1411. memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl_shared));
  1412. priv->hw_setting.max_txq_num = iwl_param_queues_num;
  1413. priv->hw_setting.ac_queue_count = AC_NUM;
  1414. priv->hw_setting.cck_flag = RATE_MCS_CCK_MSK;
  1415. priv->hw_setting.tx_cmd_len = sizeof(struct iwl_tx_cmd);
  1416. priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
  1417. priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1418. priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
  1419. priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
  1420. return 0;
  1421. }
  1422. /**
  1423. * iwl_hw_txq_ctx_free - Free TXQ Context
  1424. *
  1425. * Destroy all TX DMA queues and structures
  1426. */
  1427. void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
  1428. {
  1429. int txq_id;
  1430. /* Tx queues */
  1431. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  1432. iwl_tx_queue_free(priv, &priv->txq[txq_id]);
  1433. iwl4965_kw_free(priv);
  1434. }
  1435. /**
  1436. * iwl_hw_txq_free_tfd - Free one TFD, those at index [txq->q.last_used]
  1437. *
  1438. * Does NOT advance any indexes
  1439. */
  1440. int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  1441. {
  1442. struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
  1443. struct iwl_tfd_frame *bd = &bd_tmp[txq->q.last_used];
  1444. struct pci_dev *dev = priv->pci_dev;
  1445. int i;
  1446. int counter = 0;
  1447. int index, is_odd;
  1448. /* classify bd */
  1449. if (txq->q.id == IWL_CMD_QUEUE_NUM)
  1450. /* nothing to cleanup after for host commands */
  1451. return 0;
  1452. /* sanity check */
  1453. counter = IWL_GET_BITS(*bd, num_tbs);
  1454. if (counter > MAX_NUM_OF_TBS) {
  1455. IWL_ERROR("Too many chunks: %i\n", counter);
  1456. /* @todo issue fatal error, it is quite serious situation */
  1457. return 0;
  1458. }
  1459. /* unmap chunks if any */
  1460. for (i = 0; i < counter; i++) {
  1461. index = i / 2;
  1462. is_odd = i & 0x1;
  1463. if (is_odd)
  1464. pci_unmap_single(
  1465. dev,
  1466. IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
  1467. (IWL_GET_BITS(bd->pa[index],
  1468. tb2_addr_hi20) << 16),
  1469. IWL_GET_BITS(bd->pa[index], tb2_len),
  1470. PCI_DMA_TODEVICE);
  1471. else if (i > 0)
  1472. pci_unmap_single(dev,
  1473. le32_to_cpu(bd->pa[index].tb1_addr),
  1474. IWL_GET_BITS(bd->pa[index], tb1_len),
  1475. PCI_DMA_TODEVICE);
  1476. if (txq->txb[txq->q.last_used].skb[i]) {
  1477. struct sk_buff *skb = txq->txb[txq->q.last_used].skb[i];
  1478. dev_kfree_skb(skb);
  1479. txq->txb[txq->q.last_used].skb[i] = NULL;
  1480. }
  1481. }
  1482. return 0;
  1483. }
  1484. int iwl_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
  1485. {
  1486. IWL_ERROR("TODO: Implement iwl_hw_reg_set_txpower!\n");
  1487. return -EINVAL;
  1488. }
  1489. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  1490. {
  1491. s32 sign = 1;
  1492. if (num < 0) {
  1493. sign = -sign;
  1494. num = -num;
  1495. }
  1496. if (denom < 0) {
  1497. sign = -sign;
  1498. denom = -denom;
  1499. }
  1500. *res = 1;
  1501. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  1502. return 1;
  1503. }
  1504. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  1505. s32 current_voltage)
  1506. {
  1507. s32 comp = 0;
  1508. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  1509. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  1510. return 0;
  1511. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  1512. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  1513. if (current_voltage > eeprom_voltage)
  1514. comp *= 2;
  1515. if ((comp < -2) || (comp > 2))
  1516. comp = 0;
  1517. return comp;
  1518. }
  1519. static const struct iwl_channel_info *
  1520. iwl4965_get_channel_txpower_info(struct iwl_priv *priv, u8 phymode, u16 channel)
  1521. {
  1522. const struct iwl_channel_info *ch_info;
  1523. ch_info = iwl_get_channel_info(priv, phymode, channel);
  1524. if (!is_channel_valid(ch_info))
  1525. return NULL;
  1526. return ch_info;
  1527. }
  1528. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  1529. {
  1530. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  1531. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  1532. return CALIB_CH_GROUP_5;
  1533. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  1534. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  1535. return CALIB_CH_GROUP_1;
  1536. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  1537. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  1538. return CALIB_CH_GROUP_2;
  1539. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  1540. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  1541. return CALIB_CH_GROUP_3;
  1542. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  1543. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  1544. return CALIB_CH_GROUP_4;
  1545. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  1546. return -1;
  1547. }
  1548. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  1549. {
  1550. s32 b = -1;
  1551. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  1552. if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
  1553. continue;
  1554. if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
  1555. && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
  1556. break;
  1557. }
  1558. return b;
  1559. }
  1560. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  1561. {
  1562. s32 val;
  1563. if (x2 == x1)
  1564. return y1;
  1565. else {
  1566. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  1567. return val + y2;
  1568. }
  1569. }
  1570. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  1571. struct iwl_eeprom_calib_ch_info *chan_info)
  1572. {
  1573. s32 s = -1;
  1574. u32 c;
  1575. u32 m;
  1576. const struct iwl_eeprom_calib_measure *m1;
  1577. const struct iwl_eeprom_calib_measure *m2;
  1578. struct iwl_eeprom_calib_measure *omeas;
  1579. u32 ch_i1;
  1580. u32 ch_i2;
  1581. s = iwl4965_get_sub_band(priv, channel);
  1582. if (s >= EEPROM_TX_POWER_BANDS) {
  1583. IWL_ERROR("Tx Power can not find channel %d ", channel);
  1584. return -1;
  1585. }
  1586. ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
  1587. ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
  1588. chan_info->ch_num = (u8) channel;
  1589. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  1590. channel, s, ch_i1, ch_i2);
  1591. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  1592. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  1593. m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
  1594. measurements[c][m]);
  1595. m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
  1596. measurements[c][m]);
  1597. omeas = &(chan_info->measurements[c][m]);
  1598. omeas->actual_pow =
  1599. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1600. m1->actual_pow,
  1601. ch_i2,
  1602. m2->actual_pow);
  1603. omeas->gain_idx =
  1604. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1605. m1->gain_idx, ch_i2,
  1606. m2->gain_idx);
  1607. omeas->temperature =
  1608. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1609. m1->temperature,
  1610. ch_i2,
  1611. m2->temperature);
  1612. omeas->pa_det =
  1613. (s8) iwl4965_interpolate_value(channel, ch_i1,
  1614. m1->pa_det, ch_i2,
  1615. m2->pa_det);
  1616. IWL_DEBUG_TXPOWER
  1617. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  1618. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  1619. IWL_DEBUG_TXPOWER
  1620. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  1621. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  1622. IWL_DEBUG_TXPOWER
  1623. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  1624. m1->pa_det, m2->pa_det, omeas->pa_det);
  1625. IWL_DEBUG_TXPOWER
  1626. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  1627. m1->temperature, m2->temperature,
  1628. omeas->temperature);
  1629. }
  1630. }
  1631. return 0;
  1632. }
  1633. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  1634. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  1635. static s32 back_off_table[] = {
  1636. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  1637. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  1638. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  1639. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  1640. 10 /* CCK */
  1641. };
  1642. /* Thermal compensation values for txpower for various frequency ranges ...
  1643. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  1644. static struct iwl_txpower_comp_entry {
  1645. s32 degrees_per_05db_a;
  1646. s32 degrees_per_05db_a_denom;
  1647. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  1648. {9, 2}, /* group 0 5.2, ch 34-43 */
  1649. {4, 1}, /* group 1 5.2, ch 44-70 */
  1650. {4, 1}, /* group 2 5.2, ch 71-124 */
  1651. {4, 1}, /* group 3 5.2, ch 125-200 */
  1652. {3, 1} /* group 4 2.4, ch all */
  1653. };
  1654. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  1655. {
  1656. if (!band) {
  1657. if ((rate_power_index & 7) <= 4)
  1658. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  1659. }
  1660. return MIN_TX_GAIN_INDEX;
  1661. }
  1662. struct gain_entry {
  1663. u8 dsp;
  1664. u8 radio;
  1665. };
  1666. static const struct gain_entry gain_table[2][108] = {
  1667. /* 5.2GHz power gain index table */
  1668. {
  1669. {123, 0x3F}, /* highest txpower */
  1670. {117, 0x3F},
  1671. {110, 0x3F},
  1672. {104, 0x3F},
  1673. {98, 0x3F},
  1674. {110, 0x3E},
  1675. {104, 0x3E},
  1676. {98, 0x3E},
  1677. {110, 0x3D},
  1678. {104, 0x3D},
  1679. {98, 0x3D},
  1680. {110, 0x3C},
  1681. {104, 0x3C},
  1682. {98, 0x3C},
  1683. {110, 0x3B},
  1684. {104, 0x3B},
  1685. {98, 0x3B},
  1686. {110, 0x3A},
  1687. {104, 0x3A},
  1688. {98, 0x3A},
  1689. {110, 0x39},
  1690. {104, 0x39},
  1691. {98, 0x39},
  1692. {110, 0x38},
  1693. {104, 0x38},
  1694. {98, 0x38},
  1695. {110, 0x37},
  1696. {104, 0x37},
  1697. {98, 0x37},
  1698. {110, 0x36},
  1699. {104, 0x36},
  1700. {98, 0x36},
  1701. {110, 0x35},
  1702. {104, 0x35},
  1703. {98, 0x35},
  1704. {110, 0x34},
  1705. {104, 0x34},
  1706. {98, 0x34},
  1707. {110, 0x33},
  1708. {104, 0x33},
  1709. {98, 0x33},
  1710. {110, 0x32},
  1711. {104, 0x32},
  1712. {98, 0x32},
  1713. {110, 0x31},
  1714. {104, 0x31},
  1715. {98, 0x31},
  1716. {110, 0x30},
  1717. {104, 0x30},
  1718. {98, 0x30},
  1719. {110, 0x25},
  1720. {104, 0x25},
  1721. {98, 0x25},
  1722. {110, 0x24},
  1723. {104, 0x24},
  1724. {98, 0x24},
  1725. {110, 0x23},
  1726. {104, 0x23},
  1727. {98, 0x23},
  1728. {110, 0x22},
  1729. {104, 0x18},
  1730. {98, 0x18},
  1731. {110, 0x17},
  1732. {104, 0x17},
  1733. {98, 0x17},
  1734. {110, 0x16},
  1735. {104, 0x16},
  1736. {98, 0x16},
  1737. {110, 0x15},
  1738. {104, 0x15},
  1739. {98, 0x15},
  1740. {110, 0x14},
  1741. {104, 0x14},
  1742. {98, 0x14},
  1743. {110, 0x13},
  1744. {104, 0x13},
  1745. {98, 0x13},
  1746. {110, 0x12},
  1747. {104, 0x08},
  1748. {98, 0x08},
  1749. {110, 0x07},
  1750. {104, 0x07},
  1751. {98, 0x07},
  1752. {110, 0x06},
  1753. {104, 0x06},
  1754. {98, 0x06},
  1755. {110, 0x05},
  1756. {104, 0x05},
  1757. {98, 0x05},
  1758. {110, 0x04},
  1759. {104, 0x04},
  1760. {98, 0x04},
  1761. {110, 0x03},
  1762. {104, 0x03},
  1763. {98, 0x03},
  1764. {110, 0x02},
  1765. {104, 0x02},
  1766. {98, 0x02},
  1767. {110, 0x01},
  1768. {104, 0x01},
  1769. {98, 0x01},
  1770. {110, 0x00},
  1771. {104, 0x00},
  1772. {98, 0x00},
  1773. {93, 0x00},
  1774. {88, 0x00},
  1775. {83, 0x00},
  1776. {78, 0x00},
  1777. },
  1778. /* 2.4GHz power gain index table */
  1779. {
  1780. {110, 0x3f}, /* highest txpower */
  1781. {104, 0x3f},
  1782. {98, 0x3f},
  1783. {110, 0x3e},
  1784. {104, 0x3e},
  1785. {98, 0x3e},
  1786. {110, 0x3d},
  1787. {104, 0x3d},
  1788. {98, 0x3d},
  1789. {110, 0x3c},
  1790. {104, 0x3c},
  1791. {98, 0x3c},
  1792. {110, 0x3b},
  1793. {104, 0x3b},
  1794. {98, 0x3b},
  1795. {110, 0x3a},
  1796. {104, 0x3a},
  1797. {98, 0x3a},
  1798. {110, 0x39},
  1799. {104, 0x39},
  1800. {98, 0x39},
  1801. {110, 0x38},
  1802. {104, 0x38},
  1803. {98, 0x38},
  1804. {110, 0x37},
  1805. {104, 0x37},
  1806. {98, 0x37},
  1807. {110, 0x36},
  1808. {104, 0x36},
  1809. {98, 0x36},
  1810. {110, 0x35},
  1811. {104, 0x35},
  1812. {98, 0x35},
  1813. {110, 0x34},
  1814. {104, 0x34},
  1815. {98, 0x34},
  1816. {110, 0x33},
  1817. {104, 0x33},
  1818. {98, 0x33},
  1819. {110, 0x32},
  1820. {104, 0x32},
  1821. {98, 0x32},
  1822. {110, 0x31},
  1823. {104, 0x31},
  1824. {98, 0x31},
  1825. {110, 0x30},
  1826. {104, 0x30},
  1827. {98, 0x30},
  1828. {110, 0x6},
  1829. {104, 0x6},
  1830. {98, 0x6},
  1831. {110, 0x5},
  1832. {104, 0x5},
  1833. {98, 0x5},
  1834. {110, 0x4},
  1835. {104, 0x4},
  1836. {98, 0x4},
  1837. {110, 0x3},
  1838. {104, 0x3},
  1839. {98, 0x3},
  1840. {110, 0x2},
  1841. {104, 0x2},
  1842. {98, 0x2},
  1843. {110, 0x1},
  1844. {104, 0x1},
  1845. {98, 0x1},
  1846. {110, 0x0},
  1847. {104, 0x0},
  1848. {98, 0x0},
  1849. {97, 0},
  1850. {96, 0},
  1851. {95, 0},
  1852. {94, 0},
  1853. {93, 0},
  1854. {92, 0},
  1855. {91, 0},
  1856. {90, 0},
  1857. {89, 0},
  1858. {88, 0},
  1859. {87, 0},
  1860. {86, 0},
  1861. {85, 0},
  1862. {84, 0},
  1863. {83, 0},
  1864. {82, 0},
  1865. {81, 0},
  1866. {80, 0},
  1867. {79, 0},
  1868. {78, 0},
  1869. {77, 0},
  1870. {76, 0},
  1871. {75, 0},
  1872. {74, 0},
  1873. {73, 0},
  1874. {72, 0},
  1875. {71, 0},
  1876. {70, 0},
  1877. {69, 0},
  1878. {68, 0},
  1879. {67, 0},
  1880. {66, 0},
  1881. {65, 0},
  1882. {64, 0},
  1883. {63, 0},
  1884. {62, 0},
  1885. {61, 0},
  1886. {60, 0},
  1887. {59, 0},
  1888. }
  1889. };
  1890. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  1891. u8 is_fat, u8 ctrl_chan_high,
  1892. struct iwl_tx_power_db *tx_power_tbl)
  1893. {
  1894. u8 saturation_power;
  1895. s32 target_power;
  1896. s32 user_target_power;
  1897. s32 power_limit;
  1898. s32 current_temp;
  1899. s32 reg_limit;
  1900. s32 current_regulatory;
  1901. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  1902. int i;
  1903. int c;
  1904. const struct iwl_channel_info *ch_info = NULL;
  1905. struct iwl_eeprom_calib_ch_info ch_eeprom_info;
  1906. const struct iwl_eeprom_calib_measure *measurement;
  1907. s16 voltage;
  1908. s32 init_voltage;
  1909. s32 voltage_compensation;
  1910. s32 degrees_per_05db_num;
  1911. s32 degrees_per_05db_denom;
  1912. s32 factory_temp;
  1913. s32 temperature_comp[2];
  1914. s32 factory_gain_index[2];
  1915. s32 factory_actual_pwr[2];
  1916. s32 power_index;
  1917. /* Sanity check requested level (dBm) */
  1918. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  1919. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  1920. priv->user_txpower_limit);
  1921. return -EINVAL;
  1922. }
  1923. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  1924. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  1925. priv->user_txpower_limit);
  1926. return -EINVAL;
  1927. }
  1928. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  1929. * are used for indexing into txpower table) */
  1930. user_target_power = 2 * priv->user_txpower_limit;
  1931. /* Get current (RXON) channel, band, width */
  1932. ch_info =
  1933. iwl4965_get_channel_txpower_info(priv, priv->phymode, channel);
  1934. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  1935. is_fat);
  1936. if (!ch_info)
  1937. return -EINVAL;
  1938. /* get txatten group, used to select 1) thermal txpower adjustment
  1939. * and 2) mimo txpower balance between Tx chains. */
  1940. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  1941. if (txatten_grp < 0)
  1942. return -EINVAL;
  1943. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  1944. channel, txatten_grp);
  1945. if (is_fat) {
  1946. if (ctrl_chan_high)
  1947. channel -= 2;
  1948. else
  1949. channel += 2;
  1950. }
  1951. /* hardware txpower limits ...
  1952. * saturation (clipping distortion) txpowers are in half-dBm */
  1953. if (band)
  1954. saturation_power = priv->eeprom.calib_info.saturation_power24;
  1955. else
  1956. saturation_power = priv->eeprom.calib_info.saturation_power52;
  1957. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  1958. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  1959. if (band)
  1960. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  1961. else
  1962. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  1963. }
  1964. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  1965. * max_power_avg values are in dBm, convert * 2 */
  1966. if (is_fat)
  1967. reg_limit = ch_info->fat_max_power_avg * 2;
  1968. else
  1969. reg_limit = ch_info->max_power_avg * 2;
  1970. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  1971. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  1972. if (band)
  1973. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  1974. else
  1975. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  1976. }
  1977. /* Interpolate txpower calibration values for this channel,
  1978. * based on factory calibration tests on spaced channels. */
  1979. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  1980. /* calculate tx gain adjustment based on power supply voltage */
  1981. voltage = priv->eeprom.calib_info.voltage;
  1982. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  1983. voltage_compensation =
  1984. iwl4965_get_voltage_compensation(voltage, init_voltage);
  1985. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  1986. init_voltage,
  1987. voltage, voltage_compensation);
  1988. /* get current temperature (Celsius) */
  1989. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  1990. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  1991. current_temp = KELVIN_TO_CELSIUS(current_temp);
  1992. /* select thermal txpower adjustment params, based on channel group
  1993. * (same frequency group used for mimo txatten adjustment) */
  1994. degrees_per_05db_num =
  1995. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  1996. degrees_per_05db_denom =
  1997. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  1998. /* get per-chain txpower values from factory measurements */
  1999. for (c = 0; c < 2; c++) {
  2000. measurement = &ch_eeprom_info.measurements[c][1];
  2001. /* txgain adjustment (in half-dB steps) based on difference
  2002. * between factory and current temperature */
  2003. factory_temp = measurement->temperature;
  2004. iwl4965_math_div_round((current_temp - factory_temp) *
  2005. degrees_per_05db_denom,
  2006. degrees_per_05db_num,
  2007. &temperature_comp[c]);
  2008. factory_gain_index[c] = measurement->gain_idx;
  2009. factory_actual_pwr[c] = measurement->actual_pow;
  2010. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  2011. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  2012. "curr tmp %d, comp %d steps\n",
  2013. factory_temp, current_temp,
  2014. temperature_comp[c]);
  2015. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  2016. factory_gain_index[c],
  2017. factory_actual_pwr[c]);
  2018. }
  2019. /* for each of 33 bit-rates (including 1 for CCK) */
  2020. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  2021. u8 is_mimo_rate;
  2022. union iwl_tx_power_dual_stream tx_power;
  2023. /* for mimo, reduce each chain's txpower by half
  2024. * (3dB, 6 steps), so total output power is regulatory
  2025. * compliant. */
  2026. if (i & 0x8) {
  2027. current_regulatory = reg_limit -
  2028. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  2029. is_mimo_rate = 1;
  2030. } else {
  2031. current_regulatory = reg_limit;
  2032. is_mimo_rate = 0;
  2033. }
  2034. /* find txpower limit, either hardware or regulatory */
  2035. power_limit = saturation_power - back_off_table[i];
  2036. if (power_limit > current_regulatory)
  2037. power_limit = current_regulatory;
  2038. /* reduce user's txpower request if necessary
  2039. * for this rate on this channel */
  2040. target_power = user_target_power;
  2041. if (target_power > power_limit)
  2042. target_power = power_limit;
  2043. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  2044. i, saturation_power - back_off_table[i],
  2045. current_regulatory, user_target_power,
  2046. target_power);
  2047. /* for each of 2 Tx chains (radio transmitters) */
  2048. for (c = 0; c < 2; c++) {
  2049. s32 atten_value;
  2050. if (is_mimo_rate)
  2051. atten_value =
  2052. (s32)le32_to_cpu(priv->card_alive_init.
  2053. tx_atten[txatten_grp][c]);
  2054. else
  2055. atten_value = 0;
  2056. /* calculate index; higher index means lower txpower */
  2057. power_index = (u8) (factory_gain_index[c] -
  2058. (target_power -
  2059. factory_actual_pwr[c]) -
  2060. temperature_comp[c] -
  2061. voltage_compensation +
  2062. atten_value);
  2063. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  2064. power_index); */
  2065. if (power_index < get_min_power_index(i, band))
  2066. power_index = get_min_power_index(i, band);
  2067. /* adjust 5 GHz index to support negative indexes */
  2068. if (!band)
  2069. power_index += 9;
  2070. /* CCK, rate 32, reduce txpower for CCK */
  2071. if (i == POWER_TABLE_CCK_ENTRY)
  2072. power_index +=
  2073. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  2074. /* stay within the table! */
  2075. if (power_index > 107) {
  2076. IWL_WARNING("txpower index %d > 107\n",
  2077. power_index);
  2078. power_index = 107;
  2079. }
  2080. if (power_index < 0) {
  2081. IWL_WARNING("txpower index %d < 0\n",
  2082. power_index);
  2083. power_index = 0;
  2084. }
  2085. /* fill txpower command for this rate/chain */
  2086. tx_power.s.radio_tx_gain[c] =
  2087. gain_table[band][power_index].radio;
  2088. tx_power.s.dsp_predis_atten[c] =
  2089. gain_table[band][power_index].dsp;
  2090. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  2091. "gain 0x%02x dsp %d\n",
  2092. c, atten_value, power_index,
  2093. tx_power.s.radio_tx_gain[c],
  2094. tx_power.s.dsp_predis_atten[c]);
  2095. }/* for each chain */
  2096. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  2097. }/* for each rate */
  2098. return 0;
  2099. }
  2100. /**
  2101. * iwl_hw_reg_send_txpower - Configure the TXPOWER level user limit
  2102. *
  2103. * Uses the active RXON for channel, band, and characteristics (fat, high)
  2104. * The power limit is taken from priv->user_txpower_limit.
  2105. */
  2106. int iwl_hw_reg_send_txpower(struct iwl_priv *priv)
  2107. {
  2108. struct iwl_txpowertable_cmd cmd = { 0 };
  2109. int rc = 0;
  2110. u8 band = 0;
  2111. u8 is_fat = 0;
  2112. u8 ctrl_chan_high = 0;
  2113. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2114. /* If this gets hit a lot, switch it to a BUG() and catch
  2115. * the stack trace to find out who is calling this during
  2116. * a scan. */
  2117. IWL_WARNING("TX Power requested while scanning!\n");
  2118. return -EAGAIN;
  2119. }
  2120. band = ((priv->phymode == MODE_IEEE80211B) ||
  2121. (priv->phymode == MODE_IEEE80211G));
  2122. is_fat = is_fat_channel(priv->active_rxon.flags);
  2123. if (is_fat &&
  2124. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2125. ctrl_chan_high = 1;
  2126. cmd.band = band;
  2127. cmd.channel = priv->active_rxon.channel;
  2128. rc = iwl4965_fill_txpower_tbl(priv, band,
  2129. le16_to_cpu(priv->active_rxon.channel),
  2130. is_fat, ctrl_chan_high, &cmd.tx_power);
  2131. if (rc)
  2132. return rc;
  2133. rc = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  2134. return rc;
  2135. }
  2136. int iwl_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  2137. {
  2138. int rc;
  2139. u8 band = 0;
  2140. u8 is_fat = 0;
  2141. u8 ctrl_chan_high = 0;
  2142. struct iwl_channel_switch_cmd cmd = { 0 };
  2143. const struct iwl_channel_info *ch_info;
  2144. band = ((priv->phymode == MODE_IEEE80211B) ||
  2145. (priv->phymode == MODE_IEEE80211G));
  2146. ch_info = iwl_get_channel_info(priv, priv->phymode, channel);
  2147. is_fat = is_fat_channel(priv->staging_rxon.flags);
  2148. if (is_fat &&
  2149. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2150. ctrl_chan_high = 1;
  2151. cmd.band = band;
  2152. cmd.expect_beacon = 0;
  2153. cmd.channel = cpu_to_le16(channel);
  2154. cmd.rxon_flags = priv->active_rxon.flags;
  2155. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  2156. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  2157. if (ch_info)
  2158. cmd.expect_beacon = is_channel_radar(ch_info);
  2159. else
  2160. cmd.expect_beacon = 1;
  2161. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  2162. ctrl_chan_high, &cmd.tx_power);
  2163. if (rc) {
  2164. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  2165. return rc;
  2166. }
  2167. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  2168. return rc;
  2169. }
  2170. #define RTS_HCCA_RETRY_LIMIT 3
  2171. #define RTS_DFAULT_RETRY_LIMIT 60
  2172. void iwl_hw_build_tx_cmd_rate(struct iwl_priv *priv,
  2173. struct iwl_cmd *cmd,
  2174. struct ieee80211_tx_control *ctrl,
  2175. struct ieee80211_hdr *hdr, int sta_id,
  2176. int is_hcca)
  2177. {
  2178. u8 rate;
  2179. u8 rts_retry_limit = 0;
  2180. u8 data_retry_limit = 0;
  2181. __le32 tx_flags;
  2182. u16 fc = le16_to_cpu(hdr->frame_control);
  2183. tx_flags = cmd->cmd.tx.tx_flags;
  2184. rate = iwl_rates[ctrl->tx_rate].plcp;
  2185. rts_retry_limit = (is_hcca) ?
  2186. RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
  2187. if (ieee80211_is_probe_response(fc)) {
  2188. data_retry_limit = 3;
  2189. if (data_retry_limit < rts_retry_limit)
  2190. rts_retry_limit = data_retry_limit;
  2191. } else
  2192. data_retry_limit = IWL_DEFAULT_TX_RETRY;
  2193. if (priv->data_retry_limit != -1)
  2194. data_retry_limit = priv->data_retry_limit;
  2195. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2196. switch (fc & IEEE80211_FCTL_STYPE) {
  2197. case IEEE80211_STYPE_AUTH:
  2198. case IEEE80211_STYPE_DEAUTH:
  2199. case IEEE80211_STYPE_ASSOC_REQ:
  2200. case IEEE80211_STYPE_REASSOC_REQ:
  2201. if (tx_flags & TX_CMD_FLG_RTS_MSK) {
  2202. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2203. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2204. }
  2205. break;
  2206. default:
  2207. break;
  2208. }
  2209. }
  2210. cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
  2211. cmd->cmd.tx.data_retry_limit = data_retry_limit;
  2212. cmd->cmd.tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, 0);
  2213. cmd->cmd.tx.tx_flags = tx_flags;
  2214. }
  2215. int iwl_hw_get_rx_read(struct iwl_priv *priv)
  2216. {
  2217. struct iwl_shared *shared_data = priv->hw_setting.shared_virt;
  2218. return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
  2219. }
  2220. int iwl_hw_get_temperature(struct iwl_priv *priv)
  2221. {
  2222. return priv->temperature;
  2223. }
  2224. unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  2225. struct iwl_frame *frame, u8 rate)
  2226. {
  2227. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  2228. unsigned int frame_size;
  2229. tx_beacon_cmd = &frame->u.beacon;
  2230. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  2231. tx_beacon_cmd->tx.sta_id = IWL4965_BROADCAST_ID;
  2232. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2233. frame_size = iwl_fill_beacon_frame(priv,
  2234. tx_beacon_cmd->frame,
  2235. BROADCAST_ADDR,
  2236. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  2237. BUG_ON(frame_size > MAX_MPDU_SIZE);
  2238. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  2239. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  2240. tx_beacon_cmd->tx.rate_n_flags =
  2241. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  2242. else
  2243. tx_beacon_cmd->tx.rate_n_flags =
  2244. iwl_hw_set_rate_n_flags(rate, 0);
  2245. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  2246. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  2247. return (sizeof(*tx_beacon_cmd) + frame_size);
  2248. }
  2249. int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  2250. {
  2251. int rc;
  2252. unsigned long flags;
  2253. int txq_id = txq->q.id;
  2254. spin_lock_irqsave(&priv->lock, flags);
  2255. rc = iwl_grab_restricted_access(priv);
  2256. if (rc) {
  2257. spin_unlock_irqrestore(&priv->lock, flags);
  2258. return rc;
  2259. }
  2260. iwl_write_restricted(priv, FH_MEM_CBBC_QUEUE(txq_id),
  2261. txq->q.dma_addr >> 8);
  2262. iwl_write_restricted(
  2263. priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
  2264. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  2265. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
  2266. iwl_release_restricted_access(priv);
  2267. spin_unlock_irqrestore(&priv->lock, flags);
  2268. return 0;
  2269. }
  2270. static inline u8 iwl4965_get_dma_hi_address(dma_addr_t addr)
  2271. {
  2272. return sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0;
  2273. }
  2274. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
  2275. dma_addr_t addr, u16 len)
  2276. {
  2277. int index, is_odd;
  2278. struct iwl_tfd_frame *tfd = ptr;
  2279. u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
  2280. if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
  2281. IWL_ERROR("Error can not send more than %d chunks\n",
  2282. MAX_NUM_OF_TBS);
  2283. return -EINVAL;
  2284. }
  2285. index = num_tbs / 2;
  2286. is_odd = num_tbs & 0x1;
  2287. if (!is_odd) {
  2288. tfd->pa[index].tb1_addr = cpu_to_le32(addr);
  2289. IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
  2290. iwl4965_get_dma_hi_address(addr));
  2291. IWL_SET_BITS(tfd->pa[index], tb1_len, len);
  2292. } else {
  2293. IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
  2294. (u32) (addr & 0xffff));
  2295. IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
  2296. IWL_SET_BITS(tfd->pa[index], tb2_len, len);
  2297. }
  2298. IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
  2299. return 0;
  2300. }
  2301. void iwl_hw_card_show_info(struct iwl_priv *priv)
  2302. {
  2303. u16 hw_version = priv->eeprom.board_revision_4965;
  2304. IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
  2305. ((hw_version >> 8) & 0x0F),
  2306. ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
  2307. IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
  2308. priv->eeprom.board_pba_number_4965);
  2309. }
  2310. #define IWL_TX_CRC_SIZE 4
  2311. #define IWL_TX_DELIMITER_SIZE 4
  2312. int iwl4965_tx_queue_update_wr_ptr(struct iwl_priv *priv,
  2313. struct iwl_tx_queue *txq, u16 byte_cnt)
  2314. {
  2315. int len;
  2316. int txq_id = txq->q.id;
  2317. struct iwl_shared *shared_data = priv->hw_setting.shared_virt;
  2318. if (txq->need_update == 0)
  2319. return 0;
  2320. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  2321. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2322. tfd_offset[txq->q.first_empty], byte_cnt, len);
  2323. if (txq->q.first_empty < IWL4965_MAX_WIN_SIZE)
  2324. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2325. tfd_offset[IWL4965_QUEUE_SIZE + txq->q.first_empty],
  2326. byte_cnt, len);
  2327. return 0;
  2328. }
  2329. /* Set up Rx receiver/antenna/chain usage in "staging" RXON image.
  2330. * This should not be used for scan command ... it puts data in wrong place. */
  2331. void iwl4965_set_rxon_chain(struct iwl_priv *priv)
  2332. {
  2333. u8 is_single = is_single_stream(priv);
  2334. u8 idle_state, rx_state;
  2335. priv->staging_rxon.rx_chain = 0;
  2336. rx_state = idle_state = 3;
  2337. /* Tell uCode which antennas are actually connected.
  2338. * Before first association, we assume all antennas are connected.
  2339. * Just after first association, iwl4965_noise_calibration()
  2340. * checks which antennas actually *are* connected. */
  2341. priv->staging_rxon.rx_chain |=
  2342. cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
  2343. /* How many receivers should we use? */
  2344. iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
  2345. priv->staging_rxon.rx_chain |=
  2346. cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
  2347. priv->staging_rxon.rx_chain |=
  2348. cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
  2349. if (!is_single && (rx_state >= 2) &&
  2350. !test_bit(STATUS_POWER_PMI, &priv->status))
  2351. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2352. else
  2353. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2354. IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
  2355. }
  2356. #ifdef CONFIG_IWLWIFI_HT
  2357. #ifdef CONFIG_IWLWIFI_HT_AGG
  2358. /*
  2359. get the traffic load value for tid
  2360. */
  2361. static u32 iwl4965_tl_get_load(struct iwl_priv *priv, u8 tid)
  2362. {
  2363. u32 load = 0;
  2364. u32 current_time = jiffies_to_msecs(jiffies);
  2365. u32 time_diff;
  2366. s32 index;
  2367. unsigned long flags;
  2368. struct iwl_traffic_load *tid_ptr = NULL;
  2369. if (tid >= TID_MAX_LOAD_COUNT)
  2370. return 0;
  2371. tid_ptr = &(priv->lq_mngr.agg_ctrl.traffic_load[tid]);
  2372. current_time -= current_time % TID_ROUND_VALUE;
  2373. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2374. if (!(tid_ptr->queue_count))
  2375. goto out;
  2376. time_diff = TIME_WRAP_AROUND(tid_ptr->time_stamp, current_time);
  2377. index = time_diff / TID_QUEUE_CELL_SPACING;
  2378. if (index >= TID_QUEUE_MAX_SIZE) {
  2379. u32 oldest_time = current_time - TID_MAX_TIME_DIFF;
  2380. while (tid_ptr->queue_count &&
  2381. (tid_ptr->time_stamp < oldest_time)) {
  2382. tid_ptr->total -= tid_ptr->packet_count[tid_ptr->head];
  2383. tid_ptr->packet_count[tid_ptr->head] = 0;
  2384. tid_ptr->time_stamp += TID_QUEUE_CELL_SPACING;
  2385. tid_ptr->queue_count--;
  2386. tid_ptr->head++;
  2387. if (tid_ptr->head >= TID_QUEUE_MAX_SIZE)
  2388. tid_ptr->head = 0;
  2389. }
  2390. }
  2391. load = tid_ptr->total;
  2392. out:
  2393. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2394. return load;
  2395. }
  2396. /*
  2397. increment traffic load value for tid and also remove
  2398. any old values if passed the certian time period
  2399. */
  2400. static void iwl4965_tl_add_packet(struct iwl_priv *priv, u8 tid)
  2401. {
  2402. u32 current_time = jiffies_to_msecs(jiffies);
  2403. u32 time_diff;
  2404. s32 index;
  2405. unsigned long flags;
  2406. struct iwl_traffic_load *tid_ptr = NULL;
  2407. if (tid >= TID_MAX_LOAD_COUNT)
  2408. return;
  2409. tid_ptr = &(priv->lq_mngr.agg_ctrl.traffic_load[tid]);
  2410. current_time -= current_time % TID_ROUND_VALUE;
  2411. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2412. if (!(tid_ptr->queue_count)) {
  2413. tid_ptr->total = 1;
  2414. tid_ptr->time_stamp = current_time;
  2415. tid_ptr->queue_count = 1;
  2416. tid_ptr->head = 0;
  2417. tid_ptr->packet_count[0] = 1;
  2418. goto out;
  2419. }
  2420. time_diff = TIME_WRAP_AROUND(tid_ptr->time_stamp, current_time);
  2421. index = time_diff / TID_QUEUE_CELL_SPACING;
  2422. if (index >= TID_QUEUE_MAX_SIZE) {
  2423. u32 oldest_time = current_time - TID_MAX_TIME_DIFF;
  2424. while (tid_ptr->queue_count &&
  2425. (tid_ptr->time_stamp < oldest_time)) {
  2426. tid_ptr->total -= tid_ptr->packet_count[tid_ptr->head];
  2427. tid_ptr->packet_count[tid_ptr->head] = 0;
  2428. tid_ptr->time_stamp += TID_QUEUE_CELL_SPACING;
  2429. tid_ptr->queue_count--;
  2430. tid_ptr->head++;
  2431. if (tid_ptr->head >= TID_QUEUE_MAX_SIZE)
  2432. tid_ptr->head = 0;
  2433. }
  2434. }
  2435. index = (tid_ptr->head + index) % TID_QUEUE_MAX_SIZE;
  2436. tid_ptr->packet_count[index] = tid_ptr->packet_count[index] + 1;
  2437. tid_ptr->total = tid_ptr->total + 1;
  2438. if ((index + 1) > tid_ptr->queue_count)
  2439. tid_ptr->queue_count = index + 1;
  2440. out:
  2441. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2442. }
  2443. #define MMAC_SCHED_MAX_NUMBER_OF_HT_BACK_FLOWS 7
  2444. enum HT_STATUS {
  2445. BA_STATUS_FAILURE = 0,
  2446. BA_STATUS_INITIATOR_DELBA,
  2447. BA_STATUS_RECIPIENT_DELBA,
  2448. BA_STATUS_RENEW_ADDBA_REQUEST,
  2449. BA_STATUS_ACTIVE,
  2450. };
  2451. static u8 iwl4964_tl_ba_avail(struct iwl_priv *priv)
  2452. {
  2453. int i;
  2454. struct iwl_lq_mngr *lq;
  2455. u8 count = 0;
  2456. u16 msk;
  2457. lq = (struct iwl_lq_mngr *)&(priv->lq_mngr);
  2458. for (i = 0; i < TID_MAX_LOAD_COUNT ; i++) {
  2459. msk = 1 << i;
  2460. if ((lq->agg_ctrl.granted_ba & msk) ||
  2461. (lq->agg_ctrl.wait_for_agg_status & msk))
  2462. count++;
  2463. }
  2464. if (count < MMAC_SCHED_MAX_NUMBER_OF_HT_BACK_FLOWS)
  2465. return 1;
  2466. return 0;
  2467. }
  2468. static void iwl4965_ba_status(struct iwl_priv *priv,
  2469. u8 tid, enum HT_STATUS status);
  2470. static int iwl4965_perform_addba(struct iwl_priv *priv, u8 tid, u32 length,
  2471. u32 ba_timeout)
  2472. {
  2473. int rc;
  2474. rc = ieee80211_start_BA_session(priv->hw, priv->bssid, tid);
  2475. if (rc)
  2476. iwl4965_ba_status(priv, tid, BA_STATUS_FAILURE);
  2477. return rc;
  2478. }
  2479. static int iwl4965_perform_delba(struct iwl_priv *priv, u8 tid)
  2480. {
  2481. int rc;
  2482. rc = ieee80211_stop_BA_session(priv->hw, priv->bssid, tid);
  2483. if (rc)
  2484. iwl4965_ba_status(priv, tid, BA_STATUS_FAILURE);
  2485. return rc;
  2486. }
  2487. static void iwl4965_turn_on_agg_for_tid(struct iwl_priv *priv,
  2488. struct iwl_lq_mngr *lq,
  2489. u8 auto_agg, u8 tid)
  2490. {
  2491. u32 tid_msk = (1 << tid);
  2492. unsigned long flags;
  2493. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2494. /*
  2495. if ((auto_agg) && (!lq->enable_counter)){
  2496. lq->agg_ctrl.next_retry = 0;
  2497. lq->agg_ctrl.tid_retry = 0;
  2498. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2499. return;
  2500. }
  2501. */
  2502. if (!(lq->agg_ctrl.granted_ba & tid_msk) &&
  2503. (lq->agg_ctrl.requested_ba & tid_msk)) {
  2504. u8 available_queues;
  2505. u32 load;
  2506. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2507. available_queues = iwl4964_tl_ba_avail(priv);
  2508. load = iwl4965_tl_get_load(priv, tid);
  2509. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2510. if (!available_queues) {
  2511. if (auto_agg)
  2512. lq->agg_ctrl.tid_retry |= tid_msk;
  2513. else {
  2514. lq->agg_ctrl.requested_ba &= ~tid_msk;
  2515. lq->agg_ctrl.wait_for_agg_status &= ~tid_msk;
  2516. }
  2517. } else if ((auto_agg) &&
  2518. ((load <= lq->agg_ctrl.tid_traffic_load_threshold) ||
  2519. ((lq->agg_ctrl.wait_for_agg_status & tid_msk))))
  2520. lq->agg_ctrl.tid_retry |= tid_msk;
  2521. else {
  2522. lq->agg_ctrl.wait_for_agg_status |= tid_msk;
  2523. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2524. iwl4965_perform_addba(priv, tid, 0x40,
  2525. lq->agg_ctrl.ba_timeout);
  2526. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2527. }
  2528. }
  2529. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2530. }
  2531. static void iwl4965_turn_on_agg(struct iwl_priv *priv, u8 tid)
  2532. {
  2533. struct iwl_lq_mngr *lq;
  2534. unsigned long flags;
  2535. lq = (struct iwl_lq_mngr *)&(priv->lq_mngr);
  2536. if ((tid < TID_MAX_LOAD_COUNT))
  2537. iwl4965_turn_on_agg_for_tid(priv, lq, lq->agg_ctrl.auto_agg,
  2538. tid);
  2539. else if (tid == TID_ALL_SPECIFIED) {
  2540. if (lq->agg_ctrl.requested_ba) {
  2541. for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++)
  2542. iwl4965_turn_on_agg_for_tid(priv, lq,
  2543. lq->agg_ctrl.auto_agg, tid);
  2544. } else {
  2545. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2546. lq->agg_ctrl.tid_retry = 0;
  2547. lq->agg_ctrl.next_retry = 0;
  2548. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2549. }
  2550. }
  2551. }
  2552. void iwl4965_turn_off_agg(struct iwl_priv *priv, u8 tid)
  2553. {
  2554. u32 tid_msk;
  2555. struct iwl_lq_mngr *lq;
  2556. unsigned long flags;
  2557. lq = (struct iwl_lq_mngr *)&(priv->lq_mngr);
  2558. if ((tid < TID_MAX_LOAD_COUNT)) {
  2559. tid_msk = 1 << tid;
  2560. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2561. lq->agg_ctrl.wait_for_agg_status |= tid_msk;
  2562. lq->agg_ctrl.requested_ba &= ~tid_msk;
  2563. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2564. iwl4965_perform_delba(priv, tid);
  2565. } else if (tid == TID_ALL_SPECIFIED) {
  2566. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2567. for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++) {
  2568. tid_msk = 1 << tid;
  2569. lq->agg_ctrl.wait_for_agg_status |= tid_msk;
  2570. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2571. iwl4965_perform_delba(priv, tid);
  2572. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2573. }
  2574. lq->agg_ctrl.requested_ba = 0;
  2575. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2576. }
  2577. }
  2578. static void iwl4965_ba_status(struct iwl_priv *priv,
  2579. u8 tid, enum HT_STATUS status)
  2580. {
  2581. struct iwl_lq_mngr *lq;
  2582. u32 tid_msk = (1 << tid);
  2583. unsigned long flags;
  2584. lq = (struct iwl_lq_mngr *)&(priv->lq_mngr);
  2585. if ((tid >= TID_MAX_LOAD_COUNT))
  2586. goto out;
  2587. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2588. switch (status) {
  2589. case BA_STATUS_ACTIVE:
  2590. if (!(lq->agg_ctrl.granted_ba & tid_msk))
  2591. lq->agg_ctrl.granted_ba |= tid_msk;
  2592. break;
  2593. default:
  2594. if ((lq->agg_ctrl.granted_ba & tid_msk))
  2595. lq->agg_ctrl.granted_ba &= ~tid_msk;
  2596. break;
  2597. }
  2598. lq->agg_ctrl.wait_for_agg_status &= ~tid_msk;
  2599. if (status != BA_STATUS_ACTIVE) {
  2600. if (lq->agg_ctrl.auto_agg) {
  2601. lq->agg_ctrl.tid_retry |= tid_msk;
  2602. lq->agg_ctrl.next_retry =
  2603. jiffies + msecs_to_jiffies(500);
  2604. } else
  2605. lq->agg_ctrl.requested_ba &= ~tid_msk;
  2606. }
  2607. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2608. out:
  2609. return;
  2610. }
  2611. static void iwl4965_bg_agg_work(struct work_struct *work)
  2612. {
  2613. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2614. agg_work);
  2615. u32 tid;
  2616. u32 retry_tid;
  2617. u32 tid_msk;
  2618. unsigned long flags;
  2619. struct iwl_lq_mngr *lq = (struct iwl_lq_mngr *)&(priv->lq_mngr);
  2620. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2621. retry_tid = lq->agg_ctrl.tid_retry;
  2622. lq->agg_ctrl.tid_retry = 0;
  2623. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2624. if (retry_tid == TID_ALL_SPECIFIED)
  2625. iwl4965_turn_on_agg(priv, TID_ALL_SPECIFIED);
  2626. else {
  2627. for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++) {
  2628. tid_msk = (1 << tid);
  2629. if (retry_tid & tid_msk)
  2630. iwl4965_turn_on_agg(priv, tid);
  2631. }
  2632. }
  2633. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2634. if (lq->agg_ctrl.tid_retry)
  2635. lq->agg_ctrl.next_retry = jiffies + msecs_to_jiffies(500);
  2636. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2637. return;
  2638. }
  2639. #endif /*CONFIG_IWLWIFI_HT_AGG */
  2640. #endif /* CONFIG_IWLWIFI_HT */
  2641. int iwl4965_tx_cmd(struct iwl_priv *priv, struct iwl_cmd *out_cmd,
  2642. u8 sta_id, dma_addr_t txcmd_phys,
  2643. struct ieee80211_hdr *hdr, u8 hdr_len,
  2644. struct ieee80211_tx_control *ctrl, void *sta_in)
  2645. {
  2646. struct iwl_tx_cmd cmd;
  2647. struct iwl_tx_cmd *tx = (struct iwl_tx_cmd *)&out_cmd->cmd.payload[0];
  2648. dma_addr_t scratch_phys;
  2649. u8 unicast = 0;
  2650. u8 is_data = 1;
  2651. u16 fc;
  2652. u16 rate_flags;
  2653. int rate_index = min(ctrl->tx_rate & 0xffff, IWL_RATE_COUNT - 1);
  2654. #ifdef CONFIG_IWLWIFI_HT
  2655. #ifdef CONFIG_IWLWIFI_HT_AGG
  2656. __le16 *qc;
  2657. #endif /*CONFIG_IWLWIFI_HT_AGG */
  2658. #endif /* CONFIG_IWLWIFI_HT */
  2659. unicast = !is_multicast_ether_addr(hdr->addr1);
  2660. fc = le16_to_cpu(hdr->frame_control);
  2661. if ((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA)
  2662. is_data = 0;
  2663. memcpy(&cmd, &(out_cmd->cmd.tx), sizeof(struct iwl_tx_cmd));
  2664. memset(tx, 0, sizeof(struct iwl_tx_cmd));
  2665. memcpy(tx->hdr, hdr, hdr_len);
  2666. tx->len = cmd.len;
  2667. tx->driver_txop = cmd.driver_txop;
  2668. tx->stop_time.life_time = cmd.stop_time.life_time;
  2669. tx->tx_flags = cmd.tx_flags;
  2670. tx->sta_id = cmd.sta_id;
  2671. tx->tid_tspec = cmd.tid_tspec;
  2672. tx->timeout.pm_frame_timeout = cmd.timeout.pm_frame_timeout;
  2673. tx->next_frame_len = cmd.next_frame_len;
  2674. tx->sec_ctl = cmd.sec_ctl;
  2675. memcpy(&(tx->key[0]), &(cmd.key[0]), 16);
  2676. tx->tx_flags = cmd.tx_flags;
  2677. tx->rts_retry_limit = cmd.rts_retry_limit;
  2678. tx->data_retry_limit = cmd.data_retry_limit;
  2679. scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
  2680. offsetof(struct iwl_tx_cmd, scratch);
  2681. tx->dram_lsb_ptr = cpu_to_le32(scratch_phys);
  2682. tx->dram_msb_ptr = iwl4965_get_dma_hi_address(scratch_phys);
  2683. /* Hard coded to start at the highest retry fallback position
  2684. * until the 4965 specific rate control algorithm is tied in */
  2685. tx->initial_rate_index = LINK_QUAL_MAX_RETRY_NUM - 1;
  2686. /* Alternate between antenna A and B for successive frames */
  2687. if (priv->use_ant_b_for_management_frame) {
  2688. priv->use_ant_b_for_management_frame = 0;
  2689. rate_flags = RATE_MCS_ANT_B_MSK;
  2690. } else {
  2691. priv->use_ant_b_for_management_frame = 1;
  2692. rate_flags = RATE_MCS_ANT_A_MSK;
  2693. }
  2694. if (!unicast || !is_data) {
  2695. if ((rate_index >= IWL_FIRST_CCK_RATE) &&
  2696. (rate_index <= IWL_LAST_CCK_RATE))
  2697. rate_flags |= RATE_MCS_CCK_MSK;
  2698. } else {
  2699. tx->initial_rate_index = 0;
  2700. tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
  2701. }
  2702. tx->rate_n_flags = iwl_hw_set_rate_n_flags(iwl_rates[rate_index].plcp,
  2703. rate_flags);
  2704. if (ieee80211_is_probe_request(fc))
  2705. tx->tx_flags |= TX_CMD_FLG_TSF_MSK;
  2706. else if (ieee80211_is_back_request(fc))
  2707. tx->tx_flags |= TX_CMD_FLG_ACK_MSK |
  2708. TX_CMD_FLG_IMM_BA_RSP_MASK;
  2709. #ifdef CONFIG_IWLWIFI_HT
  2710. #ifdef CONFIG_IWLWIFI_HT_AGG
  2711. qc = ieee80211_get_qos_ctrl(hdr);
  2712. if (qc &&
  2713. (priv->iw_mode != IEEE80211_IF_TYPE_IBSS)) {
  2714. u8 tid = 0;
  2715. tid = (u8) (le16_to_cpu(*qc) & 0xF);
  2716. if (tid < TID_MAX_LOAD_COUNT)
  2717. iwl4965_tl_add_packet(priv, tid);
  2718. }
  2719. if (priv->lq_mngr.agg_ctrl.next_retry &&
  2720. (time_after(priv->lq_mngr.agg_ctrl.next_retry, jiffies))) {
  2721. unsigned long flags;
  2722. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2723. priv->lq_mngr.agg_ctrl.next_retry = 0;
  2724. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2725. schedule_work(&priv->agg_work);
  2726. }
  2727. #endif
  2728. #endif
  2729. return 0;
  2730. }
  2731. /**
  2732. * sign_extend - Sign extend a value using specified bit as sign-bit
  2733. *
  2734. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  2735. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  2736. *
  2737. * @param oper value to sign extend
  2738. * @param index 0 based bit index (0<=index<32) to sign bit
  2739. */
  2740. static s32 sign_extend(u32 oper, int index)
  2741. {
  2742. u8 shift = 31 - index;
  2743. return (s32)(oper << shift) >> shift;
  2744. }
  2745. /**
  2746. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  2747. * @statistics: Provides the temperature reading from the uCode
  2748. *
  2749. * A return of <0 indicates bogus data in the statistics
  2750. */
  2751. int iwl4965_get_temperature(const struct iwl_priv *priv)
  2752. {
  2753. s32 temperature;
  2754. s32 vt;
  2755. s32 R1, R2, R3;
  2756. u32 R4;
  2757. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  2758. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  2759. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  2760. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  2761. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  2762. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  2763. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  2764. } else {
  2765. IWL_DEBUG_TEMP("Running temperature calibration\n");
  2766. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  2767. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  2768. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  2769. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  2770. }
  2771. /*
  2772. * Temperature is only 23 bits so sign extend out to 32
  2773. *
  2774. * NOTE If we haven't received a statistics notification yet
  2775. * with an updated temperature, use R4 provided to us in the
  2776. * ALIVE response. */
  2777. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  2778. vt = sign_extend(R4, 23);
  2779. else
  2780. vt = sign_extend(
  2781. le32_to_cpu(priv->statistics.general.temperature), 23);
  2782. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  2783. R1, R2, R3, vt);
  2784. if (R3 == R1) {
  2785. IWL_ERROR("Calibration conflict R1 == R3\n");
  2786. return -1;
  2787. }
  2788. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  2789. * Add offset to center the adjustment around 0 degrees Centigrade. */
  2790. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  2791. temperature /= (R3 - R1);
  2792. temperature = (temperature * 97) / 100 +
  2793. TEMPERATURE_CALIB_KELVIN_OFFSET;
  2794. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  2795. KELVIN_TO_CELSIUS(temperature));
  2796. return temperature;
  2797. }
  2798. /* Adjust Txpower only if temperature variance is greater than threshold. */
  2799. #define IWL_TEMPERATURE_THRESHOLD 3
  2800. /**
  2801. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  2802. *
  2803. * If the temperature changed has changed sufficiently, then a recalibration
  2804. * is needed.
  2805. *
  2806. * Assumes caller will replace priv->last_temperature once calibration
  2807. * executed.
  2808. */
  2809. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  2810. {
  2811. int temp_diff;
  2812. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  2813. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  2814. return 0;
  2815. }
  2816. temp_diff = priv->temperature - priv->last_temperature;
  2817. /* get absolute value */
  2818. if (temp_diff < 0) {
  2819. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  2820. temp_diff = -temp_diff;
  2821. } else if (temp_diff == 0)
  2822. IWL_DEBUG_POWER("Same temp, \n");
  2823. else
  2824. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  2825. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  2826. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  2827. return 0;
  2828. }
  2829. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  2830. return 1;
  2831. }
  2832. /* Calculate noise level, based on measurements during network silence just
  2833. * before arriving beacon. This measurement can be done only if we know
  2834. * exactly when to expect beacons, therefore only when we're associated. */
  2835. static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
  2836. {
  2837. struct statistics_rx_non_phy *rx_info
  2838. = &(priv->statistics.rx.general);
  2839. int num_active_rx = 0;
  2840. int total_silence = 0;
  2841. int bcn_silence_a =
  2842. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  2843. int bcn_silence_b =
  2844. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  2845. int bcn_silence_c =
  2846. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  2847. if (bcn_silence_a) {
  2848. total_silence += bcn_silence_a;
  2849. num_active_rx++;
  2850. }
  2851. if (bcn_silence_b) {
  2852. total_silence += bcn_silence_b;
  2853. num_active_rx++;
  2854. }
  2855. if (bcn_silence_c) {
  2856. total_silence += bcn_silence_c;
  2857. num_active_rx++;
  2858. }
  2859. /* Average among active antennas */
  2860. if (num_active_rx)
  2861. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  2862. else
  2863. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2864. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  2865. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  2866. priv->last_rx_noise);
  2867. }
  2868. void iwl_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  2869. {
  2870. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2871. int change;
  2872. s32 temp;
  2873. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  2874. (int)sizeof(priv->statistics), pkt->len);
  2875. change = ((priv->statistics.general.temperature !=
  2876. pkt->u.stats.general.temperature) ||
  2877. ((priv->statistics.flag &
  2878. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  2879. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  2880. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  2881. set_bit(STATUS_STATISTICS, &priv->status);
  2882. /* Reschedule the statistics timer to occur in
  2883. * REG_RECALIB_PERIOD seconds to ensure we get a
  2884. * thermal update even if the uCode doesn't give
  2885. * us one */
  2886. mod_timer(&priv->statistics_periodic, jiffies +
  2887. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  2888. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2889. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  2890. iwl4965_rx_calc_noise(priv);
  2891. #ifdef CONFIG_IWLWIFI_SENSITIVITY
  2892. queue_work(priv->workqueue, &priv->sensitivity_work);
  2893. #endif
  2894. }
  2895. /* If the hardware hasn't reported a change in
  2896. * temperature then don't bother computing a
  2897. * calibrated temperature value */
  2898. if (!change)
  2899. return;
  2900. temp = iwl4965_get_temperature(priv);
  2901. if (temp < 0)
  2902. return;
  2903. if (priv->temperature != temp) {
  2904. if (priv->temperature)
  2905. IWL_DEBUG_TEMP("Temperature changed "
  2906. "from %dC to %dC\n",
  2907. KELVIN_TO_CELSIUS(priv->temperature),
  2908. KELVIN_TO_CELSIUS(temp));
  2909. else
  2910. IWL_DEBUG_TEMP("Temperature "
  2911. "initialized to %dC\n",
  2912. KELVIN_TO_CELSIUS(temp));
  2913. }
  2914. priv->temperature = temp;
  2915. set_bit(STATUS_TEMPERATURE, &priv->status);
  2916. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2917. iwl4965_is_temp_calib_needed(priv))
  2918. queue_work(priv->workqueue, &priv->txpower_work);
  2919. }
  2920. static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
  2921. int include_phy,
  2922. struct iwl_rx_mem_buffer *rxb,
  2923. struct ieee80211_rx_status *stats)
  2924. {
  2925. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2926. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2927. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  2928. struct ieee80211_hdr *hdr;
  2929. u16 len;
  2930. __le32 *rx_end;
  2931. unsigned int skblen;
  2932. u32 ampdu_status;
  2933. if (!include_phy && priv->last_phy_res[0])
  2934. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2935. if (!rx_start) {
  2936. IWL_ERROR("MPDU frame without a PHY data\n");
  2937. return;
  2938. }
  2939. if (include_phy) {
  2940. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  2941. rx_start->cfg_phy_cnt);
  2942. len = le16_to_cpu(rx_start->byte_count);
  2943. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  2944. sizeof(struct iwl4965_rx_phy_res) +
  2945. rx_start->cfg_phy_cnt + len);
  2946. } else {
  2947. struct iwl4965_rx_mpdu_res_start *amsdu =
  2948. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2949. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  2950. sizeof(struct iwl4965_rx_mpdu_res_start));
  2951. len = le16_to_cpu(amsdu->byte_count);
  2952. rx_start->byte_count = amsdu->byte_count;
  2953. rx_end = (__le32 *) (((u8 *) hdr) + len);
  2954. }
  2955. if (len > 2342 || len < 16) {
  2956. IWL_DEBUG_DROP("byte count out of range [16,2342]"
  2957. " : %d\n", len);
  2958. return;
  2959. }
  2960. ampdu_status = le32_to_cpu(*rx_end);
  2961. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  2962. /* start from MAC */
  2963. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  2964. skb_put(rxb->skb, len); /* end where data ends */
  2965. /* We only process data packets if the interface is open */
  2966. if (unlikely(!priv->is_open)) {
  2967. IWL_DEBUG_DROP_LIMIT
  2968. ("Dropping packet while interface is not open.\n");
  2969. return;
  2970. }
  2971. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  2972. if (iwl_param_hwcrypto)
  2973. iwl_set_decrypted_flag(priv, rxb->skb,
  2974. ampdu_status, stats);
  2975. iwl_handle_data_packet_monitor(priv, rxb, hdr, len, stats, 0);
  2976. return;
  2977. }
  2978. stats->flag = 0;
  2979. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  2980. if (iwl_param_hwcrypto)
  2981. iwl_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
  2982. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2983. priv->alloc_rxb_skb--;
  2984. rxb->skb = NULL;
  2985. #ifdef LED
  2986. priv->led_packets += len;
  2987. iwl_setup_activity_timer(priv);
  2988. #endif
  2989. }
  2990. /* Calc max signal level (dBm) among 3 possible receivers */
  2991. static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
  2992. {
  2993. /* data from PHY/DSP regarding signal strength, etc.,
  2994. * contents are always there, not configurable by host. */
  2995. struct iwl4965_rx_non_cfg_phy *ncphy =
  2996. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  2997. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  2998. >> IWL_AGC_DB_POS;
  2999. u32 valid_antennae =
  3000. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  3001. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  3002. u8 max_rssi = 0;
  3003. u32 i;
  3004. /* Find max rssi among 3 possible receivers.
  3005. * These values are measured by the digital signal processor (DSP).
  3006. * They should stay fairly constant even as the signal strength varies,
  3007. * if the radio's automatic gain control (AGC) is working right.
  3008. * AGC value (see below) will provide the "interesting" info. */
  3009. for (i = 0; i < 3; i++)
  3010. if (valid_antennae & (1 << i))
  3011. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  3012. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  3013. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  3014. max_rssi, agc);
  3015. /* dBm = max_rssi dB - agc dB - constant.
  3016. * Higher AGC (higher radio gain) means lower signal. */
  3017. return (max_rssi - agc - IWL_RSSI_OFFSET);
  3018. }
  3019. #ifdef CONFIG_IWLWIFI_HT
  3020. /* Parsed Information Elements */
  3021. struct ieee802_11_elems {
  3022. u8 *ds_params;
  3023. u8 ds_params_len;
  3024. u8 *tim;
  3025. u8 tim_len;
  3026. u8 *ibss_params;
  3027. u8 ibss_params_len;
  3028. u8 *erp_info;
  3029. u8 erp_info_len;
  3030. u8 *ht_cap_param;
  3031. u8 ht_cap_param_len;
  3032. u8 *ht_extra_param;
  3033. u8 ht_extra_param_len;
  3034. };
  3035. static int parse_elems(u8 *start, size_t len, struct ieee802_11_elems *elems)
  3036. {
  3037. size_t left = len;
  3038. u8 *pos = start;
  3039. int unknown = 0;
  3040. memset(elems, 0, sizeof(*elems));
  3041. while (left >= 2) {
  3042. u8 id, elen;
  3043. id = *pos++;
  3044. elen = *pos++;
  3045. left -= 2;
  3046. if (elen > left)
  3047. return -1;
  3048. switch (id) {
  3049. case WLAN_EID_DS_PARAMS:
  3050. elems->ds_params = pos;
  3051. elems->ds_params_len = elen;
  3052. break;
  3053. case WLAN_EID_TIM:
  3054. elems->tim = pos;
  3055. elems->tim_len = elen;
  3056. break;
  3057. case WLAN_EID_IBSS_PARAMS:
  3058. elems->ibss_params = pos;
  3059. elems->ibss_params_len = elen;
  3060. break;
  3061. case WLAN_EID_ERP_INFO:
  3062. elems->erp_info = pos;
  3063. elems->erp_info_len = elen;
  3064. break;
  3065. case WLAN_EID_HT_CAPABILITY:
  3066. elems->ht_cap_param = pos;
  3067. elems->ht_cap_param_len = elen;
  3068. break;
  3069. case WLAN_EID_HT_EXTRA_INFO:
  3070. elems->ht_extra_param = pos;
  3071. elems->ht_extra_param_len = elen;
  3072. break;
  3073. default:
  3074. unknown++;
  3075. break;
  3076. }
  3077. left -= elen;
  3078. pos += elen;
  3079. }
  3080. return 0;
  3081. }
  3082. #endif /* CONFIG_IWLWIFI_HT */
  3083. static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  3084. {
  3085. unsigned long flags;
  3086. spin_lock_irqsave(&priv->sta_lock, flags);
  3087. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  3088. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  3089. priv->stations[sta_id].sta.sta.modify_mask = 0;
  3090. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3091. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3092. iwl_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3093. }
  3094. static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  3095. {
  3096. /* FIXME: need locking over ps_status ??? */
  3097. u8 sta_id = iwl_hw_find_station(priv, addr);
  3098. if (sta_id != IWL_INVALID_STATION) {
  3099. u8 sta_awake = priv->stations[sta_id].
  3100. ps_status == STA_PS_STATUS_WAKE;
  3101. if (sta_awake && ps_bit)
  3102. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  3103. else if (!sta_awake && !ps_bit) {
  3104. iwl4965_sta_modify_ps_wake(priv, sta_id);
  3105. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  3106. }
  3107. }
  3108. }
  3109. /* Called for REPLY_4965_RX (legacy ABG frames), or
  3110. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  3111. static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  3112. struct iwl_rx_mem_buffer *rxb)
  3113. {
  3114. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  3115. /* Use phy data (Rx signal strength, etc.) contained within
  3116. * this rx packet for legacy frames,
  3117. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  3118. int include_phy = (pkt->hdr.cmd == REPLY_4965_RX);
  3119. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  3120. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  3121. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  3122. __le32 *rx_end;
  3123. unsigned int len = 0;
  3124. struct ieee80211_hdr *header;
  3125. u16 fc;
  3126. struct ieee80211_rx_status stats = {
  3127. .mactime = le64_to_cpu(rx_start->timestamp),
  3128. .channel = le16_to_cpu(rx_start->channel),
  3129. .phymode =
  3130. (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  3131. MODE_IEEE80211G : MODE_IEEE80211A,
  3132. .antenna = 0,
  3133. .rate = iwl_hw_get_rate(rx_start->rate_n_flags),
  3134. .flag = 0,
  3135. #ifdef CONFIG_IWLWIFI_HT_AGG
  3136. .ordered = 0
  3137. #endif /* CONFIG_IWLWIFI_HT_AGG */
  3138. };
  3139. u8 network_packet;
  3140. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  3141. IWL_DEBUG_DROP
  3142. ("dsp size out of range [0,20]: "
  3143. "%d/n", rx_start->cfg_phy_cnt);
  3144. return;
  3145. }
  3146. if (!include_phy) {
  3147. if (priv->last_phy_res[0])
  3148. rx_start = (struct iwl4965_rx_phy_res *)
  3149. &priv->last_phy_res[1];
  3150. else
  3151. rx_start = NULL;
  3152. }
  3153. if (!rx_start) {
  3154. IWL_ERROR("MPDU frame without a PHY data\n");
  3155. return;
  3156. }
  3157. if (include_phy) {
  3158. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  3159. + rx_start->cfg_phy_cnt);
  3160. len = le16_to_cpu(rx_start->byte_count);
  3161. rx_end = (__le32 *) (pkt->u.raw + rx_start->cfg_phy_cnt +
  3162. sizeof(struct iwl4965_rx_phy_res) + len);
  3163. } else {
  3164. struct iwl4965_rx_mpdu_res_start *amsdu =
  3165. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  3166. header = (void *)(pkt->u.raw +
  3167. sizeof(struct iwl4965_rx_mpdu_res_start));
  3168. len = le16_to_cpu(amsdu->byte_count);
  3169. rx_end = (__le32 *) (pkt->u.raw +
  3170. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  3171. }
  3172. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  3173. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  3174. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  3175. le32_to_cpu(*rx_end));
  3176. return;
  3177. }
  3178. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  3179. stats.freq = ieee80211chan2mhz(stats.channel);
  3180. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  3181. stats.ssi = iwl4965_calc_rssi(rx_start);
  3182. /* Meaningful noise values are available only from beacon statistics,
  3183. * which are gathered only when associated, and indicate noise
  3184. * only for the associated network channel ...
  3185. * Ignore these noise values while scanning (other channels) */
  3186. if (iwl_is_associated(priv) &&
  3187. !test_bit(STATUS_SCANNING, &priv->status)) {
  3188. stats.noise = priv->last_rx_noise;
  3189. stats.signal = iwl_calc_sig_qual(stats.ssi, stats.noise);
  3190. } else {
  3191. stats.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3192. stats.signal = iwl_calc_sig_qual(stats.ssi, 0);
  3193. }
  3194. /* Reset beacon noise level if not associated. */
  3195. if (!iwl_is_associated(priv))
  3196. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3197. #ifdef CONFIG_IWLWIFI_DEBUG
  3198. /* TODO: Parts of iwl_report_frame are broken for 4965 */
  3199. if (iwl_debug_level & (IWL_DL_RX))
  3200. /* Set "1" to report good data frames in groups of 100 */
  3201. iwl_report_frame(priv, pkt, header, 1);
  3202. if (iwl_debug_level & (IWL_DL_RX | IWL_DL_STATS))
  3203. IWL_DEBUG_RX("Rssi %d, noise %d, qual %d, TSF %lu\n",
  3204. stats.ssi, stats.noise, stats.signal,
  3205. (long unsigned int)le64_to_cpu(rx_start->timestamp));
  3206. #endif
  3207. network_packet = iwl_is_network_packet(priv, header);
  3208. if (network_packet) {
  3209. priv->last_rx_rssi = stats.ssi;
  3210. priv->last_beacon_time = priv->ucode_beacon_time;
  3211. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  3212. }
  3213. fc = le16_to_cpu(header->frame_control);
  3214. switch (fc & IEEE80211_FCTL_FTYPE) {
  3215. case IEEE80211_FTYPE_MGMT:
  3216. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3217. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3218. header->addr2);
  3219. switch (fc & IEEE80211_FCTL_STYPE) {
  3220. case IEEE80211_STYPE_PROBE_RESP:
  3221. case IEEE80211_STYPE_BEACON:
  3222. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA &&
  3223. !compare_ether_addr(header->addr2, priv->bssid)) ||
  3224. (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
  3225. !compare_ether_addr(header->addr3, priv->bssid))) {
  3226. struct ieee80211_mgmt *mgmt =
  3227. (struct ieee80211_mgmt *)header;
  3228. u64 timestamp =
  3229. le64_to_cpu(mgmt->u.beacon.timestamp);
  3230. priv->timestamp0 = timestamp & 0xFFFFFFFF;
  3231. priv->timestamp1 =
  3232. (timestamp >> 32) & 0xFFFFFFFF;
  3233. priv->beacon_int = le16_to_cpu(
  3234. mgmt->u.beacon.beacon_int);
  3235. if (priv->call_post_assoc_from_beacon &&
  3236. (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
  3237. priv->call_post_assoc_from_beacon = 0;
  3238. queue_work(priv->workqueue,
  3239. &priv->post_associate.work);
  3240. }
  3241. }
  3242. break;
  3243. case IEEE80211_STYPE_ACTION:
  3244. break;
  3245. /*
  3246. * TODO: There is no callback function from upper
  3247. * stack to inform us when associated status. this
  3248. * work around to sniff assoc_resp management frame
  3249. * and finish the association process.
  3250. */
  3251. case IEEE80211_STYPE_ASSOC_RESP:
  3252. case IEEE80211_STYPE_REASSOC_RESP:
  3253. if (network_packet && iwl_is_associated(priv)) {
  3254. #ifdef CONFIG_IWLWIFI_HT
  3255. u8 *pos = NULL;
  3256. struct ieee802_11_elems elems;
  3257. #endif /*CONFIG_IWLWIFI_HT */
  3258. struct ieee80211_mgmt *mgnt =
  3259. (struct ieee80211_mgmt *)header;
  3260. priv->assoc_id = (~((1 << 15) | (1 << 14))
  3261. & le16_to_cpu(mgnt->u.assoc_resp.aid));
  3262. priv->assoc_capability =
  3263. le16_to_cpu(
  3264. mgnt->u.assoc_resp.capab_info);
  3265. #ifdef CONFIG_IWLWIFI_HT
  3266. pos = mgnt->u.assoc_resp.variable;
  3267. if (!parse_elems(pos,
  3268. len - (pos - (u8 *) mgnt),
  3269. &elems)) {
  3270. if (elems.ht_extra_param &&
  3271. elems.ht_cap_param)
  3272. break;
  3273. }
  3274. #endif /*CONFIG_IWLWIFI_HT */
  3275. /* assoc_id is 0 no association */
  3276. if (!priv->assoc_id)
  3277. break;
  3278. if (priv->beacon_int)
  3279. queue_work(priv->workqueue,
  3280. &priv->post_associate.work);
  3281. else
  3282. priv->call_post_assoc_from_beacon = 1;
  3283. }
  3284. break;
  3285. case IEEE80211_STYPE_PROBE_REQ:
  3286. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  3287. !iwl_is_associated(priv)) {
  3288. DECLARE_MAC_BUF(mac1);
  3289. DECLARE_MAC_BUF(mac2);
  3290. DECLARE_MAC_BUF(mac3);
  3291. IWL_DEBUG_DROP("Dropping (non network): "
  3292. "%s, %s, %s\n",
  3293. print_mac(mac1, header->addr1),
  3294. print_mac(mac2, header->addr2),
  3295. print_mac(mac3, header->addr3));
  3296. return;
  3297. }
  3298. }
  3299. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &stats);
  3300. break;
  3301. case IEEE80211_FTYPE_CTL:
  3302. #ifdef CONFIG_IWLWIFI_HT_AGG
  3303. switch (fc & IEEE80211_FCTL_STYPE) {
  3304. case IEEE80211_STYPE_BACK_REQ:
  3305. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  3306. iwl4965_handle_data_packet(priv, 0, include_phy,
  3307. rxb, &stats);
  3308. break;
  3309. default:
  3310. break;
  3311. }
  3312. #endif
  3313. break;
  3314. case IEEE80211_FTYPE_DATA: {
  3315. DECLARE_MAC_BUF(mac1);
  3316. DECLARE_MAC_BUF(mac2);
  3317. DECLARE_MAC_BUF(mac3);
  3318. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3319. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3320. header->addr2);
  3321. if (unlikely(!network_packet))
  3322. IWL_DEBUG_DROP("Dropping (non network): "
  3323. "%s, %s, %s\n",
  3324. print_mac(mac1, header->addr1),
  3325. print_mac(mac2, header->addr2),
  3326. print_mac(mac3, header->addr3));
  3327. else if (unlikely(is_duplicate_packet(priv, header)))
  3328. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  3329. print_mac(mac1, header->addr1),
  3330. print_mac(mac2, header->addr2),
  3331. print_mac(mac3, header->addr3));
  3332. else
  3333. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  3334. &stats);
  3335. break;
  3336. }
  3337. default:
  3338. break;
  3339. }
  3340. }
  3341. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  3342. * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  3343. static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
  3344. struct iwl_rx_mem_buffer *rxb)
  3345. {
  3346. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  3347. priv->last_phy_res[0] = 1;
  3348. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  3349. sizeof(struct iwl4965_rx_phy_res));
  3350. }
  3351. static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
  3352. struct iwl_rx_mem_buffer *rxb)
  3353. {
  3354. #ifdef CONFIG_IWLWIFI_SENSITIVITY
  3355. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  3356. struct iwl_missed_beacon_notif *missed_beacon;
  3357. missed_beacon = &pkt->u.missed_beacon;
  3358. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  3359. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  3360. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  3361. le32_to_cpu(missed_beacon->total_missed_becons),
  3362. le32_to_cpu(missed_beacon->num_recvd_beacons),
  3363. le32_to_cpu(missed_beacon->num_expected_beacons));
  3364. priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
  3365. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
  3366. queue_work(priv->workqueue, &priv->sensitivity_work);
  3367. }
  3368. #endif /*CONFIG_IWLWIFI_SENSITIVITY*/
  3369. }
  3370. #ifdef CONFIG_IWLWIFI_HT
  3371. #ifdef CONFIG_IWLWIFI_HT_AGG
  3372. static void iwl4965_set_tx_status(struct iwl_priv *priv, int txq_id, int idx,
  3373. u32 status, u32 retry_count, u32 rate)
  3374. {
  3375. struct ieee80211_tx_status *tx_status =
  3376. &(priv->txq[txq_id].txb[idx].status);
  3377. tx_status->flags = status ? IEEE80211_TX_STATUS_ACK : 0;
  3378. tx_status->retry_count += retry_count;
  3379. tx_status->control.tx_rate = rate;
  3380. }
  3381. static void iwl_sta_modify_enable_tid_tx(struct iwl_priv *priv,
  3382. int sta_id, int tid)
  3383. {
  3384. unsigned long flags;
  3385. spin_lock_irqsave(&priv->sta_lock, flags);
  3386. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
  3387. priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
  3388. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3389. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3390. iwl_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3391. }
  3392. static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
  3393. struct iwl_ht_agg *agg,
  3394. struct iwl_compressed_ba_resp*
  3395. ba_resp)
  3396. {
  3397. int i, sh, ack;
  3398. u16 ba_seq_ctl = le16_to_cpu(ba_resp->ba_seq_ctl);
  3399. u32 bitmap0, bitmap1;
  3400. u32 resp_bitmap0 = le32_to_cpu(ba_resp->ba_bitmap0);
  3401. u32 resp_bitmap1 = le32_to_cpu(ba_resp->ba_bitmap1);
  3402. if (unlikely(!agg->wait_for_ba)) {
  3403. IWL_ERROR("Received BA when not expected\n");
  3404. return -EINVAL;
  3405. }
  3406. agg->wait_for_ba = 0;
  3407. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->ba_seq_ctl);
  3408. sh = agg->start_idx - SEQ_TO_INDEX(ba_seq_ctl>>4);
  3409. if (sh < 0) /* tbw something is wrong with indeces */
  3410. sh += 0x100;
  3411. /* don't use 64 bits for now */
  3412. bitmap0 = resp_bitmap0 >> sh;
  3413. bitmap1 = resp_bitmap1 >> sh;
  3414. bitmap0 |= (resp_bitmap1 & ((1<<sh)|((1<<sh)-1))) << (32 - sh);
  3415. if (agg->frame_count > (64 - sh)) {
  3416. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  3417. return -1;
  3418. }
  3419. /* check for success or failure according to the
  3420. * transmitted bitmap and back bitmap */
  3421. bitmap0 &= agg->bitmap0;
  3422. bitmap1 &= agg->bitmap1;
  3423. for (i = 0; i < agg->frame_count ; i++) {
  3424. int idx = (agg->start_idx + i) & 0xff;
  3425. ack = bitmap0 & (1 << i);
  3426. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  3427. ack? "ACK":"NACK", i, idx, agg->start_idx + i);
  3428. iwl4965_set_tx_status(priv, agg->txq_id, idx, ack, 0,
  3429. agg->rate_n_flags);
  3430. }
  3431. IWL_DEBUG_TX_REPLY("Bitmap %x%x\n", bitmap0, bitmap1);
  3432. return 0;
  3433. }
  3434. static inline int iwl_queue_dec_wrap(int index, int n_bd)
  3435. {
  3436. return (index == 0) ? n_bd - 1 : index - 1;
  3437. }
  3438. static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
  3439. struct iwl_rx_mem_buffer *rxb)
  3440. {
  3441. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  3442. struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  3443. int index;
  3444. struct iwl_tx_queue *txq = NULL;
  3445. struct iwl_ht_agg *agg;
  3446. u16 ba_resp_scd_flow = le16_to_cpu(ba_resp->scd_flow);
  3447. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  3448. if (ba_resp_scd_flow >= ARRAY_SIZE(priv->txq)) {
  3449. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  3450. return;
  3451. }
  3452. txq = &priv->txq[ba_resp_scd_flow];
  3453. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  3454. index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  3455. /* TODO: Need to get this copy more sefely - now good for debug */
  3456. /*
  3457. {
  3458. DECLARE_MAC_BUF(mac);
  3459. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  3460. "sta_id = %d\n",
  3461. agg->wait_for_ba,
  3462. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  3463. ba_resp->sta_id);
  3464. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%X%X, scd_flow = "
  3465. "%d, scd_ssn = %d\n",
  3466. ba_resp->tid,
  3467. ba_resp->ba_seq_ctl,
  3468. ba_resp->ba_bitmap1,
  3469. ba_resp->ba_bitmap0,
  3470. ba_resp->scd_flow,
  3471. ba_resp->scd_ssn);
  3472. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%X%X \n",
  3473. agg->start_idx,
  3474. agg->bitmap1,
  3475. agg->bitmap0);
  3476. }
  3477. */
  3478. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  3479. /* releases all the TFDs until the SSN */
  3480. if (txq->q.last_used != (ba_resp_scd_ssn & 0xff))
  3481. iwl_tx_queue_reclaim(priv, ba_resp_scd_flow, index);
  3482. }
  3483. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
  3484. {
  3485. iwl_write_restricted_reg(priv,
  3486. SCD_QUEUE_STATUS_BITS(txq_id),
  3487. (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  3488. (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  3489. }
  3490. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  3491. u16 txq_id)
  3492. {
  3493. u32 tbl_dw_addr;
  3494. u32 tbl_dw;
  3495. u16 scd_q2ratid;
  3496. scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  3497. tbl_dw_addr = priv->scd_base_addr +
  3498. SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  3499. tbl_dw = iwl_read_restricted_mem(priv, tbl_dw_addr);
  3500. if (txq_id & 0x1)
  3501. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  3502. else
  3503. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  3504. iwl_write_restricted_mem(priv, tbl_dw_addr, tbl_dw);
  3505. return 0;
  3506. }
  3507. /**
  3508. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  3509. */
  3510. static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
  3511. int tx_fifo, int sta_id, int tid,
  3512. u16 ssn_idx)
  3513. {
  3514. unsigned long flags;
  3515. int rc;
  3516. u16 ra_tid;
  3517. if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
  3518. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3519. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3520. ra_tid = BUILD_RAxTID(sta_id, tid);
  3521. iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
  3522. spin_lock_irqsave(&priv->lock, flags);
  3523. rc = iwl_grab_restricted_access(priv);
  3524. if (rc) {
  3525. spin_unlock_irqrestore(&priv->lock, flags);
  3526. return rc;
  3527. }
  3528. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3529. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  3530. iwl_set_bits_restricted_reg(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id));
  3531. priv->txq[txq_id].q.last_used = (ssn_idx & 0xff);
  3532. priv->txq[txq_id].q.first_empty = (ssn_idx & 0xff);
  3533. /* supposes that ssn_idx is valid (!= 0xFFF) */
  3534. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3535. iwl_write_restricted_mem(priv,
  3536. priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  3537. (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  3538. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  3539. iwl_write_restricted_mem(priv, priv->scd_base_addr +
  3540. SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  3541. (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  3542. & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  3543. iwl_set_bits_restricted_reg(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
  3544. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  3545. iwl_release_restricted_access(priv);
  3546. spin_unlock_irqrestore(&priv->lock, flags);
  3547. return 0;
  3548. }
  3549. /**
  3550. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  3551. */
  3552. static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
  3553. u16 ssn_idx, u8 tx_fifo)
  3554. {
  3555. unsigned long flags;
  3556. int rc;
  3557. if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
  3558. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3559. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3560. return -EINVAL;
  3561. }
  3562. spin_lock_irqsave(&priv->lock, flags);
  3563. rc = iwl_grab_restricted_access(priv);
  3564. if (rc) {
  3565. spin_unlock_irqrestore(&priv->lock, flags);
  3566. return rc;
  3567. }
  3568. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3569. iwl_clear_bits_restricted_reg(priv, SCD_QUEUECHAIN_SEL, (1 << txq_id));
  3570. priv->txq[txq_id].q.last_used = (ssn_idx & 0xff);
  3571. priv->txq[txq_id].q.first_empty = (ssn_idx & 0xff);
  3572. /* supposes that ssn_idx is valid (!= 0xFFF) */
  3573. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3574. iwl_clear_bits_restricted_reg(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
  3575. iwl4965_txq_ctx_deactivate(priv, txq_id);
  3576. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  3577. iwl_release_restricted_access(priv);
  3578. spin_unlock_irqrestore(&priv->lock, flags);
  3579. return 0;
  3580. }
  3581. #endif/* CONFIG_IWLWIFI_HT_AGG */
  3582. #endif /* CONFIG_IWLWIFI_HT */
  3583. /*
  3584. * RATE SCALE CODE
  3585. */
  3586. int iwl4965_init_hw_rates(struct iwl_priv *priv, struct ieee80211_rate *rates)
  3587. {
  3588. return 0;
  3589. }
  3590. /**
  3591. * iwl4965_add_station - Initialize a station's hardware rate table
  3592. *
  3593. * The uCode contains a table of fallback rates and retries per rate
  3594. * for automatic fallback during transmission.
  3595. *
  3596. * NOTE: This initializes the table for a single retry per data rate
  3597. * which is not optimal. Setting up an intelligent retry per rate
  3598. * requires feedback from transmission, which isn't exposed through
  3599. * rc80211_simple which is what this driver is currently using.
  3600. *
  3601. */
  3602. void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  3603. {
  3604. int i, r;
  3605. struct iwl_link_quality_cmd link_cmd = {
  3606. .reserved1 = 0,
  3607. };
  3608. u16 rate_flags;
  3609. /* Set up the rate scaling to start at 54M and fallback
  3610. * all the way to 1M in IEEE order and then spin on IEEE */
  3611. if (is_ap)
  3612. r = IWL_RATE_54M_INDEX;
  3613. else if (priv->phymode == MODE_IEEE80211A)
  3614. r = IWL_RATE_6M_INDEX;
  3615. else
  3616. r = IWL_RATE_1M_INDEX;
  3617. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  3618. rate_flags = 0;
  3619. if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
  3620. rate_flags |= RATE_MCS_CCK_MSK;
  3621. rate_flags |= RATE_MCS_ANT_B_MSK;
  3622. rate_flags &= ~RATE_MCS_ANT_A_MSK;
  3623. link_cmd.rs_table[i].rate_n_flags =
  3624. iwl_hw_set_rate_n_flags(iwl_rates[r].plcp, rate_flags);
  3625. r = iwl_get_prev_ieee_rate(r);
  3626. }
  3627. link_cmd.general_params.single_stream_ant_msk = 2;
  3628. link_cmd.general_params.dual_stream_ant_msk = 3;
  3629. link_cmd.agg_params.agg_dis_start_th = 3;
  3630. link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
  3631. /* Update the rate scaling for control frame Tx to AP */
  3632. link_cmd.sta_id = is_ap ? IWL_AP_ID : IWL4965_BROADCAST_ID;
  3633. iwl_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd),
  3634. &link_cmd);
  3635. }
  3636. #ifdef CONFIG_IWLWIFI_HT
  3637. static u8 iwl_is_channel_extension(struct iwl_priv *priv, int phymode,
  3638. u16 channel, u8 extension_chan_offset)
  3639. {
  3640. const struct iwl_channel_info *ch_info;
  3641. ch_info = iwl_get_channel_info(priv, phymode, channel);
  3642. if (!is_channel_valid(ch_info))
  3643. return 0;
  3644. if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO)
  3645. return 0;
  3646. if ((ch_info->fat_extension_channel == extension_chan_offset) ||
  3647. (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
  3648. return 1;
  3649. return 0;
  3650. }
  3651. static u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
  3652. const struct sta_ht_info *ht_info)
  3653. {
  3654. if (priv->channel_width != IWL_CHANNEL_WIDTH_40MHZ)
  3655. return 0;
  3656. if (ht_info->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ)
  3657. return 0;
  3658. if (ht_info->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO)
  3659. return 0;
  3660. /* no fat tx allowed on 2.4GHZ */
  3661. if (priv->phymode != MODE_IEEE80211A)
  3662. return 0;
  3663. return (iwl_is_channel_extension(priv, priv->phymode,
  3664. ht_info->control_channel,
  3665. ht_info->extension_chan_offset));
  3666. }
  3667. void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct sta_ht_info *ht_info)
  3668. {
  3669. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  3670. u32 val;
  3671. if (!ht_info->is_ht)
  3672. return;
  3673. if (iwl_is_fat_tx_allowed(priv, ht_info))
  3674. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3675. else
  3676. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
  3677. RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
  3678. if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
  3679. IWL_DEBUG_ASSOC("control diff than current %d %d\n",
  3680. le16_to_cpu(rxon->channel),
  3681. ht_info->control_channel);
  3682. rxon->channel = cpu_to_le16(ht_info->control_channel);
  3683. return;
  3684. }
  3685. /* Note: control channel is oposit to extension channel */
  3686. switch (ht_info->extension_chan_offset) {
  3687. case IWL_EXT_CHANNEL_OFFSET_ABOVE:
  3688. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3689. break;
  3690. case IWL_EXT_CHANNEL_OFFSET_BELOW:
  3691. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3692. break;
  3693. case IWL_EXT_CHANNEL_OFFSET_AUTO:
  3694. rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3695. break;
  3696. default:
  3697. rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3698. break;
  3699. }
  3700. val = ht_info->operating_mode;
  3701. rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
  3702. priv->active_rate_ht[0] = ht_info->supp_rates[0];
  3703. priv->active_rate_ht[1] = ht_info->supp_rates[1];
  3704. iwl4965_set_rxon_chain(priv);
  3705. IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
  3706. "rxon flags 0x%X operation mode :0x%X "
  3707. "extension channel offset 0x%x "
  3708. "control chan %d\n",
  3709. priv->active_rate_ht[0], priv->active_rate_ht[1],
  3710. le32_to_cpu(rxon->flags), ht_info->operating_mode,
  3711. ht_info->extension_chan_offset,
  3712. ht_info->control_channel);
  3713. return;
  3714. }
  3715. void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index)
  3716. {
  3717. __le32 sta_flags;
  3718. struct sta_ht_info *ht_info = &priv->current_assoc_ht;
  3719. priv->current_channel_width = IWL_CHANNEL_WIDTH_20MHZ;
  3720. if (!ht_info->is_ht)
  3721. goto done;
  3722. sta_flags = priv->stations[index].sta.station_flags;
  3723. if (ht_info->tx_mimo_ps_mode == IWL_MIMO_PS_DYNAMIC)
  3724. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  3725. else
  3726. sta_flags &= ~STA_FLG_RTS_MIMO_PROT_MSK;
  3727. sta_flags |= cpu_to_le32(
  3728. (u32)ht_info->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  3729. sta_flags |= cpu_to_le32(
  3730. (u32)ht_info->mpdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  3731. sta_flags &= (~STA_FLG_FAT_EN_MSK);
  3732. ht_info->tx_chan_width = IWL_CHANNEL_WIDTH_20MHZ;
  3733. ht_info->chan_width_cap = IWL_CHANNEL_WIDTH_20MHZ;
  3734. if (iwl_is_fat_tx_allowed(priv, ht_info)) {
  3735. sta_flags |= STA_FLG_FAT_EN_MSK;
  3736. ht_info->chan_width_cap = IWL_CHANNEL_WIDTH_40MHZ;
  3737. if (ht_info->supported_chan_width == IWL_CHANNEL_WIDTH_40MHZ)
  3738. ht_info->tx_chan_width = IWL_CHANNEL_WIDTH_40MHZ;
  3739. }
  3740. priv->current_channel_width = ht_info->tx_chan_width;
  3741. priv->stations[index].sta.station_flags = sta_flags;
  3742. done:
  3743. return;
  3744. }
  3745. #ifdef CONFIG_IWLWIFI_HT_AGG
  3746. static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv,
  3747. int sta_id, int tid, u16 ssn)
  3748. {
  3749. unsigned long flags;
  3750. spin_lock_irqsave(&priv->sta_lock, flags);
  3751. priv->stations[sta_id].sta.station_flags_msk = 0;
  3752. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  3753. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  3754. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  3755. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3756. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3757. iwl_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3758. }
  3759. static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv,
  3760. int sta_id, int tid)
  3761. {
  3762. unsigned long flags;
  3763. spin_lock_irqsave(&priv->sta_lock, flags);
  3764. priv->stations[sta_id].sta.station_flags_msk = 0;
  3765. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  3766. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  3767. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3768. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3769. iwl_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3770. }
  3771. static const u16 default_tid_to_tx_fifo[] = {
  3772. IWL_TX_FIFO_AC1,
  3773. IWL_TX_FIFO_AC0,
  3774. IWL_TX_FIFO_AC0,
  3775. IWL_TX_FIFO_AC1,
  3776. IWL_TX_FIFO_AC2,
  3777. IWL_TX_FIFO_AC2,
  3778. IWL_TX_FIFO_AC3,
  3779. IWL_TX_FIFO_AC3,
  3780. IWL_TX_FIFO_NONE,
  3781. IWL_TX_FIFO_NONE,
  3782. IWL_TX_FIFO_NONE,
  3783. IWL_TX_FIFO_NONE,
  3784. IWL_TX_FIFO_NONE,
  3785. IWL_TX_FIFO_NONE,
  3786. IWL_TX_FIFO_NONE,
  3787. IWL_TX_FIFO_NONE,
  3788. IWL_TX_FIFO_AC3
  3789. };
  3790. static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
  3791. {
  3792. int txq_id;
  3793. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  3794. if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
  3795. return txq_id;
  3796. return -1;
  3797. }
  3798. int iwl_mac_ht_tx_agg_start(struct ieee80211_hw *hw, u8 *da, u16 tid,
  3799. u16 *start_seq_num)
  3800. {
  3801. struct iwl_priv *priv = hw->priv;
  3802. int sta_id;
  3803. int tx_fifo;
  3804. int txq_id;
  3805. int ssn = -1;
  3806. unsigned long flags;
  3807. struct iwl_tid_data *tid_data;
  3808. DECLARE_MAC_BUF(mac);
  3809. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  3810. tx_fifo = default_tid_to_tx_fifo[tid];
  3811. else
  3812. return -EINVAL;
  3813. IWL_WARNING("iwl-AGG iwl_mac_ht_tx_agg_start on da=%s"
  3814. " tid=%d\n", print_mac(mac, da), tid);
  3815. sta_id = iwl_hw_find_station(priv, da);
  3816. if (sta_id == IWL_INVALID_STATION)
  3817. return -ENXIO;
  3818. txq_id = iwl_txq_ctx_activate_free(priv);
  3819. if (txq_id == -1)
  3820. return -ENXIO;
  3821. spin_lock_irqsave(&priv->sta_lock, flags);
  3822. tid_data = &priv->stations[sta_id].tid[tid];
  3823. ssn = SEQ_TO_SN(tid_data->seq_number);
  3824. tid_data->agg.txq_id = txq_id;
  3825. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3826. *start_seq_num = ssn;
  3827. iwl4965_ba_status(priv, tid, BA_STATUS_ACTIVE);
  3828. return iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
  3829. sta_id, tid, ssn);
  3830. }
  3831. int iwl_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, u8 *da, u16 tid,
  3832. int generator)
  3833. {
  3834. struct iwl_priv *priv = hw->priv;
  3835. int tx_fifo_id, txq_id, sta_id, ssn = -1;
  3836. struct iwl_tid_data *tid_data;
  3837. int rc;
  3838. DECLARE_MAC_BUF(mac);
  3839. if (!da) {
  3840. IWL_ERROR("%s: da = NULL\n", __func__);
  3841. return -EINVAL;
  3842. }
  3843. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  3844. tx_fifo_id = default_tid_to_tx_fifo[tid];
  3845. else
  3846. return -EINVAL;
  3847. sta_id = iwl_hw_find_station(priv, da);
  3848. if (sta_id == IWL_INVALID_STATION)
  3849. return -ENXIO;
  3850. tid_data = &priv->stations[sta_id].tid[tid];
  3851. ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
  3852. txq_id = tid_data->agg.txq_id;
  3853. rc = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
  3854. /* FIXME: need more safe way to handle error condition */
  3855. if (rc)
  3856. return rc;
  3857. iwl4965_ba_status(priv, tid, BA_STATUS_INITIATOR_DELBA);
  3858. IWL_DEBUG_INFO("iwl_mac_ht_tx_agg_stop on da=%s tid=%d\n",
  3859. print_mac(mac, da), tid);
  3860. return 0;
  3861. }
  3862. int iwl_mac_ht_rx_agg_start(struct ieee80211_hw *hw, u8 *da,
  3863. u16 tid, u16 start_seq_num)
  3864. {
  3865. struct iwl_priv *priv = hw->priv;
  3866. int sta_id;
  3867. DECLARE_MAC_BUF(mac);
  3868. IWL_WARNING("iwl-AGG iwl_mac_ht_rx_agg_start on da=%s"
  3869. " tid=%d\n", print_mac(mac, da), tid);
  3870. sta_id = iwl_hw_find_station(priv, da);
  3871. iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, start_seq_num);
  3872. return 0;
  3873. }
  3874. int iwl_mac_ht_rx_agg_stop(struct ieee80211_hw *hw, u8 *da,
  3875. u16 tid, int generator)
  3876. {
  3877. struct iwl_priv *priv = hw->priv;
  3878. int sta_id;
  3879. DECLARE_MAC_BUF(mac);
  3880. IWL_WARNING("iwl-AGG iwl_mac_ht_rx_agg_stop on da=%s tid=%d\n",
  3881. print_mac(mac, da), tid);
  3882. sta_id = iwl_hw_find_station(priv, da);
  3883. iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
  3884. return 0;
  3885. }
  3886. #endif /* CONFIG_IWLWIFI_HT_AGG */
  3887. #endif /* CONFIG_IWLWIFI_HT */
  3888. /* Set up 4965-specific Rx frame reply handlers */
  3889. void iwl_hw_rx_handler_setup(struct iwl_priv *priv)
  3890. {
  3891. /* Legacy Rx frames */
  3892. priv->rx_handlers[REPLY_4965_RX] = iwl4965_rx_reply_rx;
  3893. /* High-throughput (HT) Rx frames */
  3894. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
  3895. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
  3896. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  3897. iwl4965_rx_missed_beacon_notif;
  3898. #ifdef CONFIG_IWLWIFI_HT
  3899. #ifdef CONFIG_IWLWIFI_HT_AGG
  3900. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  3901. #endif /* CONFIG_IWLWIFI_AGG */
  3902. #endif /* CONFIG_IWLWIFI */
  3903. }
  3904. void iwl_hw_setup_deferred_work(struct iwl_priv *priv)
  3905. {
  3906. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  3907. INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
  3908. #ifdef CONFIG_IWLWIFI_SENSITIVITY
  3909. INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
  3910. #endif
  3911. #ifdef CONFIG_IWLWIFI_HT
  3912. #ifdef CONFIG_IWLWIFI_HT_AGG
  3913. INIT_WORK(&priv->agg_work, iwl4965_bg_agg_work);
  3914. #endif /* CONFIG_IWLWIFI_AGG */
  3915. #endif /* CONFIG_IWLWIFI_HT */
  3916. init_timer(&priv->statistics_periodic);
  3917. priv->statistics_periodic.data = (unsigned long)priv;
  3918. priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
  3919. }
  3920. void iwl_hw_cancel_deferred_work(struct iwl_priv *priv)
  3921. {
  3922. del_timer_sync(&priv->statistics_periodic);
  3923. cancel_delayed_work(&priv->init_alive_start);
  3924. }
  3925. struct pci_device_id iwl_hw_card_ids[] = {
  3926. {0x8086, 0x4229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  3927. {0x8086, 0x4230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  3928. {0}
  3929. };
  3930. int iwl_eeprom_aqcuire_semaphore(struct iwl_priv *priv)
  3931. {
  3932. u16 count;
  3933. int rc;
  3934. for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
  3935. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  3936. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
  3937. rc = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  3938. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
  3939. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
  3940. EEPROM_SEM_TIMEOUT);
  3941. if (rc >= 0) {
  3942. IWL_DEBUG_IO("Aqcuired semaphore after %d tries.\n",
  3943. count+1);
  3944. return rc;
  3945. }
  3946. }
  3947. return rc;
  3948. }
  3949. inline void iwl_eeprom_release_semaphore(struct iwl_priv *priv)
  3950. {
  3951. iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
  3952. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
  3953. }
  3954. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);