ad1848_lib.c 38 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of AD1848/AD1847/CS4248
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #define SNDRV_MAIN_OBJECT_FILE
  22. #include <sound/driver.h>
  23. #include <linux/delay.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/slab.h>
  27. #include <linux/ioport.h>
  28. #include <sound/core.h>
  29. #include <sound/ad1848.h>
  30. #include <sound/control.h>
  31. #include <sound/tlv.h>
  32. #include <sound/pcm_params.h>
  33. #include <asm/io.h>
  34. #include <asm/dma.h>
  35. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  36. MODULE_DESCRIPTION("Routines for control of AD1848/AD1847/CS4248");
  37. MODULE_LICENSE("GPL");
  38. #if 0
  39. #define SNDRV_DEBUG_MCE
  40. #endif
  41. /*
  42. * Some variables
  43. */
  44. static unsigned char freq_bits[14] = {
  45. /* 5510 */ 0x00 | AD1848_XTAL2,
  46. /* 6620 */ 0x0E | AD1848_XTAL2,
  47. /* 8000 */ 0x00 | AD1848_XTAL1,
  48. /* 9600 */ 0x0E | AD1848_XTAL1,
  49. /* 11025 */ 0x02 | AD1848_XTAL2,
  50. /* 16000 */ 0x02 | AD1848_XTAL1,
  51. /* 18900 */ 0x04 | AD1848_XTAL2,
  52. /* 22050 */ 0x06 | AD1848_XTAL2,
  53. /* 27042 */ 0x04 | AD1848_XTAL1,
  54. /* 32000 */ 0x06 | AD1848_XTAL1,
  55. /* 33075 */ 0x0C | AD1848_XTAL2,
  56. /* 37800 */ 0x08 | AD1848_XTAL2,
  57. /* 44100 */ 0x0A | AD1848_XTAL2,
  58. /* 48000 */ 0x0C | AD1848_XTAL1
  59. };
  60. static unsigned int rates[14] = {
  61. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  62. 27042, 32000, 33075, 37800, 44100, 48000
  63. };
  64. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  65. .count = ARRAY_SIZE(rates),
  66. .list = rates,
  67. .mask = 0,
  68. };
  69. static unsigned char snd_ad1848_original_image[16] =
  70. {
  71. 0x00, /* 00 - lic */
  72. 0x00, /* 01 - ric */
  73. 0x9f, /* 02 - la1ic */
  74. 0x9f, /* 03 - ra1ic */
  75. 0x9f, /* 04 - la2ic */
  76. 0x9f, /* 05 - ra2ic */
  77. 0xbf, /* 06 - loc */
  78. 0xbf, /* 07 - roc */
  79. 0x20, /* 08 - dfr */
  80. AD1848_AUTOCALIB, /* 09 - ic */
  81. 0x00, /* 0a - pc */
  82. 0x00, /* 0b - ti */
  83. 0x00, /* 0c - mi */
  84. 0x00, /* 0d - lbc */
  85. 0x00, /* 0e - dru */
  86. 0x00, /* 0f - drl */
  87. };
  88. /*
  89. * Basic I/O functions
  90. */
  91. static void snd_ad1848_wait(struct snd_ad1848 *chip)
  92. {
  93. int timeout;
  94. for (timeout = 250; timeout > 0; timeout--) {
  95. if ((inb(AD1848P(chip, REGSEL)) & AD1848_INIT) == 0)
  96. break;
  97. udelay(100);
  98. }
  99. }
  100. void snd_ad1848_out(struct snd_ad1848 *chip,
  101. unsigned char reg,
  102. unsigned char value)
  103. {
  104. snd_ad1848_wait(chip);
  105. #ifdef CONFIG_SND_DEBUG
  106. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  107. snd_printk(KERN_WARNING "auto calibration time out - "
  108. "reg = 0x%x, value = 0x%x\n", reg, value);
  109. #endif
  110. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  111. outb(chip->image[reg] = value, AD1848P(chip, REG));
  112. mb();
  113. snd_printdd("codec out - reg 0x%x = 0x%x\n",
  114. chip->mce_bit | reg, value);
  115. }
  116. EXPORT_SYMBOL(snd_ad1848_out);
  117. static void snd_ad1848_dout(struct snd_ad1848 *chip,
  118. unsigned char reg, unsigned char value)
  119. {
  120. snd_ad1848_wait(chip);
  121. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  122. outb(value, AD1848P(chip, REG));
  123. mb();
  124. }
  125. static unsigned char snd_ad1848_in(struct snd_ad1848 *chip, unsigned char reg)
  126. {
  127. snd_ad1848_wait(chip);
  128. #ifdef CONFIG_SND_DEBUG
  129. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  130. snd_printk(KERN_WARNING "auto calibration time out - "
  131. "reg = 0x%x\n", reg);
  132. #endif
  133. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  134. mb();
  135. return inb(AD1848P(chip, REG));
  136. }
  137. #if 0
  138. static void snd_ad1848_debug(struct snd_ad1848 *chip)
  139. {
  140. printk("AD1848 REGS: INDEX = 0x%02x ", inb(AD1848P(chip, REGSEL)));
  141. printk(" STATUS = 0x%02x\n", inb(AD1848P(chip, STATUS)));
  142. printk(" 0x00: left input = 0x%02x ", snd_ad1848_in(chip, 0x00));
  143. printk(" 0x08: playback format = 0x%02x\n", snd_ad1848_in(chip, 0x08));
  144. printk(" 0x01: right input = 0x%02x ", snd_ad1848_in(chip, 0x01));
  145. printk(" 0x09: iface (CFIG 1) = 0x%02x\n", snd_ad1848_in(chip, 0x09));
  146. printk(" 0x02: AUXA left = 0x%02x ", snd_ad1848_in(chip, 0x02));
  147. printk(" 0x0a: pin control = 0x%02x\n", snd_ad1848_in(chip, 0x0a));
  148. printk(" 0x03: AUXA right = 0x%02x ", snd_ad1848_in(chip, 0x03));
  149. printk(" 0x0b: init & status = 0x%02x\n", snd_ad1848_in(chip, 0x0b));
  150. printk(" 0x04: AUXB left = 0x%02x ", snd_ad1848_in(chip, 0x04));
  151. printk(" 0x0c: revision & mode = 0x%02x\n", snd_ad1848_in(chip, 0x0c));
  152. printk(" 0x05: AUXB right = 0x%02x ", snd_ad1848_in(chip, 0x05));
  153. printk(" 0x0d: loopback = 0x%02x\n", snd_ad1848_in(chip, 0x0d));
  154. printk(" 0x06: left output = 0x%02x ", snd_ad1848_in(chip, 0x06));
  155. printk(" 0x0e: data upr count = 0x%02x\n", snd_ad1848_in(chip, 0x0e));
  156. printk(" 0x07: right output = 0x%02x ", snd_ad1848_in(chip, 0x07));
  157. printk(" 0x0f: data lwr count = 0x%02x\n", snd_ad1848_in(chip, 0x0f));
  158. }
  159. #endif
  160. /*
  161. * AD1848 detection / MCE routines
  162. */
  163. static void snd_ad1848_mce_up(struct snd_ad1848 *chip)
  164. {
  165. unsigned long flags;
  166. int timeout;
  167. snd_ad1848_wait(chip);
  168. #ifdef CONFIG_SND_DEBUG
  169. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  170. snd_printk(KERN_WARNING "mce_up - auto calibration time out (0)\n");
  171. #endif
  172. spin_lock_irqsave(&chip->reg_lock, flags);
  173. chip->mce_bit |= AD1848_MCE;
  174. timeout = inb(AD1848P(chip, REGSEL));
  175. if (timeout == 0x80)
  176. snd_printk(KERN_WARNING "mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
  177. if (!(timeout & AD1848_MCE))
  178. outb(chip->mce_bit | (timeout & 0x1f), AD1848P(chip, REGSEL));
  179. spin_unlock_irqrestore(&chip->reg_lock, flags);
  180. }
  181. static void snd_ad1848_mce_down(struct snd_ad1848 *chip)
  182. {
  183. unsigned long flags, timeout;
  184. int reg;
  185. spin_lock_irqsave(&chip->reg_lock, flags);
  186. for (timeout = 5; timeout > 0; timeout--)
  187. inb(AD1848P(chip, REGSEL));
  188. /* end of cleanup sequence */
  189. for (timeout = 12000; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  190. udelay(100);
  191. snd_printdd("(1) timeout = %d\n", timeout);
  192. #ifdef CONFIG_SND_DEBUG
  193. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  194. snd_printk(KERN_WARNING "mce_down [0x%lx] - auto calibration time out (0)\n", AD1848P(chip, REGSEL));
  195. #endif
  196. chip->mce_bit &= ~AD1848_MCE;
  197. reg = inb(AD1848P(chip, REGSEL));
  198. outb(chip->mce_bit | (reg & 0x1f), AD1848P(chip, REGSEL));
  199. if (reg == 0x80)
  200. snd_printk(KERN_WARNING "mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  201. if ((reg & AD1848_MCE) == 0) {
  202. spin_unlock_irqrestore(&chip->reg_lock, flags);
  203. return;
  204. }
  205. /*
  206. * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
  207. * It may take up to 5 sample periods (at most 907 us @ 5.5125 kHz) for
  208. * the process to _start_, so it is important to wait at least that long
  209. * before checking. Otherwise we might think AC has finished when it
  210. * has in fact not begun. It could take 128 (no AC) or 384 (AC) cycles
  211. * for ACI to drop. This gives a wait of at most 70 ms with a more
  212. * typical value of 3-9 ms.
  213. */
  214. timeout = jiffies + msecs_to_jiffies(250);
  215. do {
  216. spin_unlock_irqrestore(&chip->reg_lock, flags);
  217. msleep(1);
  218. spin_lock_irqsave(&chip->reg_lock, flags);
  219. reg = snd_ad1848_in(chip, AD1848_TEST_INIT) &
  220. AD1848_CALIB_IN_PROGRESS;
  221. } while (reg && time_before(jiffies, timeout));
  222. spin_unlock_irqrestore(&chip->reg_lock, flags);
  223. if (reg)
  224. snd_printk(KERN_ERR
  225. "mce_down - auto calibration time out (2)\n");
  226. snd_printdd("(4) jiffies = %lu\n", jiffies);
  227. snd_printd("mce_down - exit = 0x%x\n", inb(AD1848P(chip, REGSEL)));
  228. }
  229. static unsigned int snd_ad1848_get_count(unsigned char format,
  230. unsigned int size)
  231. {
  232. switch (format & 0xe0) {
  233. case AD1848_LINEAR_16:
  234. size >>= 1;
  235. break;
  236. }
  237. if (format & AD1848_STEREO)
  238. size >>= 1;
  239. return size;
  240. }
  241. static int snd_ad1848_trigger(struct snd_ad1848 *chip, unsigned char what,
  242. int channel, int cmd)
  243. {
  244. int result = 0;
  245. #if 0
  246. printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, inb(AD1848P(card, STATUS)));
  247. #endif
  248. spin_lock(&chip->reg_lock);
  249. if (cmd == SNDRV_PCM_TRIGGER_START) {
  250. if (chip->image[AD1848_IFACE_CTRL] & what) {
  251. spin_unlock(&chip->reg_lock);
  252. return 0;
  253. }
  254. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL] |= what);
  255. chip->mode |= AD1848_MODE_RUNNING;
  256. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  257. if (!(chip->image[AD1848_IFACE_CTRL] & what)) {
  258. spin_unlock(&chip->reg_lock);
  259. return 0;
  260. }
  261. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL] &= ~what);
  262. chip->mode &= ~AD1848_MODE_RUNNING;
  263. } else {
  264. result = -EINVAL;
  265. }
  266. spin_unlock(&chip->reg_lock);
  267. return result;
  268. }
  269. /*
  270. * CODEC I/O
  271. */
  272. static unsigned char snd_ad1848_get_rate(unsigned int rate)
  273. {
  274. int i;
  275. for (i = 0; i < ARRAY_SIZE(rates); i++)
  276. if (rate == rates[i])
  277. return freq_bits[i];
  278. snd_BUG();
  279. return freq_bits[ARRAY_SIZE(rates) - 1];
  280. }
  281. static int snd_ad1848_ioctl(struct snd_pcm_substream *substream,
  282. unsigned int cmd, void *arg)
  283. {
  284. return snd_pcm_lib_ioctl(substream, cmd, arg);
  285. }
  286. static unsigned char snd_ad1848_get_format(int format, int channels)
  287. {
  288. unsigned char rformat;
  289. rformat = AD1848_LINEAR_8;
  290. switch (format) {
  291. case SNDRV_PCM_FORMAT_A_LAW: rformat = AD1848_ALAW_8; break;
  292. case SNDRV_PCM_FORMAT_MU_LAW: rformat = AD1848_ULAW_8; break;
  293. case SNDRV_PCM_FORMAT_S16_LE: rformat = AD1848_LINEAR_16; break;
  294. }
  295. if (channels > 1)
  296. rformat |= AD1848_STEREO;
  297. #if 0
  298. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  299. #endif
  300. return rformat;
  301. }
  302. static void snd_ad1848_calibrate_mute(struct snd_ad1848 *chip, int mute)
  303. {
  304. unsigned long flags;
  305. mute = mute ? 1 : 0;
  306. spin_lock_irqsave(&chip->reg_lock, flags);
  307. if (chip->calibrate_mute == mute) {
  308. spin_unlock_irqrestore(&chip->reg_lock, flags);
  309. return;
  310. }
  311. if (!mute) {
  312. snd_ad1848_dout(chip, AD1848_LEFT_INPUT, chip->image[AD1848_LEFT_INPUT]);
  313. snd_ad1848_dout(chip, AD1848_RIGHT_INPUT, chip->image[AD1848_RIGHT_INPUT]);
  314. }
  315. snd_ad1848_dout(chip, AD1848_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX1_LEFT_INPUT]);
  316. snd_ad1848_dout(chip, AD1848_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX1_RIGHT_INPUT]);
  317. snd_ad1848_dout(chip, AD1848_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX2_LEFT_INPUT]);
  318. snd_ad1848_dout(chip, AD1848_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX2_RIGHT_INPUT]);
  319. snd_ad1848_dout(chip, AD1848_LEFT_OUTPUT, mute ? 0x80 : chip->image[AD1848_LEFT_OUTPUT]);
  320. snd_ad1848_dout(chip, AD1848_RIGHT_OUTPUT, mute ? 0x80 : chip->image[AD1848_RIGHT_OUTPUT]);
  321. chip->calibrate_mute = mute;
  322. spin_unlock_irqrestore(&chip->reg_lock, flags);
  323. }
  324. static void snd_ad1848_set_data_format(struct snd_ad1848 *chip, struct snd_pcm_hw_params *hw_params)
  325. {
  326. if (hw_params == NULL) {
  327. chip->image[AD1848_DATA_FORMAT] = 0x20;
  328. } else {
  329. chip->image[AD1848_DATA_FORMAT] =
  330. snd_ad1848_get_format(params_format(hw_params), params_channels(hw_params)) |
  331. snd_ad1848_get_rate(params_rate(hw_params));
  332. }
  333. // snd_printk(">>> pmode = 0x%x, dfr = 0x%x\n", pstr->mode, chip->image[AD1848_DATA_FORMAT]);
  334. }
  335. static int snd_ad1848_open(struct snd_ad1848 *chip, unsigned int mode)
  336. {
  337. unsigned long flags;
  338. mutex_lock(&chip->open_mutex);
  339. if (chip->mode & AD1848_MODE_OPEN) {
  340. mutex_unlock(&chip->open_mutex);
  341. return -EAGAIN;
  342. }
  343. snd_ad1848_mce_down(chip);
  344. #ifdef SNDRV_DEBUG_MCE
  345. snd_printk("open: (1)\n");
  346. #endif
  347. snd_ad1848_mce_up(chip);
  348. spin_lock_irqsave(&chip->reg_lock, flags);
  349. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO |
  350. AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO |
  351. AD1848_CALIB_MODE);
  352. chip->image[AD1848_IFACE_CTRL] |= AD1848_AUTOCALIB;
  353. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL]);
  354. spin_unlock_irqrestore(&chip->reg_lock, flags);
  355. snd_ad1848_mce_down(chip);
  356. #ifdef SNDRV_DEBUG_MCE
  357. snd_printk("open: (2)\n");
  358. #endif
  359. snd_ad1848_set_data_format(chip, NULL);
  360. snd_ad1848_mce_up(chip);
  361. spin_lock_irqsave(&chip->reg_lock, flags);
  362. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  363. spin_unlock_irqrestore(&chip->reg_lock, flags);
  364. snd_ad1848_mce_down(chip);
  365. #ifdef SNDRV_DEBUG_MCE
  366. snd_printk("open: (3)\n");
  367. #endif
  368. /* ok. now enable and ack CODEC IRQ */
  369. spin_lock_irqsave(&chip->reg_lock, flags);
  370. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  371. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  372. chip->image[AD1848_PIN_CTRL] |= AD1848_IRQ_ENABLE;
  373. snd_ad1848_out(chip, AD1848_PIN_CTRL, chip->image[AD1848_PIN_CTRL]);
  374. spin_unlock_irqrestore(&chip->reg_lock, flags);
  375. chip->mode = mode;
  376. mutex_unlock(&chip->open_mutex);
  377. return 0;
  378. }
  379. static void snd_ad1848_close(struct snd_ad1848 *chip)
  380. {
  381. unsigned long flags;
  382. mutex_lock(&chip->open_mutex);
  383. if (!chip->mode) {
  384. mutex_unlock(&chip->open_mutex);
  385. return;
  386. }
  387. /* disable IRQ */
  388. spin_lock_irqsave(&chip->reg_lock, flags);
  389. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  390. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  391. chip->image[AD1848_PIN_CTRL] &= ~AD1848_IRQ_ENABLE;
  392. snd_ad1848_out(chip, AD1848_PIN_CTRL, chip->image[AD1848_PIN_CTRL]);
  393. spin_unlock_irqrestore(&chip->reg_lock, flags);
  394. /* now disable capture & playback */
  395. snd_ad1848_mce_up(chip);
  396. spin_lock_irqsave(&chip->reg_lock, flags);
  397. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO |
  398. AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO);
  399. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL]);
  400. spin_unlock_irqrestore(&chip->reg_lock, flags);
  401. snd_ad1848_mce_down(chip);
  402. /* clear IRQ again */
  403. spin_lock_irqsave(&chip->reg_lock, flags);
  404. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  405. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  406. spin_unlock_irqrestore(&chip->reg_lock, flags);
  407. chip->mode = 0;
  408. mutex_unlock(&chip->open_mutex);
  409. }
  410. /*
  411. * ok.. exported functions..
  412. */
  413. static int snd_ad1848_playback_trigger(struct snd_pcm_substream *substream,
  414. int cmd)
  415. {
  416. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  417. return snd_ad1848_trigger(chip, AD1848_PLAYBACK_ENABLE, SNDRV_PCM_STREAM_PLAYBACK, cmd);
  418. }
  419. static int snd_ad1848_capture_trigger(struct snd_pcm_substream *substream,
  420. int cmd)
  421. {
  422. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  423. return snd_ad1848_trigger(chip, AD1848_CAPTURE_ENABLE, SNDRV_PCM_STREAM_CAPTURE, cmd);
  424. }
  425. static int snd_ad1848_playback_hw_params(struct snd_pcm_substream *substream,
  426. struct snd_pcm_hw_params *hw_params)
  427. {
  428. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  429. unsigned long flags;
  430. int err;
  431. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  432. return err;
  433. snd_ad1848_calibrate_mute(chip, 1);
  434. snd_ad1848_set_data_format(chip, hw_params);
  435. snd_ad1848_mce_up(chip);
  436. spin_lock_irqsave(&chip->reg_lock, flags);
  437. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  438. spin_unlock_irqrestore(&chip->reg_lock, flags);
  439. snd_ad1848_mce_down(chip);
  440. snd_ad1848_calibrate_mute(chip, 0);
  441. return 0;
  442. }
  443. static int snd_ad1848_playback_hw_free(struct snd_pcm_substream *substream)
  444. {
  445. return snd_pcm_lib_free_pages(substream);
  446. }
  447. static int snd_ad1848_playback_prepare(struct snd_pcm_substream *substream)
  448. {
  449. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  450. struct snd_pcm_runtime *runtime = substream->runtime;
  451. unsigned long flags;
  452. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  453. unsigned int count = snd_pcm_lib_period_bytes(substream);
  454. chip->dma_size = size;
  455. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO);
  456. snd_dma_program(chip->dma, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
  457. count = snd_ad1848_get_count(chip->image[AD1848_DATA_FORMAT], count) - 1;
  458. spin_lock_irqsave(&chip->reg_lock, flags);
  459. snd_ad1848_out(chip, AD1848_DATA_LWR_CNT, (unsigned char) count);
  460. snd_ad1848_out(chip, AD1848_DATA_UPR_CNT, (unsigned char) (count >> 8));
  461. spin_unlock_irqrestore(&chip->reg_lock, flags);
  462. return 0;
  463. }
  464. static int snd_ad1848_capture_hw_params(struct snd_pcm_substream *substream,
  465. struct snd_pcm_hw_params *hw_params)
  466. {
  467. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  468. unsigned long flags;
  469. int err;
  470. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  471. return err;
  472. snd_ad1848_calibrate_mute(chip, 1);
  473. snd_ad1848_set_data_format(chip, hw_params);
  474. snd_ad1848_mce_up(chip);
  475. spin_lock_irqsave(&chip->reg_lock, flags);
  476. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  477. spin_unlock_irqrestore(&chip->reg_lock, flags);
  478. snd_ad1848_mce_down(chip);
  479. snd_ad1848_calibrate_mute(chip, 0);
  480. return 0;
  481. }
  482. static int snd_ad1848_capture_hw_free(struct snd_pcm_substream *substream)
  483. {
  484. return snd_pcm_lib_free_pages(substream);
  485. }
  486. static int snd_ad1848_capture_prepare(struct snd_pcm_substream *substream)
  487. {
  488. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  489. struct snd_pcm_runtime *runtime = substream->runtime;
  490. unsigned long flags;
  491. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  492. unsigned int count = snd_pcm_lib_period_bytes(substream);
  493. chip->dma_size = size;
  494. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO);
  495. snd_dma_program(chip->dma, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
  496. count = snd_ad1848_get_count(chip->image[AD1848_DATA_FORMAT], count) - 1;
  497. spin_lock_irqsave(&chip->reg_lock, flags);
  498. snd_ad1848_out(chip, AD1848_DATA_LWR_CNT, (unsigned char) count);
  499. snd_ad1848_out(chip, AD1848_DATA_UPR_CNT, (unsigned char) (count >> 8));
  500. spin_unlock_irqrestore(&chip->reg_lock, flags);
  501. return 0;
  502. }
  503. static irqreturn_t snd_ad1848_interrupt(int irq, void *dev_id)
  504. {
  505. struct snd_ad1848 *chip = dev_id;
  506. if ((chip->mode & AD1848_MODE_PLAY) && chip->playback_substream &&
  507. (chip->mode & AD1848_MODE_RUNNING))
  508. snd_pcm_period_elapsed(chip->playback_substream);
  509. if ((chip->mode & AD1848_MODE_CAPTURE) && chip->capture_substream &&
  510. (chip->mode & AD1848_MODE_RUNNING))
  511. snd_pcm_period_elapsed(chip->capture_substream);
  512. outb(0, AD1848P(chip, STATUS)); /* clear global interrupt bit */
  513. return IRQ_HANDLED;
  514. }
  515. static snd_pcm_uframes_t snd_ad1848_playback_pointer(struct snd_pcm_substream *substream)
  516. {
  517. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  518. size_t ptr;
  519. if (!(chip->image[AD1848_IFACE_CTRL] & AD1848_PLAYBACK_ENABLE))
  520. return 0;
  521. ptr = snd_dma_pointer(chip->dma, chip->dma_size);
  522. return bytes_to_frames(substream->runtime, ptr);
  523. }
  524. static snd_pcm_uframes_t snd_ad1848_capture_pointer(struct snd_pcm_substream *substream)
  525. {
  526. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  527. size_t ptr;
  528. if (!(chip->image[AD1848_IFACE_CTRL] & AD1848_CAPTURE_ENABLE))
  529. return 0;
  530. ptr = snd_dma_pointer(chip->dma, chip->dma_size);
  531. return bytes_to_frames(substream->runtime, ptr);
  532. }
  533. /*
  534. */
  535. static void snd_ad1848_thinkpad_twiddle(struct snd_ad1848 *chip, int on) {
  536. int tmp;
  537. if (!chip->thinkpad_flag) return;
  538. outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
  539. tmp = inb(AD1848_THINKPAD_CTL_PORT2);
  540. if (on)
  541. /* turn it on */
  542. tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
  543. else
  544. /* turn it off */
  545. tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
  546. outb(tmp, AD1848_THINKPAD_CTL_PORT2);
  547. }
  548. #ifdef CONFIG_PM
  549. static void snd_ad1848_suspend(struct snd_ad1848 *chip)
  550. {
  551. snd_pcm_suspend_all(chip->pcm);
  552. if (chip->thinkpad_flag)
  553. snd_ad1848_thinkpad_twiddle(chip, 0);
  554. }
  555. static void snd_ad1848_resume(struct snd_ad1848 *chip)
  556. {
  557. int i;
  558. if (chip->thinkpad_flag)
  559. snd_ad1848_thinkpad_twiddle(chip, 1);
  560. /* clear any pendings IRQ */
  561. inb(AD1848P(chip, STATUS));
  562. outb(0, AD1848P(chip, STATUS));
  563. mb();
  564. snd_ad1848_mce_down(chip);
  565. for (i = 0; i < 16; i++)
  566. snd_ad1848_out(chip, i, chip->image[i]);
  567. snd_ad1848_mce_up(chip);
  568. snd_ad1848_mce_down(chip);
  569. }
  570. #endif /* CONFIG_PM */
  571. static int snd_ad1848_probe(struct snd_ad1848 * chip)
  572. {
  573. unsigned long flags;
  574. int i, id, rev, ad1847;
  575. unsigned char *ptr;
  576. #if 0
  577. snd_ad1848_debug(chip);
  578. #endif
  579. id = ad1847 = 0;
  580. for (i = 0; i < 1000; i++) {
  581. mb();
  582. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  583. udelay(500);
  584. else {
  585. spin_lock_irqsave(&chip->reg_lock, flags);
  586. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x00);
  587. snd_ad1848_out(chip, AD1848_LEFT_INPUT, 0xaa);
  588. snd_ad1848_out(chip, AD1848_RIGHT_INPUT, 0x45);
  589. rev = snd_ad1848_in(chip, AD1848_RIGHT_INPUT);
  590. if (rev == 0x65) {
  591. spin_unlock_irqrestore(&chip->reg_lock, flags);
  592. id = 1;
  593. ad1847 = 1;
  594. break;
  595. }
  596. if (snd_ad1848_in(chip, AD1848_LEFT_INPUT) == 0xaa && rev == 0x45) {
  597. spin_unlock_irqrestore(&chip->reg_lock, flags);
  598. id = 1;
  599. break;
  600. }
  601. spin_unlock_irqrestore(&chip->reg_lock, flags);
  602. }
  603. }
  604. if (id != 1)
  605. return -ENODEV; /* no valid device found */
  606. if (chip->hardware == AD1848_HW_DETECT) {
  607. if (ad1847) {
  608. chip->hardware = AD1848_HW_AD1847;
  609. } else {
  610. chip->hardware = AD1848_HW_AD1848;
  611. rev = snd_ad1848_in(chip, AD1848_MISC_INFO);
  612. if (rev & 0x80) {
  613. chip->hardware = AD1848_HW_CS4248;
  614. } else if ((rev & 0x0f) == 0x0a) {
  615. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x40);
  616. for (i = 0; i < 16; ++i) {
  617. if (snd_ad1848_in(chip, i) != snd_ad1848_in(chip, i + 16)) {
  618. chip->hardware = AD1848_HW_CMI8330;
  619. break;
  620. }
  621. }
  622. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x00);
  623. }
  624. }
  625. }
  626. spin_lock_irqsave(&chip->reg_lock, flags);
  627. inb(AD1848P(chip, STATUS)); /* clear any pendings IRQ */
  628. outb(0, AD1848P(chip, STATUS));
  629. mb();
  630. spin_unlock_irqrestore(&chip->reg_lock, flags);
  631. chip->image[AD1848_MISC_INFO] = 0x00;
  632. chip->image[AD1848_IFACE_CTRL] =
  633. (chip->image[AD1848_IFACE_CTRL] & ~AD1848_SINGLE_DMA) | AD1848_SINGLE_DMA;
  634. ptr = (unsigned char *) &chip->image;
  635. snd_ad1848_mce_down(chip);
  636. spin_lock_irqsave(&chip->reg_lock, flags);
  637. for (i = 0; i < 16; i++) /* ok.. fill all AD1848 registers */
  638. snd_ad1848_out(chip, i, *ptr++);
  639. spin_unlock_irqrestore(&chip->reg_lock, flags);
  640. snd_ad1848_mce_up(chip);
  641. snd_ad1848_mce_down(chip);
  642. return 0; /* all things are ok.. */
  643. }
  644. /*
  645. */
  646. static struct snd_pcm_hardware snd_ad1848_playback =
  647. {
  648. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  649. SNDRV_PCM_INFO_MMAP_VALID),
  650. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  651. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE),
  652. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  653. .rate_min = 5510,
  654. .rate_max = 48000,
  655. .channels_min = 1,
  656. .channels_max = 2,
  657. .buffer_bytes_max = (128*1024),
  658. .period_bytes_min = 64,
  659. .period_bytes_max = (128*1024),
  660. .periods_min = 1,
  661. .periods_max = 1024,
  662. .fifo_size = 0,
  663. };
  664. static struct snd_pcm_hardware snd_ad1848_capture =
  665. {
  666. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  667. SNDRV_PCM_INFO_MMAP_VALID),
  668. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  669. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE),
  670. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  671. .rate_min = 5510,
  672. .rate_max = 48000,
  673. .channels_min = 1,
  674. .channels_max = 2,
  675. .buffer_bytes_max = (128*1024),
  676. .period_bytes_min = 64,
  677. .period_bytes_max = (128*1024),
  678. .periods_min = 1,
  679. .periods_max = 1024,
  680. .fifo_size = 0,
  681. };
  682. /*
  683. */
  684. static int snd_ad1848_playback_open(struct snd_pcm_substream *substream)
  685. {
  686. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  687. struct snd_pcm_runtime *runtime = substream->runtime;
  688. int err;
  689. if ((err = snd_ad1848_open(chip, AD1848_MODE_PLAY)) < 0)
  690. return err;
  691. chip->playback_substream = substream;
  692. runtime->hw = snd_ad1848_playback;
  693. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.buffer_bytes_max);
  694. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.period_bytes_max);
  695. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  696. return 0;
  697. }
  698. static int snd_ad1848_capture_open(struct snd_pcm_substream *substream)
  699. {
  700. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  701. struct snd_pcm_runtime *runtime = substream->runtime;
  702. int err;
  703. if ((err = snd_ad1848_open(chip, AD1848_MODE_CAPTURE)) < 0)
  704. return err;
  705. chip->capture_substream = substream;
  706. runtime->hw = snd_ad1848_capture;
  707. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.buffer_bytes_max);
  708. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.period_bytes_max);
  709. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  710. return 0;
  711. }
  712. static int snd_ad1848_playback_close(struct snd_pcm_substream *substream)
  713. {
  714. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  715. chip->mode &= ~AD1848_MODE_PLAY;
  716. chip->playback_substream = NULL;
  717. snd_ad1848_close(chip);
  718. return 0;
  719. }
  720. static int snd_ad1848_capture_close(struct snd_pcm_substream *substream)
  721. {
  722. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  723. chip->mode &= ~AD1848_MODE_CAPTURE;
  724. chip->capture_substream = NULL;
  725. snd_ad1848_close(chip);
  726. return 0;
  727. }
  728. static int snd_ad1848_free(struct snd_ad1848 *chip)
  729. {
  730. release_and_free_resource(chip->res_port);
  731. if (chip->irq >= 0)
  732. free_irq(chip->irq, (void *) chip);
  733. if (chip->dma >= 0) {
  734. snd_dma_disable(chip->dma);
  735. free_dma(chip->dma);
  736. }
  737. kfree(chip);
  738. return 0;
  739. }
  740. static int snd_ad1848_dev_free(struct snd_device *device)
  741. {
  742. struct snd_ad1848 *chip = device->device_data;
  743. return snd_ad1848_free(chip);
  744. }
  745. static const char *snd_ad1848_chip_id(struct snd_ad1848 *chip)
  746. {
  747. switch (chip->hardware) {
  748. case AD1848_HW_AD1847: return "AD1847";
  749. case AD1848_HW_AD1848: return "AD1848";
  750. case AD1848_HW_CS4248: return "CS4248";
  751. case AD1848_HW_CMI8330: return "CMI8330/C3D";
  752. default: return "???";
  753. }
  754. }
  755. int snd_ad1848_create(struct snd_card *card,
  756. unsigned long port,
  757. int irq, int dma,
  758. unsigned short hardware,
  759. struct snd_ad1848 ** rchip)
  760. {
  761. static struct snd_device_ops ops = {
  762. .dev_free = snd_ad1848_dev_free,
  763. };
  764. struct snd_ad1848 *chip;
  765. int err;
  766. *rchip = NULL;
  767. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  768. if (chip == NULL)
  769. return -ENOMEM;
  770. spin_lock_init(&chip->reg_lock);
  771. mutex_init(&chip->open_mutex);
  772. chip->card = card;
  773. chip->port = port;
  774. chip->irq = -1;
  775. chip->dma = -1;
  776. chip->hardware = hardware;
  777. memcpy(&chip->image, &snd_ad1848_original_image, sizeof(snd_ad1848_original_image));
  778. if ((chip->res_port = request_region(port, 4, "AD1848")) == NULL) {
  779. snd_printk(KERN_ERR "ad1848: can't grab port 0x%lx\n", port);
  780. snd_ad1848_free(chip);
  781. return -EBUSY;
  782. }
  783. if (request_irq(irq, snd_ad1848_interrupt, IRQF_DISABLED, "AD1848", (void *) chip)) {
  784. snd_printk(KERN_ERR "ad1848: can't grab IRQ %d\n", irq);
  785. snd_ad1848_free(chip);
  786. return -EBUSY;
  787. }
  788. chip->irq = irq;
  789. if (request_dma(dma, "AD1848")) {
  790. snd_printk(KERN_ERR "ad1848: can't grab DMA %d\n", dma);
  791. snd_ad1848_free(chip);
  792. return -EBUSY;
  793. }
  794. chip->dma = dma;
  795. if (hardware == AD1848_HW_THINKPAD) {
  796. chip->thinkpad_flag = 1;
  797. chip->hardware = AD1848_HW_DETECT; /* reset */
  798. snd_ad1848_thinkpad_twiddle(chip, 1);
  799. }
  800. if (snd_ad1848_probe(chip) < 0) {
  801. snd_ad1848_free(chip);
  802. return -ENODEV;
  803. }
  804. /* Register device */
  805. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  806. snd_ad1848_free(chip);
  807. return err;
  808. }
  809. #ifdef CONFIG_PM
  810. chip->suspend = snd_ad1848_suspend;
  811. chip->resume = snd_ad1848_resume;
  812. #endif
  813. *rchip = chip;
  814. return 0;
  815. }
  816. EXPORT_SYMBOL(snd_ad1848_create);
  817. static struct snd_pcm_ops snd_ad1848_playback_ops = {
  818. .open = snd_ad1848_playback_open,
  819. .close = snd_ad1848_playback_close,
  820. .ioctl = snd_ad1848_ioctl,
  821. .hw_params = snd_ad1848_playback_hw_params,
  822. .hw_free = snd_ad1848_playback_hw_free,
  823. .prepare = snd_ad1848_playback_prepare,
  824. .trigger = snd_ad1848_playback_trigger,
  825. .pointer = snd_ad1848_playback_pointer,
  826. };
  827. static struct snd_pcm_ops snd_ad1848_capture_ops = {
  828. .open = snd_ad1848_capture_open,
  829. .close = snd_ad1848_capture_close,
  830. .ioctl = snd_ad1848_ioctl,
  831. .hw_params = snd_ad1848_capture_hw_params,
  832. .hw_free = snd_ad1848_capture_hw_free,
  833. .prepare = snd_ad1848_capture_prepare,
  834. .trigger = snd_ad1848_capture_trigger,
  835. .pointer = snd_ad1848_capture_pointer,
  836. };
  837. int snd_ad1848_pcm(struct snd_ad1848 *chip, int device, struct snd_pcm **rpcm)
  838. {
  839. struct snd_pcm *pcm;
  840. int err;
  841. if ((err = snd_pcm_new(chip->card, "AD1848", device, 1, 1, &pcm)) < 0)
  842. return err;
  843. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ad1848_playback_ops);
  844. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ad1848_capture_ops);
  845. pcm->private_data = chip;
  846. pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  847. strcpy(pcm->name, snd_ad1848_chip_id(chip));
  848. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  849. snd_dma_isa_data(),
  850. 64*1024, chip->dma > 3 ? 128*1024 : 64*1024);
  851. chip->pcm = pcm;
  852. if (rpcm)
  853. *rpcm = pcm;
  854. return 0;
  855. }
  856. EXPORT_SYMBOL(snd_ad1848_pcm);
  857. const struct snd_pcm_ops *snd_ad1848_get_pcm_ops(int direction)
  858. {
  859. return direction == SNDRV_PCM_STREAM_PLAYBACK ?
  860. &snd_ad1848_playback_ops : &snd_ad1848_capture_ops;
  861. }
  862. EXPORT_SYMBOL(snd_ad1848_get_pcm_ops);
  863. /*
  864. * MIXER part
  865. */
  866. static int snd_ad1848_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  867. {
  868. static char *texts[4] = {
  869. "Line", "Aux", "Mic", "Mix"
  870. };
  871. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  872. uinfo->count = 2;
  873. uinfo->value.enumerated.items = 4;
  874. if (uinfo->value.enumerated.item > 3)
  875. uinfo->value.enumerated.item = 3;
  876. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  877. return 0;
  878. }
  879. static int snd_ad1848_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  880. {
  881. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  882. unsigned long flags;
  883. spin_lock_irqsave(&chip->reg_lock, flags);
  884. ucontrol->value.enumerated.item[0] = (chip->image[AD1848_LEFT_INPUT] & AD1848_MIXS_ALL) >> 6;
  885. ucontrol->value.enumerated.item[1] = (chip->image[AD1848_RIGHT_INPUT] & AD1848_MIXS_ALL) >> 6;
  886. spin_unlock_irqrestore(&chip->reg_lock, flags);
  887. return 0;
  888. }
  889. static int snd_ad1848_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  890. {
  891. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  892. unsigned long flags;
  893. unsigned short left, right;
  894. int change;
  895. if (ucontrol->value.enumerated.item[0] > 3 ||
  896. ucontrol->value.enumerated.item[1] > 3)
  897. return -EINVAL;
  898. left = ucontrol->value.enumerated.item[0] << 6;
  899. right = ucontrol->value.enumerated.item[1] << 6;
  900. spin_lock_irqsave(&chip->reg_lock, flags);
  901. left = (chip->image[AD1848_LEFT_INPUT] & ~AD1848_MIXS_ALL) | left;
  902. right = (chip->image[AD1848_RIGHT_INPUT] & ~AD1848_MIXS_ALL) | right;
  903. change = left != chip->image[AD1848_LEFT_INPUT] ||
  904. right != chip->image[AD1848_RIGHT_INPUT];
  905. snd_ad1848_out(chip, AD1848_LEFT_INPUT, left);
  906. snd_ad1848_out(chip, AD1848_RIGHT_INPUT, right);
  907. spin_unlock_irqrestore(&chip->reg_lock, flags);
  908. return change;
  909. }
  910. static int snd_ad1848_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  911. {
  912. int mask = (kcontrol->private_value >> 16) & 0xff;
  913. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  914. uinfo->count = 1;
  915. uinfo->value.integer.min = 0;
  916. uinfo->value.integer.max = mask;
  917. return 0;
  918. }
  919. static int snd_ad1848_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  920. {
  921. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  922. unsigned long flags;
  923. int reg = kcontrol->private_value & 0xff;
  924. int shift = (kcontrol->private_value >> 8) & 0xff;
  925. int mask = (kcontrol->private_value >> 16) & 0xff;
  926. int invert = (kcontrol->private_value >> 24) & 0xff;
  927. spin_lock_irqsave(&chip->reg_lock, flags);
  928. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  929. spin_unlock_irqrestore(&chip->reg_lock, flags);
  930. if (invert)
  931. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  932. return 0;
  933. }
  934. static int snd_ad1848_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  935. {
  936. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  937. unsigned long flags;
  938. int reg = kcontrol->private_value & 0xff;
  939. int shift = (kcontrol->private_value >> 8) & 0xff;
  940. int mask = (kcontrol->private_value >> 16) & 0xff;
  941. int invert = (kcontrol->private_value >> 24) & 0xff;
  942. int change;
  943. unsigned short val;
  944. val = (ucontrol->value.integer.value[0] & mask);
  945. if (invert)
  946. val = mask - val;
  947. val <<= shift;
  948. spin_lock_irqsave(&chip->reg_lock, flags);
  949. val = (chip->image[reg] & ~(mask << shift)) | val;
  950. change = val != chip->image[reg];
  951. snd_ad1848_out(chip, reg, val);
  952. spin_unlock_irqrestore(&chip->reg_lock, flags);
  953. return change;
  954. }
  955. static int snd_ad1848_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  956. {
  957. int mask = (kcontrol->private_value >> 24) & 0xff;
  958. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  959. uinfo->count = 2;
  960. uinfo->value.integer.min = 0;
  961. uinfo->value.integer.max = mask;
  962. return 0;
  963. }
  964. static int snd_ad1848_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  965. {
  966. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  967. unsigned long flags;
  968. int left_reg = kcontrol->private_value & 0xff;
  969. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  970. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  971. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  972. int mask = (kcontrol->private_value >> 24) & 0xff;
  973. int invert = (kcontrol->private_value >> 22) & 1;
  974. spin_lock_irqsave(&chip->reg_lock, flags);
  975. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  976. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  977. spin_unlock_irqrestore(&chip->reg_lock, flags);
  978. if (invert) {
  979. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  980. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  981. }
  982. return 0;
  983. }
  984. static int snd_ad1848_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  985. {
  986. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  987. unsigned long flags;
  988. int left_reg = kcontrol->private_value & 0xff;
  989. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  990. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  991. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  992. int mask = (kcontrol->private_value >> 24) & 0xff;
  993. int invert = (kcontrol->private_value >> 22) & 1;
  994. int change;
  995. unsigned short val1, val2;
  996. val1 = ucontrol->value.integer.value[0] & mask;
  997. val2 = ucontrol->value.integer.value[1] & mask;
  998. if (invert) {
  999. val1 = mask - val1;
  1000. val2 = mask - val2;
  1001. }
  1002. val1 <<= shift_left;
  1003. val2 <<= shift_right;
  1004. spin_lock_irqsave(&chip->reg_lock, flags);
  1005. if (left_reg != right_reg) {
  1006. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1007. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1008. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1009. snd_ad1848_out(chip, left_reg, val1);
  1010. snd_ad1848_out(chip, right_reg, val2);
  1011. } else {
  1012. val1 = (chip->image[left_reg] & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1013. change = val1 != chip->image[left_reg];
  1014. snd_ad1848_out(chip, left_reg, val1);
  1015. }
  1016. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1017. return change;
  1018. }
  1019. /*
  1020. */
  1021. int snd_ad1848_add_ctl_elem(struct snd_ad1848 *chip,
  1022. const struct ad1848_mix_elem *c)
  1023. {
  1024. static struct snd_kcontrol_new newctls[] = {
  1025. [AD1848_MIX_SINGLE] = {
  1026. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1027. .info = snd_ad1848_info_single,
  1028. .get = snd_ad1848_get_single,
  1029. .put = snd_ad1848_put_single,
  1030. },
  1031. [AD1848_MIX_DOUBLE] = {
  1032. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1033. .info = snd_ad1848_info_double,
  1034. .get = snd_ad1848_get_double,
  1035. .put = snd_ad1848_put_double,
  1036. },
  1037. [AD1848_MIX_CAPTURE] = {
  1038. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1039. .info = snd_ad1848_info_mux,
  1040. .get = snd_ad1848_get_mux,
  1041. .put = snd_ad1848_put_mux,
  1042. },
  1043. };
  1044. struct snd_kcontrol *ctl;
  1045. int err;
  1046. ctl = snd_ctl_new1(&newctls[c->type], chip);
  1047. if (! ctl)
  1048. return -ENOMEM;
  1049. strlcpy(ctl->id.name, c->name, sizeof(ctl->id.name));
  1050. ctl->id.index = c->index;
  1051. ctl->private_value = c->private_value;
  1052. if (c->tlv) {
  1053. ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  1054. ctl->tlv.p = c->tlv;
  1055. }
  1056. if ((err = snd_ctl_add(chip->card, ctl)) < 0)
  1057. return err;
  1058. return 0;
  1059. }
  1060. EXPORT_SYMBOL(snd_ad1848_add_ctl_elem);
  1061. static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
  1062. static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
  1063. static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
  1064. static struct ad1848_mix_elem snd_ad1848_controls[] = {
  1065. AD1848_DOUBLE("PCM Playback Switch", 0, AD1848_LEFT_OUTPUT, AD1848_RIGHT_OUTPUT, 7, 7, 1, 1),
  1066. AD1848_DOUBLE_TLV("PCM Playback Volume", 0, AD1848_LEFT_OUTPUT, AD1848_RIGHT_OUTPUT, 0, 0, 63, 1,
  1067. db_scale_6bit),
  1068. AD1848_DOUBLE("Aux Playback Switch", 0, AD1848_AUX1_LEFT_INPUT, AD1848_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1069. AD1848_DOUBLE_TLV("Aux Playback Volume", 0, AD1848_AUX1_LEFT_INPUT, AD1848_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
  1070. db_scale_5bit_12db_max),
  1071. AD1848_DOUBLE("Aux Playback Switch", 1, AD1848_AUX2_LEFT_INPUT, AD1848_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1072. AD1848_DOUBLE_TLV("Aux Playback Volume", 1, AD1848_AUX2_LEFT_INPUT, AD1848_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
  1073. db_scale_5bit_12db_max),
  1074. AD1848_DOUBLE_TLV("Capture Volume", 0, AD1848_LEFT_INPUT, AD1848_RIGHT_INPUT, 0, 0, 15, 0,
  1075. db_scale_rec_gain),
  1076. {
  1077. .name = "Capture Source",
  1078. .type = AD1848_MIX_CAPTURE,
  1079. },
  1080. AD1848_SINGLE("Loopback Capture Switch", 0, AD1848_LOOPBACK, 0, 1, 0),
  1081. AD1848_SINGLE_TLV("Loopback Capture Volume", 0, AD1848_LOOPBACK, 1, 63, 0,
  1082. db_scale_6bit),
  1083. };
  1084. int snd_ad1848_mixer(struct snd_ad1848 *chip)
  1085. {
  1086. struct snd_card *card;
  1087. struct snd_pcm *pcm;
  1088. unsigned int idx;
  1089. int err;
  1090. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1091. pcm = chip->pcm;
  1092. card = chip->card;
  1093. strcpy(card->mixername, pcm->name);
  1094. for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++)
  1095. if ((err = snd_ad1848_add_ctl_elem(chip, &snd_ad1848_controls[idx])) < 0)
  1096. return err;
  1097. return 0;
  1098. }
  1099. EXPORT_SYMBOL(snd_ad1848_mixer);
  1100. /*
  1101. * INIT part
  1102. */
  1103. static int __init alsa_ad1848_init(void)
  1104. {
  1105. return 0;
  1106. }
  1107. static void __exit alsa_ad1848_exit(void)
  1108. {
  1109. }
  1110. module_init(alsa_ad1848_init)
  1111. module_exit(alsa_ad1848_exit)