iwl-4965.c 142 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include "iwl-4965.h"
  40. #include "iwl-helpers.h"
  41. static void iwl4965_hw_card_show_info(struct iwl4965_priv *priv);
  42. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  43. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  44. IWL_RATE_SISO_##s##M_PLCP, \
  45. IWL_RATE_MIMO_##s##M_PLCP, \
  46. IWL_RATE_##r##M_IEEE, \
  47. IWL_RATE_##ip##M_INDEX, \
  48. IWL_RATE_##in##M_INDEX, \
  49. IWL_RATE_##rp##M_INDEX, \
  50. IWL_RATE_##rn##M_INDEX, \
  51. IWL_RATE_##pp##M_INDEX, \
  52. IWL_RATE_##np##M_INDEX }
  53. /*
  54. * Parameter order:
  55. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  56. *
  57. * If there isn't a valid next or previous rate then INV is used which
  58. * maps to IWL_RATE_INVALID
  59. *
  60. */
  61. const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
  62. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  63. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  64. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  65. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  66. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  67. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  68. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  69. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  70. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  71. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  72. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  73. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  74. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  75. };
  76. #ifdef CONFIG_IWL4965_HT
  77. static const u16 default_tid_to_tx_fifo[] = {
  78. IWL_TX_FIFO_AC1,
  79. IWL_TX_FIFO_AC0,
  80. IWL_TX_FIFO_AC0,
  81. IWL_TX_FIFO_AC1,
  82. IWL_TX_FIFO_AC2,
  83. IWL_TX_FIFO_AC2,
  84. IWL_TX_FIFO_AC3,
  85. IWL_TX_FIFO_AC3,
  86. IWL_TX_FIFO_NONE,
  87. IWL_TX_FIFO_NONE,
  88. IWL_TX_FIFO_NONE,
  89. IWL_TX_FIFO_NONE,
  90. IWL_TX_FIFO_NONE,
  91. IWL_TX_FIFO_NONE,
  92. IWL_TX_FIFO_NONE,
  93. IWL_TX_FIFO_NONE,
  94. IWL_TX_FIFO_AC3
  95. };
  96. #endif /*CONFIG_IWL4965_HT */
  97. static int is_fat_channel(__le32 rxon_flags)
  98. {
  99. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  100. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  101. }
  102. static u8 is_single_stream(struct iwl4965_priv *priv)
  103. {
  104. #ifdef CONFIG_IWL4965_HT
  105. if (!priv->current_ht_config.is_ht ||
  106. (priv->current_ht_config.supp_mcs_set[1] == 0) ||
  107. (priv->ps_mode == IWL_MIMO_PS_STATIC))
  108. return 1;
  109. #else
  110. return 1;
  111. #endif /*CONFIG_IWL4965_HT */
  112. return 0;
  113. }
  114. /*
  115. * Determine how many receiver/antenna chains to use.
  116. * More provides better reception via diversity. Fewer saves power.
  117. * MIMO (dual stream) requires at least 2, but works better with 3.
  118. * This does not determine *which* chains to use, just how many.
  119. */
  120. static int iwl4965_get_rx_chain_counter(struct iwl4965_priv *priv,
  121. u8 *idle_state, u8 *rx_state)
  122. {
  123. u8 is_single = is_single_stream(priv);
  124. u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
  125. /* # of Rx chains to use when expecting MIMO. */
  126. if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
  127. *rx_state = 2;
  128. else
  129. *rx_state = 3;
  130. /* # Rx chains when idling and maybe trying to save power */
  131. switch (priv->ps_mode) {
  132. case IWL_MIMO_PS_STATIC:
  133. case IWL_MIMO_PS_DYNAMIC:
  134. *idle_state = (is_cam) ? 2 : 1;
  135. break;
  136. case IWL_MIMO_PS_NONE:
  137. *idle_state = (is_cam) ? *rx_state : 1;
  138. break;
  139. default:
  140. *idle_state = 1;
  141. break;
  142. }
  143. return 0;
  144. }
  145. int iwl4965_hw_rxq_stop(struct iwl4965_priv *priv)
  146. {
  147. int rc;
  148. unsigned long flags;
  149. spin_lock_irqsave(&priv->lock, flags);
  150. rc = iwl4965_grab_nic_access(priv);
  151. if (rc) {
  152. spin_unlock_irqrestore(&priv->lock, flags);
  153. return rc;
  154. }
  155. /* stop Rx DMA */
  156. iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  157. rc = iwl4965_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  158. (1 << 24), 1000);
  159. if (rc < 0)
  160. IWL_ERROR("Can't stop Rx DMA.\n");
  161. iwl4965_release_nic_access(priv);
  162. spin_unlock_irqrestore(&priv->lock, flags);
  163. return 0;
  164. }
  165. u8 iwl4965_hw_find_station(struct iwl4965_priv *priv, const u8 *addr)
  166. {
  167. int i;
  168. int start = 0;
  169. int ret = IWL_INVALID_STATION;
  170. unsigned long flags;
  171. DECLARE_MAC_BUF(mac);
  172. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
  173. (priv->iw_mode == IEEE80211_IF_TYPE_AP))
  174. start = IWL_STA_ID;
  175. if (is_broadcast_ether_addr(addr))
  176. return IWL4965_BROADCAST_ID;
  177. spin_lock_irqsave(&priv->sta_lock, flags);
  178. for (i = start; i < priv->hw_setting.max_stations; i++)
  179. if ((priv->stations[i].used) &&
  180. (!compare_ether_addr
  181. (priv->stations[i].sta.sta.addr, addr))) {
  182. ret = i;
  183. goto out;
  184. }
  185. IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
  186. print_mac(mac, addr), priv->num_stations);
  187. out:
  188. spin_unlock_irqrestore(&priv->sta_lock, flags);
  189. return ret;
  190. }
  191. static int iwl4965_nic_set_pwr_src(struct iwl4965_priv *priv, int pwr_max)
  192. {
  193. int ret;
  194. unsigned long flags;
  195. spin_lock_irqsave(&priv->lock, flags);
  196. ret = iwl4965_grab_nic_access(priv);
  197. if (ret) {
  198. spin_unlock_irqrestore(&priv->lock, flags);
  199. return ret;
  200. }
  201. if (!pwr_max) {
  202. u32 val;
  203. ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  204. &val);
  205. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
  206. iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  207. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  208. ~APMG_PS_CTRL_MSK_PWR_SRC);
  209. } else
  210. iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  211. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  212. ~APMG_PS_CTRL_MSK_PWR_SRC);
  213. iwl4965_release_nic_access(priv);
  214. spin_unlock_irqrestore(&priv->lock, flags);
  215. return ret;
  216. }
  217. static int iwl4965_rx_init(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq)
  218. {
  219. int rc;
  220. unsigned long flags;
  221. unsigned int rb_size;
  222. spin_lock_irqsave(&priv->lock, flags);
  223. rc = iwl4965_grab_nic_access(priv);
  224. if (rc) {
  225. spin_unlock_irqrestore(&priv->lock, flags);
  226. return rc;
  227. }
  228. if (iwl4965_param_amsdu_size_8K)
  229. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  230. else
  231. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  232. /* Stop Rx DMA */
  233. iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  234. /* Reset driver's Rx queue write index */
  235. iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  236. /* Tell device where to find RBD circular buffer in DRAM */
  237. iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  238. rxq->dma_addr >> 8);
  239. /* Tell device where in DRAM to update its Rx status */
  240. iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  241. (priv->hw_setting.shared_phys +
  242. offsetof(struct iwl4965_shared, val0)) >> 4);
  243. /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
  244. iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  245. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  246. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  247. rb_size |
  248. /*0x10 << 4 | */
  249. (RX_QUEUE_SIZE_LOG <<
  250. FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
  251. /*
  252. * iwl4965_write32(priv,CSR_INT_COAL_REG,0);
  253. */
  254. iwl4965_release_nic_access(priv);
  255. spin_unlock_irqrestore(&priv->lock, flags);
  256. return 0;
  257. }
  258. /* Tell 4965 where to find the "keep warm" buffer */
  259. static int iwl4965_kw_init(struct iwl4965_priv *priv)
  260. {
  261. unsigned long flags;
  262. int rc;
  263. spin_lock_irqsave(&priv->lock, flags);
  264. rc = iwl4965_grab_nic_access(priv);
  265. if (rc)
  266. goto out;
  267. iwl4965_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
  268. priv->kw.dma_addr >> 4);
  269. iwl4965_release_nic_access(priv);
  270. out:
  271. spin_unlock_irqrestore(&priv->lock, flags);
  272. return rc;
  273. }
  274. static int iwl4965_kw_alloc(struct iwl4965_priv *priv)
  275. {
  276. struct pci_dev *dev = priv->pci_dev;
  277. struct iwl4965_kw *kw = &priv->kw;
  278. kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
  279. kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
  280. if (!kw->v_addr)
  281. return -ENOMEM;
  282. return 0;
  283. }
  284. #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
  285. ? # x " " : "")
  286. /**
  287. * iwl4965_set_fat_chan_info - Copy fat channel info into driver's priv.
  288. *
  289. * Does not set up a command, or touch hardware.
  290. */
  291. int iwl4965_set_fat_chan_info(struct iwl4965_priv *priv, int phymode, u16 channel,
  292. const struct iwl4965_eeprom_channel *eeprom_ch,
  293. u8 fat_extension_channel)
  294. {
  295. struct iwl4965_channel_info *ch_info;
  296. ch_info = (struct iwl4965_channel_info *)
  297. iwl4965_get_channel_info(priv, phymode, channel);
  298. if (!is_channel_valid(ch_info))
  299. return -1;
  300. IWL_DEBUG_INFO("FAT Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  301. " %ddBm): Ad-Hoc %ssupported\n",
  302. ch_info->channel,
  303. is_channel_a_band(ch_info) ?
  304. "5.2" : "2.4",
  305. CHECK_AND_PRINT(IBSS),
  306. CHECK_AND_PRINT(ACTIVE),
  307. CHECK_AND_PRINT(RADAR),
  308. CHECK_AND_PRINT(WIDE),
  309. CHECK_AND_PRINT(NARROW),
  310. CHECK_AND_PRINT(DFS),
  311. eeprom_ch->flags,
  312. eeprom_ch->max_power_avg,
  313. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
  314. && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
  315. "" : "not ");
  316. ch_info->fat_eeprom = *eeprom_ch;
  317. ch_info->fat_max_power_avg = eeprom_ch->max_power_avg;
  318. ch_info->fat_curr_txpow = eeprom_ch->max_power_avg;
  319. ch_info->fat_min_power = 0;
  320. ch_info->fat_scan_power = eeprom_ch->max_power_avg;
  321. ch_info->fat_flags = eeprom_ch->flags;
  322. ch_info->fat_extension_channel = fat_extension_channel;
  323. return 0;
  324. }
  325. /**
  326. * iwl4965_kw_free - Free the "keep warm" buffer
  327. */
  328. static void iwl4965_kw_free(struct iwl4965_priv *priv)
  329. {
  330. struct pci_dev *dev = priv->pci_dev;
  331. struct iwl4965_kw *kw = &priv->kw;
  332. if (kw->v_addr) {
  333. pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
  334. memset(kw, 0, sizeof(*kw));
  335. }
  336. }
  337. /**
  338. * iwl4965_txq_ctx_reset - Reset TX queue context
  339. * Destroys all DMA structures and initialise them again
  340. *
  341. * @param priv
  342. * @return error code
  343. */
  344. static int iwl4965_txq_ctx_reset(struct iwl4965_priv *priv)
  345. {
  346. int rc = 0;
  347. int txq_id, slots_num;
  348. unsigned long flags;
  349. iwl4965_kw_free(priv);
  350. /* Free all tx/cmd queues and keep-warm buffer */
  351. iwl4965_hw_txq_ctx_free(priv);
  352. /* Alloc keep-warm buffer */
  353. rc = iwl4965_kw_alloc(priv);
  354. if (rc) {
  355. IWL_ERROR("Keep Warm allocation failed");
  356. goto error_kw;
  357. }
  358. spin_lock_irqsave(&priv->lock, flags);
  359. rc = iwl4965_grab_nic_access(priv);
  360. if (unlikely(rc)) {
  361. IWL_ERROR("TX reset failed");
  362. spin_unlock_irqrestore(&priv->lock, flags);
  363. goto error_reset;
  364. }
  365. /* Turn off all Tx DMA channels */
  366. iwl4965_write_prph(priv, KDR_SCD_TXFACT, 0);
  367. iwl4965_release_nic_access(priv);
  368. spin_unlock_irqrestore(&priv->lock, flags);
  369. /* Tell 4965 where to find the keep-warm buffer */
  370. rc = iwl4965_kw_init(priv);
  371. if (rc) {
  372. IWL_ERROR("kw_init failed\n");
  373. goto error_reset;
  374. }
  375. /* Alloc and init all (default 16) Tx queues,
  376. * including the command queue (#4) */
  377. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  378. slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
  379. TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
  380. rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
  381. txq_id);
  382. if (rc) {
  383. IWL_ERROR("Tx %d queue init failed\n", txq_id);
  384. goto error;
  385. }
  386. }
  387. return rc;
  388. error:
  389. iwl4965_hw_txq_ctx_free(priv);
  390. error_reset:
  391. iwl4965_kw_free(priv);
  392. error_kw:
  393. return rc;
  394. }
  395. int iwl4965_hw_nic_init(struct iwl4965_priv *priv)
  396. {
  397. int rc;
  398. unsigned long flags;
  399. struct iwl4965_rx_queue *rxq = &priv->rxq;
  400. u8 rev_id;
  401. u32 val;
  402. u8 val_link;
  403. iwl4965_power_init_handle(priv);
  404. /* nic_init */
  405. spin_lock_irqsave(&priv->lock, flags);
  406. iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  407. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  408. iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  409. rc = iwl4965_poll_bit(priv, CSR_GP_CNTRL,
  410. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  411. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  412. if (rc < 0) {
  413. spin_unlock_irqrestore(&priv->lock, flags);
  414. IWL_DEBUG_INFO("Failed to init the card\n");
  415. return rc;
  416. }
  417. rc = iwl4965_grab_nic_access(priv);
  418. if (rc) {
  419. spin_unlock_irqrestore(&priv->lock, flags);
  420. return rc;
  421. }
  422. iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
  423. iwl4965_write_prph(priv, APMG_CLK_CTRL_REG,
  424. APMG_CLK_VAL_DMA_CLK_RQT |
  425. APMG_CLK_VAL_BSM_CLK_RQT);
  426. iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
  427. udelay(20);
  428. iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  429. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  430. iwl4965_release_nic_access(priv);
  431. iwl4965_write32(priv, CSR_INT_COALESCING, 512 / 32);
  432. spin_unlock_irqrestore(&priv->lock, flags);
  433. /* Determine HW type */
  434. rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
  435. if (rc)
  436. return rc;
  437. IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
  438. iwl4965_nic_set_pwr_src(priv, 1);
  439. spin_lock_irqsave(&priv->lock, flags);
  440. if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
  441. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  442. /* Enable No Snoop field */
  443. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  444. val & ~(1 << 11));
  445. }
  446. spin_unlock_irqrestore(&priv->lock, flags);
  447. if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
  448. IWL_ERROR("Older EEPROM detected! Aborting.\n");
  449. return -EINVAL;
  450. }
  451. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  452. /* disable L1 entry -- workaround for pre-B1 */
  453. pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
  454. spin_lock_irqsave(&priv->lock, flags);
  455. /* set CSR_HW_CONFIG_REG for uCode use */
  456. iwl4965_set_bit(priv, CSR_SW_VER, CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R |
  457. CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  458. CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  459. rc = iwl4965_grab_nic_access(priv);
  460. if (rc < 0) {
  461. spin_unlock_irqrestore(&priv->lock, flags);
  462. IWL_DEBUG_INFO("Failed to init the card\n");
  463. return rc;
  464. }
  465. iwl4965_read_prph(priv, APMG_PS_CTRL_REG);
  466. iwl4965_set_bits_prph(priv, APMG_PS_CTRL_REG,
  467. APMG_PS_CTRL_VAL_RESET_REQ);
  468. udelay(5);
  469. iwl4965_clear_bits_prph(priv, APMG_PS_CTRL_REG,
  470. APMG_PS_CTRL_VAL_RESET_REQ);
  471. iwl4965_release_nic_access(priv);
  472. spin_unlock_irqrestore(&priv->lock, flags);
  473. iwl4965_hw_card_show_info(priv);
  474. /* end nic_init */
  475. /* Allocate the RX queue, or reset if it is already allocated */
  476. if (!rxq->bd) {
  477. rc = iwl4965_rx_queue_alloc(priv);
  478. if (rc) {
  479. IWL_ERROR("Unable to initialize Rx queue\n");
  480. return -ENOMEM;
  481. }
  482. } else
  483. iwl4965_rx_queue_reset(priv, rxq);
  484. iwl4965_rx_replenish(priv);
  485. iwl4965_rx_init(priv, rxq);
  486. spin_lock_irqsave(&priv->lock, flags);
  487. rxq->need_update = 1;
  488. iwl4965_rx_queue_update_write_ptr(priv, rxq);
  489. spin_unlock_irqrestore(&priv->lock, flags);
  490. /* Allocate and init all Tx and Command queues */
  491. rc = iwl4965_txq_ctx_reset(priv);
  492. if (rc)
  493. return rc;
  494. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
  495. IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
  496. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
  497. IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
  498. set_bit(STATUS_INIT, &priv->status);
  499. return 0;
  500. }
  501. int iwl4965_hw_nic_stop_master(struct iwl4965_priv *priv)
  502. {
  503. int rc = 0;
  504. u32 reg_val;
  505. unsigned long flags;
  506. spin_lock_irqsave(&priv->lock, flags);
  507. /* set stop master bit */
  508. iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  509. reg_val = iwl4965_read32(priv, CSR_GP_CNTRL);
  510. if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
  511. (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
  512. IWL_DEBUG_INFO("Card in power save, master is already "
  513. "stopped\n");
  514. else {
  515. rc = iwl4965_poll_bit(priv, CSR_RESET,
  516. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  517. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  518. if (rc < 0) {
  519. spin_unlock_irqrestore(&priv->lock, flags);
  520. return rc;
  521. }
  522. }
  523. spin_unlock_irqrestore(&priv->lock, flags);
  524. IWL_DEBUG_INFO("stop master\n");
  525. return rc;
  526. }
  527. /**
  528. * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
  529. */
  530. void iwl4965_hw_txq_ctx_stop(struct iwl4965_priv *priv)
  531. {
  532. int txq_id;
  533. unsigned long flags;
  534. /* Stop each Tx DMA channel, and wait for it to be idle */
  535. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  536. spin_lock_irqsave(&priv->lock, flags);
  537. if (iwl4965_grab_nic_access(priv)) {
  538. spin_unlock_irqrestore(&priv->lock, flags);
  539. continue;
  540. }
  541. iwl4965_write_direct32(priv,
  542. IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
  543. 0x0);
  544. iwl4965_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
  545. IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
  546. (txq_id), 200);
  547. iwl4965_release_nic_access(priv);
  548. spin_unlock_irqrestore(&priv->lock, flags);
  549. }
  550. /* Deallocate memory for all Tx queues */
  551. iwl4965_hw_txq_ctx_free(priv);
  552. }
  553. int iwl4965_hw_nic_reset(struct iwl4965_priv *priv)
  554. {
  555. int rc = 0;
  556. unsigned long flags;
  557. iwl4965_hw_nic_stop_master(priv);
  558. spin_lock_irqsave(&priv->lock, flags);
  559. iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  560. udelay(10);
  561. iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  562. rc = iwl4965_poll_bit(priv, CSR_RESET,
  563. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  564. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  565. udelay(10);
  566. rc = iwl4965_grab_nic_access(priv);
  567. if (!rc) {
  568. iwl4965_write_prph(priv, APMG_CLK_EN_REG,
  569. APMG_CLK_VAL_DMA_CLK_RQT |
  570. APMG_CLK_VAL_BSM_CLK_RQT);
  571. udelay(10);
  572. iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  573. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  574. iwl4965_release_nic_access(priv);
  575. }
  576. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  577. wake_up_interruptible(&priv->wait_command_queue);
  578. spin_unlock_irqrestore(&priv->lock, flags);
  579. return rc;
  580. }
  581. #define REG_RECALIB_PERIOD (60)
  582. /**
  583. * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
  584. *
  585. * This callback is provided in order to queue the statistics_work
  586. * in work_queue context (v. softirq)
  587. *
  588. * This timer function is continually reset to execute within
  589. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  590. * was received. We need to ensure we receive the statistics in order
  591. * to update the temperature used for calibrating the TXPOWER. However,
  592. * we can't send the statistics command from softirq context (which
  593. * is the context which timers run at) so we have to queue off the
  594. * statistics_work to actually send the command to the hardware.
  595. */
  596. static void iwl4965_bg_statistics_periodic(unsigned long data)
  597. {
  598. struct iwl4965_priv *priv = (struct iwl4965_priv *)data;
  599. queue_work(priv->workqueue, &priv->statistics_work);
  600. }
  601. /**
  602. * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
  603. *
  604. * This is queued by iwl4965_bg_statistics_periodic.
  605. */
  606. static void iwl4965_bg_statistics_work(struct work_struct *work)
  607. {
  608. struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
  609. statistics_work);
  610. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  611. return;
  612. mutex_lock(&priv->mutex);
  613. iwl4965_send_statistics_request(priv);
  614. mutex_unlock(&priv->mutex);
  615. }
  616. #define CT_LIMIT_CONST 259
  617. #define TM_CT_KILL_THRESHOLD 110
  618. void iwl4965_rf_kill_ct_config(struct iwl4965_priv *priv)
  619. {
  620. struct iwl4965_ct_kill_config cmd;
  621. u32 R1, R2, R3;
  622. u32 temp_th;
  623. u32 crit_temperature;
  624. unsigned long flags;
  625. int rc = 0;
  626. spin_lock_irqsave(&priv->lock, flags);
  627. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  628. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  629. spin_unlock_irqrestore(&priv->lock, flags);
  630. if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
  631. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  632. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  633. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  634. } else {
  635. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  636. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  637. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  638. }
  639. temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
  640. crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
  641. cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
  642. rc = iwl4965_send_cmd_pdu(priv,
  643. REPLY_CT_KILL_CONFIG_CMD, sizeof(cmd), &cmd);
  644. if (rc)
  645. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  646. else
  647. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
  648. }
  649. #ifdef CONFIG_IWL4965_SENSITIVITY
  650. /* "false alarms" are signals that our DSP tries to lock onto,
  651. * but then determines that they are either noise, or transmissions
  652. * from a distant wireless network (also "noise", really) that get
  653. * "stepped on" by stronger transmissions within our own network.
  654. * This algorithm attempts to set a sensitivity level that is high
  655. * enough to receive all of our own network traffic, but not so
  656. * high that our DSP gets too busy trying to lock onto non-network
  657. * activity/noise. */
  658. static int iwl4965_sens_energy_cck(struct iwl4965_priv *priv,
  659. u32 norm_fa,
  660. u32 rx_enable_time,
  661. struct statistics_general_data *rx_info)
  662. {
  663. u32 max_nrg_cck = 0;
  664. int i = 0;
  665. u8 max_silence_rssi = 0;
  666. u32 silence_ref = 0;
  667. u8 silence_rssi_a = 0;
  668. u8 silence_rssi_b = 0;
  669. u8 silence_rssi_c = 0;
  670. u32 val;
  671. /* "false_alarms" values below are cross-multiplications to assess the
  672. * numbers of false alarms within the measured period of actual Rx
  673. * (Rx is off when we're txing), vs the min/max expected false alarms
  674. * (some should be expected if rx is sensitive enough) in a
  675. * hypothetical listening period of 200 time units (TU), 204.8 msec:
  676. *
  677. * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
  678. *
  679. * */
  680. u32 false_alarms = norm_fa * 200 * 1024;
  681. u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
  682. u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
  683. struct iwl4965_sensitivity_data *data = NULL;
  684. data = &(priv->sensitivity_data);
  685. data->nrg_auto_corr_silence_diff = 0;
  686. /* Find max silence rssi among all 3 receivers.
  687. * This is background noise, which may include transmissions from other
  688. * networks, measured during silence before our network's beacon */
  689. silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
  690. ALL_BAND_FILTER) >> 8);
  691. silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
  692. ALL_BAND_FILTER) >> 8);
  693. silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
  694. ALL_BAND_FILTER) >> 8);
  695. val = max(silence_rssi_b, silence_rssi_c);
  696. max_silence_rssi = max(silence_rssi_a, (u8) val);
  697. /* Store silence rssi in 20-beacon history table */
  698. data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
  699. data->nrg_silence_idx++;
  700. if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
  701. data->nrg_silence_idx = 0;
  702. /* Find max silence rssi across 20 beacon history */
  703. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
  704. val = data->nrg_silence_rssi[i];
  705. silence_ref = max(silence_ref, val);
  706. }
  707. IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
  708. silence_rssi_a, silence_rssi_b, silence_rssi_c,
  709. silence_ref);
  710. /* Find max rx energy (min value!) among all 3 receivers,
  711. * measured during beacon frame.
  712. * Save it in 10-beacon history table. */
  713. i = data->nrg_energy_idx;
  714. val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
  715. data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
  716. data->nrg_energy_idx++;
  717. if (data->nrg_energy_idx >= 10)
  718. data->nrg_energy_idx = 0;
  719. /* Find min rx energy (max value) across 10 beacon history.
  720. * This is the minimum signal level that we want to receive well.
  721. * Add backoff (margin so we don't miss slightly lower energy frames).
  722. * This establishes an upper bound (min value) for energy threshold. */
  723. max_nrg_cck = data->nrg_value[0];
  724. for (i = 1; i < 10; i++)
  725. max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
  726. max_nrg_cck += 6;
  727. IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
  728. rx_info->beacon_energy_a, rx_info->beacon_energy_b,
  729. rx_info->beacon_energy_c, max_nrg_cck - 6);
  730. /* Count number of consecutive beacons with fewer-than-desired
  731. * false alarms. */
  732. if (false_alarms < min_false_alarms)
  733. data->num_in_cck_no_fa++;
  734. else
  735. data->num_in_cck_no_fa = 0;
  736. IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
  737. data->num_in_cck_no_fa);
  738. /* If we got too many false alarms this time, reduce sensitivity */
  739. if (false_alarms > max_false_alarms) {
  740. IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
  741. false_alarms, max_false_alarms);
  742. IWL_DEBUG_CALIB("... reducing sensitivity\n");
  743. data->nrg_curr_state = IWL_FA_TOO_MANY;
  744. if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
  745. /* Store for "fewer than desired" on later beacon */
  746. data->nrg_silence_ref = silence_ref;
  747. /* increase energy threshold (reduce nrg value)
  748. * to decrease sensitivity */
  749. if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
  750. data->nrg_th_cck = data->nrg_th_cck
  751. - NRG_STEP_CCK;
  752. }
  753. /* increase auto_corr values to decrease sensitivity */
  754. if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
  755. data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
  756. else {
  757. val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
  758. data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
  759. }
  760. val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
  761. data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
  762. /* Else if we got fewer than desired, increase sensitivity */
  763. } else if (false_alarms < min_false_alarms) {
  764. data->nrg_curr_state = IWL_FA_TOO_FEW;
  765. /* Compare silence level with silence level for most recent
  766. * healthy number or too many false alarms */
  767. data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
  768. (s32)silence_ref;
  769. IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
  770. false_alarms, min_false_alarms,
  771. data->nrg_auto_corr_silence_diff);
  772. /* Increase value to increase sensitivity, but only if:
  773. * 1a) previous beacon did *not* have *too many* false alarms
  774. * 1b) AND there's a significant difference in Rx levels
  775. * from a previous beacon with too many, or healthy # FAs
  776. * OR 2) We've seen a lot of beacons (100) with too few
  777. * false alarms */
  778. if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
  779. ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
  780. (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
  781. IWL_DEBUG_CALIB("... increasing sensitivity\n");
  782. /* Increase nrg value to increase sensitivity */
  783. val = data->nrg_th_cck + NRG_STEP_CCK;
  784. data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
  785. /* Decrease auto_corr values to increase sensitivity */
  786. val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
  787. data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
  788. val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
  789. data->auto_corr_cck_mrc =
  790. max((u32)AUTO_CORR_MIN_CCK_MRC, val);
  791. } else
  792. IWL_DEBUG_CALIB("... but not changing sensitivity\n");
  793. /* Else we got a healthy number of false alarms, keep status quo */
  794. } else {
  795. IWL_DEBUG_CALIB(" FA in safe zone\n");
  796. data->nrg_curr_state = IWL_FA_GOOD_RANGE;
  797. /* Store for use in "fewer than desired" with later beacon */
  798. data->nrg_silence_ref = silence_ref;
  799. /* If previous beacon had too many false alarms,
  800. * give it some extra margin by reducing sensitivity again
  801. * (but don't go below measured energy of desired Rx) */
  802. if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
  803. IWL_DEBUG_CALIB("... increasing margin\n");
  804. data->nrg_th_cck -= NRG_MARGIN;
  805. }
  806. }
  807. /* Make sure the energy threshold does not go above the measured
  808. * energy of the desired Rx signals (reduced by backoff margin),
  809. * or else we might start missing Rx frames.
  810. * Lower value is higher energy, so we use max()!
  811. */
  812. data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
  813. IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
  814. data->nrg_prev_state = data->nrg_curr_state;
  815. return 0;
  816. }
  817. static int iwl4965_sens_auto_corr_ofdm(struct iwl4965_priv *priv,
  818. u32 norm_fa,
  819. u32 rx_enable_time)
  820. {
  821. u32 val;
  822. u32 false_alarms = norm_fa * 200 * 1024;
  823. u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
  824. u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
  825. struct iwl4965_sensitivity_data *data = NULL;
  826. data = &(priv->sensitivity_data);
  827. /* If we got too many false alarms this time, reduce sensitivity */
  828. if (false_alarms > max_false_alarms) {
  829. IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
  830. false_alarms, max_false_alarms);
  831. val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
  832. data->auto_corr_ofdm =
  833. min((u32)AUTO_CORR_MAX_OFDM, val);
  834. val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
  835. data->auto_corr_ofdm_mrc =
  836. min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
  837. val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
  838. data->auto_corr_ofdm_x1 =
  839. min((u32)AUTO_CORR_MAX_OFDM_X1, val);
  840. val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
  841. data->auto_corr_ofdm_mrc_x1 =
  842. min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
  843. }
  844. /* Else if we got fewer than desired, increase sensitivity */
  845. else if (false_alarms < min_false_alarms) {
  846. IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
  847. false_alarms, min_false_alarms);
  848. val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
  849. data->auto_corr_ofdm =
  850. max((u32)AUTO_CORR_MIN_OFDM, val);
  851. val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
  852. data->auto_corr_ofdm_mrc =
  853. max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
  854. val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
  855. data->auto_corr_ofdm_x1 =
  856. max((u32)AUTO_CORR_MIN_OFDM_X1, val);
  857. val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
  858. data->auto_corr_ofdm_mrc_x1 =
  859. max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
  860. }
  861. else
  862. IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
  863. min_false_alarms, false_alarms, max_false_alarms);
  864. return 0;
  865. }
  866. static int iwl4965_sensitivity_callback(struct iwl4965_priv *priv,
  867. struct iwl4965_cmd *cmd, struct sk_buff *skb)
  868. {
  869. /* We didn't cache the SKB; let the caller free it */
  870. return 1;
  871. }
  872. /* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
  873. static int iwl4965_sensitivity_write(struct iwl4965_priv *priv, u8 flags)
  874. {
  875. int rc = 0;
  876. struct iwl4965_sensitivity_cmd cmd ;
  877. struct iwl4965_sensitivity_data *data = NULL;
  878. struct iwl4965_host_cmd cmd_out = {
  879. .id = SENSITIVITY_CMD,
  880. .len = sizeof(struct iwl4965_sensitivity_cmd),
  881. .meta.flags = flags,
  882. .data = &cmd,
  883. };
  884. data = &(priv->sensitivity_data);
  885. memset(&cmd, 0, sizeof(cmd));
  886. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
  887. cpu_to_le16((u16)data->auto_corr_ofdm);
  888. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
  889. cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
  890. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
  891. cpu_to_le16((u16)data->auto_corr_ofdm_x1);
  892. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
  893. cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
  894. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
  895. cpu_to_le16((u16)data->auto_corr_cck);
  896. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
  897. cpu_to_le16((u16)data->auto_corr_cck_mrc);
  898. cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
  899. cpu_to_le16((u16)data->nrg_th_cck);
  900. cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
  901. cpu_to_le16((u16)data->nrg_th_ofdm);
  902. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
  903. __constant_cpu_to_le16(190);
  904. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
  905. __constant_cpu_to_le16(390);
  906. cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
  907. __constant_cpu_to_le16(62);
  908. IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
  909. data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
  910. data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
  911. data->nrg_th_ofdm);
  912. IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
  913. data->auto_corr_cck, data->auto_corr_cck_mrc,
  914. data->nrg_th_cck);
  915. /* Update uCode's "work" table, and copy it to DSP */
  916. cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
  917. if (flags & CMD_ASYNC)
  918. cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
  919. /* Don't send command to uCode if nothing has changed */
  920. if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
  921. sizeof(u16)*HD_TABLE_SIZE)) {
  922. IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
  923. return 0;
  924. }
  925. /* Copy table for comparison next time */
  926. memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
  927. sizeof(u16)*HD_TABLE_SIZE);
  928. rc = iwl4965_send_cmd(priv, &cmd_out);
  929. if (!rc) {
  930. IWL_DEBUG_CALIB("SENSITIVITY_CMD succeeded\n");
  931. return rc;
  932. }
  933. return 0;
  934. }
  935. void iwl4965_init_sensitivity(struct iwl4965_priv *priv, u8 flags, u8 force)
  936. {
  937. int rc = 0;
  938. int i;
  939. struct iwl4965_sensitivity_data *data = NULL;
  940. IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
  941. if (force)
  942. memset(&(priv->sensitivity_tbl[0]), 0,
  943. sizeof(u16)*HD_TABLE_SIZE);
  944. /* Clear driver's sensitivity algo data */
  945. data = &(priv->sensitivity_data);
  946. memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
  947. data->num_in_cck_no_fa = 0;
  948. data->nrg_curr_state = IWL_FA_TOO_MANY;
  949. data->nrg_prev_state = IWL_FA_TOO_MANY;
  950. data->nrg_silence_ref = 0;
  951. data->nrg_silence_idx = 0;
  952. data->nrg_energy_idx = 0;
  953. for (i = 0; i < 10; i++)
  954. data->nrg_value[i] = 0;
  955. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
  956. data->nrg_silence_rssi[i] = 0;
  957. data->auto_corr_ofdm = 90;
  958. data->auto_corr_ofdm_mrc = 170;
  959. data->auto_corr_ofdm_x1 = 105;
  960. data->auto_corr_ofdm_mrc_x1 = 220;
  961. data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
  962. data->auto_corr_cck_mrc = 200;
  963. data->nrg_th_cck = 100;
  964. data->nrg_th_ofdm = 100;
  965. data->last_bad_plcp_cnt_ofdm = 0;
  966. data->last_fa_cnt_ofdm = 0;
  967. data->last_bad_plcp_cnt_cck = 0;
  968. data->last_fa_cnt_cck = 0;
  969. /* Clear prior Sensitivity command data to force send to uCode */
  970. if (force)
  971. memset(&(priv->sensitivity_tbl[0]), 0,
  972. sizeof(u16)*HD_TABLE_SIZE);
  973. rc |= iwl4965_sensitivity_write(priv, flags);
  974. IWL_DEBUG_CALIB("<<return 0x%X\n", rc);
  975. return;
  976. }
  977. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  978. * Called after every association, but this runs only once!
  979. * ... once chain noise is calibrated the first time, it's good forever. */
  980. void iwl4965_chain_noise_reset(struct iwl4965_priv *priv)
  981. {
  982. struct iwl4965_chain_noise_data *data = NULL;
  983. int rc = 0;
  984. data = &(priv->chain_noise_data);
  985. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl4965_is_associated(priv)) {
  986. struct iwl4965_calibration_cmd cmd;
  987. memset(&cmd, 0, sizeof(cmd));
  988. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  989. cmd.diff_gain_a = 0;
  990. cmd.diff_gain_b = 0;
  991. cmd.diff_gain_c = 0;
  992. rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  993. sizeof(cmd), &cmd);
  994. msleep(4);
  995. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  996. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  997. }
  998. return;
  999. }
  1000. /*
  1001. * Accumulate 20 beacons of signal and noise statistics for each of
  1002. * 3 receivers/antennas/rx-chains, then figure out:
  1003. * 1) Which antennas are connected.
  1004. * 2) Differential rx gain settings to balance the 3 receivers.
  1005. */
  1006. static void iwl4965_noise_calibration(struct iwl4965_priv *priv,
  1007. struct iwl4965_notif_statistics *stat_resp)
  1008. {
  1009. struct iwl4965_chain_noise_data *data = NULL;
  1010. int rc = 0;
  1011. u32 chain_noise_a;
  1012. u32 chain_noise_b;
  1013. u32 chain_noise_c;
  1014. u32 chain_sig_a;
  1015. u32 chain_sig_b;
  1016. u32 chain_sig_c;
  1017. u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  1018. u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  1019. u32 max_average_sig;
  1020. u16 max_average_sig_antenna_i;
  1021. u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
  1022. u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
  1023. u16 i = 0;
  1024. u16 chan_num = INITIALIZATION_VALUE;
  1025. u32 band = INITIALIZATION_VALUE;
  1026. u32 active_chains = 0;
  1027. unsigned long flags;
  1028. struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
  1029. data = &(priv->chain_noise_data);
  1030. /* Accumulate just the first 20 beacons after the first association,
  1031. * then we're done forever. */
  1032. if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
  1033. if (data->state == IWL_CHAIN_NOISE_ALIVE)
  1034. IWL_DEBUG_CALIB("Wait for noise calib reset\n");
  1035. return;
  1036. }
  1037. spin_lock_irqsave(&priv->lock, flags);
  1038. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  1039. IWL_DEBUG_CALIB(" << Interference data unavailable\n");
  1040. spin_unlock_irqrestore(&priv->lock, flags);
  1041. return;
  1042. }
  1043. band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
  1044. chan_num = le16_to_cpu(priv->staging_rxon.channel);
  1045. /* Make sure we accumulate data for just the associated channel
  1046. * (even if scanning). */
  1047. if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
  1048. ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
  1049. (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
  1050. IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
  1051. chan_num, band);
  1052. spin_unlock_irqrestore(&priv->lock, flags);
  1053. return;
  1054. }
  1055. /* Accumulate beacon statistics values across 20 beacons */
  1056. chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
  1057. IN_BAND_FILTER;
  1058. chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
  1059. IN_BAND_FILTER;
  1060. chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
  1061. IN_BAND_FILTER;
  1062. chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
  1063. chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
  1064. chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
  1065. spin_unlock_irqrestore(&priv->lock, flags);
  1066. data->beacon_count++;
  1067. data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
  1068. data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
  1069. data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
  1070. data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
  1071. data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
  1072. data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
  1073. IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
  1074. data->beacon_count);
  1075. IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
  1076. chain_sig_a, chain_sig_b, chain_sig_c);
  1077. IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
  1078. chain_noise_a, chain_noise_b, chain_noise_c);
  1079. /* If this is the 20th beacon, determine:
  1080. * 1) Disconnected antennas (using signal strengths)
  1081. * 2) Differential gain (using silence noise) to balance receivers */
  1082. if (data->beacon_count == CAL_NUM_OF_BEACONS) {
  1083. /* Analyze signal for disconnected antenna */
  1084. average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
  1085. average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
  1086. average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
  1087. if (average_sig[0] >= average_sig[1]) {
  1088. max_average_sig = average_sig[0];
  1089. max_average_sig_antenna_i = 0;
  1090. active_chains = (1 << max_average_sig_antenna_i);
  1091. } else {
  1092. max_average_sig = average_sig[1];
  1093. max_average_sig_antenna_i = 1;
  1094. active_chains = (1 << max_average_sig_antenna_i);
  1095. }
  1096. if (average_sig[2] >= max_average_sig) {
  1097. max_average_sig = average_sig[2];
  1098. max_average_sig_antenna_i = 2;
  1099. active_chains = (1 << max_average_sig_antenna_i);
  1100. }
  1101. IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
  1102. average_sig[0], average_sig[1], average_sig[2]);
  1103. IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
  1104. max_average_sig, max_average_sig_antenna_i);
  1105. /* Compare signal strengths for all 3 receivers. */
  1106. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1107. if (i != max_average_sig_antenna_i) {
  1108. s32 rssi_delta = (max_average_sig -
  1109. average_sig[i]);
  1110. /* If signal is very weak, compared with
  1111. * strongest, mark it as disconnected. */
  1112. if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
  1113. data->disconn_array[i] = 1;
  1114. else
  1115. active_chains |= (1 << i);
  1116. IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
  1117. "disconn_array[i] = %d\n",
  1118. i, rssi_delta, data->disconn_array[i]);
  1119. }
  1120. }
  1121. /*If both chains A & B are disconnected -
  1122. * connect B and leave A as is */
  1123. if (data->disconn_array[CHAIN_A] &&
  1124. data->disconn_array[CHAIN_B]) {
  1125. data->disconn_array[CHAIN_B] = 0;
  1126. active_chains |= (1 << CHAIN_B);
  1127. IWL_DEBUG_CALIB("both A & B chains are disconnected! "
  1128. "W/A - declare B as connected\n");
  1129. }
  1130. IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
  1131. active_chains);
  1132. /* Save for use within RXON, TX, SCAN commands, etc. */
  1133. priv->valid_antenna = active_chains;
  1134. /* Analyze noise for rx balance */
  1135. average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
  1136. average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
  1137. average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
  1138. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1139. if (!(data->disconn_array[i]) &&
  1140. (average_noise[i] <= min_average_noise)) {
  1141. /* This means that chain i is active and has
  1142. * lower noise values so far: */
  1143. min_average_noise = average_noise[i];
  1144. min_average_noise_antenna_i = i;
  1145. }
  1146. }
  1147. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  1148. IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
  1149. average_noise[0], average_noise[1],
  1150. average_noise[2]);
  1151. IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
  1152. min_average_noise, min_average_noise_antenna_i);
  1153. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1154. s32 delta_g = 0;
  1155. if (!(data->disconn_array[i]) &&
  1156. (data->delta_gain_code[i] ==
  1157. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  1158. delta_g = average_noise[i] - min_average_noise;
  1159. data->delta_gain_code[i] = (u8)((delta_g *
  1160. 10) / 15);
  1161. if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
  1162. data->delta_gain_code[i])
  1163. data->delta_gain_code[i] =
  1164. CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
  1165. data->delta_gain_code[i] =
  1166. (data->delta_gain_code[i] | (1 << 2));
  1167. } else
  1168. data->delta_gain_code[i] = 0;
  1169. }
  1170. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  1171. data->delta_gain_code[0],
  1172. data->delta_gain_code[1],
  1173. data->delta_gain_code[2]);
  1174. /* Differential gain gets sent to uCode only once */
  1175. if (!data->radio_write) {
  1176. struct iwl4965_calibration_cmd cmd;
  1177. data->radio_write = 1;
  1178. memset(&cmd, 0, sizeof(cmd));
  1179. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  1180. cmd.diff_gain_a = data->delta_gain_code[0];
  1181. cmd.diff_gain_b = data->delta_gain_code[1];
  1182. cmd.diff_gain_c = data->delta_gain_code[2];
  1183. rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  1184. sizeof(cmd), &cmd);
  1185. if (rc)
  1186. IWL_DEBUG_CALIB("fail sending cmd "
  1187. "REPLY_PHY_CALIBRATION_CMD \n");
  1188. /* TODO we might want recalculate
  1189. * rx_chain in rxon cmd */
  1190. /* Mark so we run this algo only once! */
  1191. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  1192. }
  1193. data->chain_noise_a = 0;
  1194. data->chain_noise_b = 0;
  1195. data->chain_noise_c = 0;
  1196. data->chain_signal_a = 0;
  1197. data->chain_signal_b = 0;
  1198. data->chain_signal_c = 0;
  1199. data->beacon_count = 0;
  1200. }
  1201. return;
  1202. }
  1203. static void iwl4965_sensitivity_calibration(struct iwl4965_priv *priv,
  1204. struct iwl4965_notif_statistics *resp)
  1205. {
  1206. int rc = 0;
  1207. u32 rx_enable_time;
  1208. u32 fa_cck;
  1209. u32 fa_ofdm;
  1210. u32 bad_plcp_cck;
  1211. u32 bad_plcp_ofdm;
  1212. u32 norm_fa_ofdm;
  1213. u32 norm_fa_cck;
  1214. struct iwl4965_sensitivity_data *data = NULL;
  1215. struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
  1216. struct statistics_rx *statistics = &(resp->rx);
  1217. unsigned long flags;
  1218. struct statistics_general_data statis;
  1219. data = &(priv->sensitivity_data);
  1220. if (!iwl4965_is_associated(priv)) {
  1221. IWL_DEBUG_CALIB("<< - not associated\n");
  1222. return;
  1223. }
  1224. spin_lock_irqsave(&priv->lock, flags);
  1225. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  1226. IWL_DEBUG_CALIB("<< invalid data.\n");
  1227. spin_unlock_irqrestore(&priv->lock, flags);
  1228. return;
  1229. }
  1230. /* Extract Statistics: */
  1231. rx_enable_time = le32_to_cpu(rx_info->channel_load);
  1232. fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
  1233. fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
  1234. bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
  1235. bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
  1236. statis.beacon_silence_rssi_a =
  1237. le32_to_cpu(statistics->general.beacon_silence_rssi_a);
  1238. statis.beacon_silence_rssi_b =
  1239. le32_to_cpu(statistics->general.beacon_silence_rssi_b);
  1240. statis.beacon_silence_rssi_c =
  1241. le32_to_cpu(statistics->general.beacon_silence_rssi_c);
  1242. statis.beacon_energy_a =
  1243. le32_to_cpu(statistics->general.beacon_energy_a);
  1244. statis.beacon_energy_b =
  1245. le32_to_cpu(statistics->general.beacon_energy_b);
  1246. statis.beacon_energy_c =
  1247. le32_to_cpu(statistics->general.beacon_energy_c);
  1248. spin_unlock_irqrestore(&priv->lock, flags);
  1249. IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
  1250. if (!rx_enable_time) {
  1251. IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
  1252. return;
  1253. }
  1254. /* These statistics increase monotonically, and do not reset
  1255. * at each beacon. Calculate difference from last value, or just
  1256. * use the new statistics value if it has reset or wrapped around. */
  1257. if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
  1258. data->last_bad_plcp_cnt_cck = bad_plcp_cck;
  1259. else {
  1260. bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
  1261. data->last_bad_plcp_cnt_cck += bad_plcp_cck;
  1262. }
  1263. if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
  1264. data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
  1265. else {
  1266. bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
  1267. data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
  1268. }
  1269. if (data->last_fa_cnt_ofdm > fa_ofdm)
  1270. data->last_fa_cnt_ofdm = fa_ofdm;
  1271. else {
  1272. fa_ofdm -= data->last_fa_cnt_ofdm;
  1273. data->last_fa_cnt_ofdm += fa_ofdm;
  1274. }
  1275. if (data->last_fa_cnt_cck > fa_cck)
  1276. data->last_fa_cnt_cck = fa_cck;
  1277. else {
  1278. fa_cck -= data->last_fa_cnt_cck;
  1279. data->last_fa_cnt_cck += fa_cck;
  1280. }
  1281. /* Total aborted signal locks */
  1282. norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
  1283. norm_fa_cck = fa_cck + bad_plcp_cck;
  1284. IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
  1285. bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
  1286. iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
  1287. iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
  1288. rc |= iwl4965_sensitivity_write(priv, CMD_ASYNC);
  1289. return;
  1290. }
  1291. static void iwl4965_bg_sensitivity_work(struct work_struct *work)
  1292. {
  1293. struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
  1294. sensitivity_work);
  1295. mutex_lock(&priv->mutex);
  1296. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1297. test_bit(STATUS_SCANNING, &priv->status)) {
  1298. mutex_unlock(&priv->mutex);
  1299. return;
  1300. }
  1301. if (priv->start_calib) {
  1302. iwl4965_noise_calibration(priv, &priv->statistics);
  1303. if (priv->sensitivity_data.state ==
  1304. IWL_SENS_CALIB_NEED_REINIT) {
  1305. iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
  1306. priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
  1307. } else
  1308. iwl4965_sensitivity_calibration(priv,
  1309. &priv->statistics);
  1310. }
  1311. mutex_unlock(&priv->mutex);
  1312. return;
  1313. }
  1314. #endif /*CONFIG_IWL4965_SENSITIVITY*/
  1315. static void iwl4965_bg_txpower_work(struct work_struct *work)
  1316. {
  1317. struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
  1318. txpower_work);
  1319. /* If a scan happened to start before we got here
  1320. * then just return; the statistics notification will
  1321. * kick off another scheduled work to compensate for
  1322. * any temperature delta we missed here. */
  1323. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1324. test_bit(STATUS_SCANNING, &priv->status))
  1325. return;
  1326. mutex_lock(&priv->mutex);
  1327. /* Regardless of if we are assocaited, we must reconfigure the
  1328. * TX power since frames can be sent on non-radar channels while
  1329. * not associated */
  1330. iwl4965_hw_reg_send_txpower(priv);
  1331. /* Update last_temperature to keep is_calib_needed from running
  1332. * when it isn't needed... */
  1333. priv->last_temperature = priv->temperature;
  1334. mutex_unlock(&priv->mutex);
  1335. }
  1336. /*
  1337. * Acquire priv->lock before calling this function !
  1338. */
  1339. static void iwl4965_set_wr_ptrs(struct iwl4965_priv *priv, int txq_id, u32 index)
  1340. {
  1341. iwl4965_write_direct32(priv, HBUS_TARG_WRPTR,
  1342. (index & 0xff) | (txq_id << 8));
  1343. iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
  1344. }
  1345. /**
  1346. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  1347. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  1348. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  1349. *
  1350. * NOTE: Acquire priv->lock before calling this function !
  1351. */
  1352. static void iwl4965_tx_queue_set_status(struct iwl4965_priv *priv,
  1353. struct iwl4965_tx_queue *txq,
  1354. int tx_fifo_id, int scd_retry)
  1355. {
  1356. int txq_id = txq->q.id;
  1357. /* Find out whether to activate Tx queue */
  1358. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  1359. /* Set up and activate */
  1360. iwl4965_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
  1361. (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  1362. (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
  1363. (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
  1364. (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  1365. SCD_QUEUE_STTS_REG_MSK);
  1366. txq->sched_retry = scd_retry;
  1367. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  1368. active ? "Activate" : "Deactivate",
  1369. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  1370. }
  1371. static const u16 default_queue_to_tx_fifo[] = {
  1372. IWL_TX_FIFO_AC3,
  1373. IWL_TX_FIFO_AC2,
  1374. IWL_TX_FIFO_AC1,
  1375. IWL_TX_FIFO_AC0,
  1376. IWL_CMD_FIFO_NUM,
  1377. IWL_TX_FIFO_HCCA_1,
  1378. IWL_TX_FIFO_HCCA_2
  1379. };
  1380. static inline void iwl4965_txq_ctx_activate(struct iwl4965_priv *priv, int txq_id)
  1381. {
  1382. set_bit(txq_id, &priv->txq_ctx_active_msk);
  1383. }
  1384. static inline void iwl4965_txq_ctx_deactivate(struct iwl4965_priv *priv, int txq_id)
  1385. {
  1386. clear_bit(txq_id, &priv->txq_ctx_active_msk);
  1387. }
  1388. int iwl4965_alive_notify(struct iwl4965_priv *priv)
  1389. {
  1390. u32 a;
  1391. int i = 0;
  1392. unsigned long flags;
  1393. int rc;
  1394. spin_lock_irqsave(&priv->lock, flags);
  1395. #ifdef CONFIG_IWL4965_SENSITIVITY
  1396. memset(&(priv->sensitivity_data), 0,
  1397. sizeof(struct iwl4965_sensitivity_data));
  1398. memset(&(priv->chain_noise_data), 0,
  1399. sizeof(struct iwl4965_chain_noise_data));
  1400. for (i = 0; i < NUM_RX_CHAINS; i++)
  1401. priv->chain_noise_data.delta_gain_code[i] =
  1402. CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
  1403. #endif /* CONFIG_IWL4965_SENSITIVITY*/
  1404. rc = iwl4965_grab_nic_access(priv);
  1405. if (rc) {
  1406. spin_unlock_irqrestore(&priv->lock, flags);
  1407. return rc;
  1408. }
  1409. /* Clear 4965's internal Tx Scheduler data base */
  1410. priv->scd_base_addr = iwl4965_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
  1411. a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
  1412. for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  1413. iwl4965_write_targ_mem(priv, a, 0);
  1414. for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
  1415. iwl4965_write_targ_mem(priv, a, 0);
  1416. for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
  1417. iwl4965_write_targ_mem(priv, a, 0);
  1418. /* Tel 4965 where to find Tx byte count tables */
  1419. iwl4965_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
  1420. (priv->hw_setting.shared_phys +
  1421. offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
  1422. /* Disable chain mode for all queues */
  1423. iwl4965_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
  1424. /* Initialize each Tx queue (including the command queue) */
  1425. for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
  1426. /* TFD circular buffer read/write indexes */
  1427. iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
  1428. iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  1429. /* Max Tx Window size for Scheduler-ACK mode */
  1430. iwl4965_write_targ_mem(priv, priv->scd_base_addr +
  1431. SCD_CONTEXT_QUEUE_OFFSET(i),
  1432. (SCD_WIN_SIZE <<
  1433. SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  1434. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  1435. /* Frame limit */
  1436. iwl4965_write_targ_mem(priv, priv->scd_base_addr +
  1437. SCD_CONTEXT_QUEUE_OFFSET(i) +
  1438. sizeof(u32),
  1439. (SCD_FRAME_LIMIT <<
  1440. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  1441. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  1442. }
  1443. iwl4965_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
  1444. (1 << priv->hw_setting.max_txq_num) - 1);
  1445. /* Activate all Tx DMA/FIFO channels */
  1446. iwl4965_write_prph(priv, KDR_SCD_TXFACT,
  1447. SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
  1448. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  1449. /* Map each Tx/cmd queue to its corresponding fifo */
  1450. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  1451. int ac = default_queue_to_tx_fifo[i];
  1452. iwl4965_txq_ctx_activate(priv, i);
  1453. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  1454. }
  1455. iwl4965_release_nic_access(priv);
  1456. spin_unlock_irqrestore(&priv->lock, flags);
  1457. return 0;
  1458. }
  1459. /**
  1460. * iwl4965_hw_set_hw_setting
  1461. *
  1462. * Called when initializing driver
  1463. */
  1464. int iwl4965_hw_set_hw_setting(struct iwl4965_priv *priv)
  1465. {
  1466. /* Allocate area for Tx byte count tables and Rx queue status */
  1467. priv->hw_setting.shared_virt =
  1468. pci_alloc_consistent(priv->pci_dev,
  1469. sizeof(struct iwl4965_shared),
  1470. &priv->hw_setting.shared_phys);
  1471. if (!priv->hw_setting.shared_virt)
  1472. return -1;
  1473. memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared));
  1474. priv->hw_setting.max_txq_num = iwl4965_param_queues_num;
  1475. priv->hw_setting.ac_queue_count = AC_NUM;
  1476. priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
  1477. priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
  1478. priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1479. if (iwl4965_param_amsdu_size_8K)
  1480. priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  1481. else
  1482. priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  1483. priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
  1484. priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
  1485. priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
  1486. return 0;
  1487. }
  1488. /**
  1489. * iwl4965_hw_txq_ctx_free - Free TXQ Context
  1490. *
  1491. * Destroy all TX DMA queues and structures
  1492. */
  1493. void iwl4965_hw_txq_ctx_free(struct iwl4965_priv *priv)
  1494. {
  1495. int txq_id;
  1496. /* Tx queues */
  1497. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  1498. iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
  1499. /* Keep-warm buffer */
  1500. iwl4965_kw_free(priv);
  1501. }
  1502. /**
  1503. * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  1504. *
  1505. * Does NOT advance any TFD circular buffer read/write indexes
  1506. * Does NOT free the TFD itself (which is within circular buffer)
  1507. */
  1508. int iwl4965_hw_txq_free_tfd(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
  1509. {
  1510. struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
  1511. struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
  1512. struct pci_dev *dev = priv->pci_dev;
  1513. int i;
  1514. int counter = 0;
  1515. int index, is_odd;
  1516. /* Host command buffers stay mapped in memory, nothing to clean */
  1517. if (txq->q.id == IWL_CMD_QUEUE_NUM)
  1518. return 0;
  1519. /* Sanity check on number of chunks */
  1520. counter = IWL_GET_BITS(*bd, num_tbs);
  1521. if (counter > MAX_NUM_OF_TBS) {
  1522. IWL_ERROR("Too many chunks: %i\n", counter);
  1523. /* @todo issue fatal error, it is quite serious situation */
  1524. return 0;
  1525. }
  1526. /* Unmap chunks, if any.
  1527. * TFD info for odd chunks is different format than for even chunks. */
  1528. for (i = 0; i < counter; i++) {
  1529. index = i / 2;
  1530. is_odd = i & 0x1;
  1531. if (is_odd)
  1532. pci_unmap_single(
  1533. dev,
  1534. IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
  1535. (IWL_GET_BITS(bd->pa[index],
  1536. tb2_addr_hi20) << 16),
  1537. IWL_GET_BITS(bd->pa[index], tb2_len),
  1538. PCI_DMA_TODEVICE);
  1539. else if (i > 0)
  1540. pci_unmap_single(dev,
  1541. le32_to_cpu(bd->pa[index].tb1_addr),
  1542. IWL_GET_BITS(bd->pa[index], tb1_len),
  1543. PCI_DMA_TODEVICE);
  1544. /* Free SKB, if any, for this chunk */
  1545. if (txq->txb[txq->q.read_ptr].skb[i]) {
  1546. struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
  1547. dev_kfree_skb(skb);
  1548. txq->txb[txq->q.read_ptr].skb[i] = NULL;
  1549. }
  1550. }
  1551. return 0;
  1552. }
  1553. int iwl4965_hw_reg_set_txpower(struct iwl4965_priv *priv, s8 power)
  1554. {
  1555. IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
  1556. return -EINVAL;
  1557. }
  1558. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  1559. {
  1560. s32 sign = 1;
  1561. if (num < 0) {
  1562. sign = -sign;
  1563. num = -num;
  1564. }
  1565. if (denom < 0) {
  1566. sign = -sign;
  1567. denom = -denom;
  1568. }
  1569. *res = 1;
  1570. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  1571. return 1;
  1572. }
  1573. /**
  1574. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  1575. *
  1576. * Determines power supply voltage compensation for txpower calculations.
  1577. * Returns number of 1/2-dB steps to subtract from gain table index,
  1578. * to compensate for difference between power supply voltage during
  1579. * factory measurements, vs. current power supply voltage.
  1580. *
  1581. * Voltage indication is higher for lower voltage.
  1582. * Lower voltage requires more gain (lower gain table index).
  1583. */
  1584. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  1585. s32 current_voltage)
  1586. {
  1587. s32 comp = 0;
  1588. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  1589. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  1590. return 0;
  1591. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  1592. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  1593. if (current_voltage > eeprom_voltage)
  1594. comp *= 2;
  1595. if ((comp < -2) || (comp > 2))
  1596. comp = 0;
  1597. return comp;
  1598. }
  1599. static const struct iwl4965_channel_info *
  1600. iwl4965_get_channel_txpower_info(struct iwl4965_priv *priv, u8 phymode, u16 channel)
  1601. {
  1602. const struct iwl4965_channel_info *ch_info;
  1603. ch_info = iwl4965_get_channel_info(priv, phymode, channel);
  1604. if (!is_channel_valid(ch_info))
  1605. return NULL;
  1606. return ch_info;
  1607. }
  1608. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  1609. {
  1610. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  1611. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  1612. return CALIB_CH_GROUP_5;
  1613. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  1614. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  1615. return CALIB_CH_GROUP_1;
  1616. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  1617. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  1618. return CALIB_CH_GROUP_2;
  1619. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  1620. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  1621. return CALIB_CH_GROUP_3;
  1622. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  1623. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  1624. return CALIB_CH_GROUP_4;
  1625. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  1626. return -1;
  1627. }
  1628. static u32 iwl4965_get_sub_band(const struct iwl4965_priv *priv, u32 channel)
  1629. {
  1630. s32 b = -1;
  1631. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  1632. if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
  1633. continue;
  1634. if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
  1635. && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
  1636. break;
  1637. }
  1638. return b;
  1639. }
  1640. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  1641. {
  1642. s32 val;
  1643. if (x2 == x1)
  1644. return y1;
  1645. else {
  1646. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  1647. return val + y2;
  1648. }
  1649. }
  1650. /**
  1651. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  1652. *
  1653. * Interpolates factory measurements from the two sample channels within a
  1654. * sub-band, to apply to channel of interest. Interpolation is proportional to
  1655. * differences in channel frequencies, which is proportional to differences
  1656. * in channel number.
  1657. */
  1658. static int iwl4965_interpolate_chan(struct iwl4965_priv *priv, u32 channel,
  1659. struct iwl4965_eeprom_calib_ch_info *chan_info)
  1660. {
  1661. s32 s = -1;
  1662. u32 c;
  1663. u32 m;
  1664. const struct iwl4965_eeprom_calib_measure *m1;
  1665. const struct iwl4965_eeprom_calib_measure *m2;
  1666. struct iwl4965_eeprom_calib_measure *omeas;
  1667. u32 ch_i1;
  1668. u32 ch_i2;
  1669. s = iwl4965_get_sub_band(priv, channel);
  1670. if (s >= EEPROM_TX_POWER_BANDS) {
  1671. IWL_ERROR("Tx Power can not find channel %d ", channel);
  1672. return -1;
  1673. }
  1674. ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
  1675. ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
  1676. chan_info->ch_num = (u8) channel;
  1677. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  1678. channel, s, ch_i1, ch_i2);
  1679. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  1680. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  1681. m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
  1682. measurements[c][m]);
  1683. m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
  1684. measurements[c][m]);
  1685. omeas = &(chan_info->measurements[c][m]);
  1686. omeas->actual_pow =
  1687. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1688. m1->actual_pow,
  1689. ch_i2,
  1690. m2->actual_pow);
  1691. omeas->gain_idx =
  1692. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1693. m1->gain_idx, ch_i2,
  1694. m2->gain_idx);
  1695. omeas->temperature =
  1696. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1697. m1->temperature,
  1698. ch_i2,
  1699. m2->temperature);
  1700. omeas->pa_det =
  1701. (s8) iwl4965_interpolate_value(channel, ch_i1,
  1702. m1->pa_det, ch_i2,
  1703. m2->pa_det);
  1704. IWL_DEBUG_TXPOWER
  1705. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  1706. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  1707. IWL_DEBUG_TXPOWER
  1708. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  1709. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  1710. IWL_DEBUG_TXPOWER
  1711. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  1712. m1->pa_det, m2->pa_det, omeas->pa_det);
  1713. IWL_DEBUG_TXPOWER
  1714. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  1715. m1->temperature, m2->temperature,
  1716. omeas->temperature);
  1717. }
  1718. }
  1719. return 0;
  1720. }
  1721. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  1722. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  1723. static s32 back_off_table[] = {
  1724. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  1725. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  1726. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  1727. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  1728. 10 /* CCK */
  1729. };
  1730. /* Thermal compensation values for txpower for various frequency ranges ...
  1731. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  1732. static struct iwl4965_txpower_comp_entry {
  1733. s32 degrees_per_05db_a;
  1734. s32 degrees_per_05db_a_denom;
  1735. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  1736. {9, 2}, /* group 0 5.2, ch 34-43 */
  1737. {4, 1}, /* group 1 5.2, ch 44-70 */
  1738. {4, 1}, /* group 2 5.2, ch 71-124 */
  1739. {4, 1}, /* group 3 5.2, ch 125-200 */
  1740. {3, 1} /* group 4 2.4, ch all */
  1741. };
  1742. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  1743. {
  1744. if (!band) {
  1745. if ((rate_power_index & 7) <= 4)
  1746. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  1747. }
  1748. return MIN_TX_GAIN_INDEX;
  1749. }
  1750. struct gain_entry {
  1751. u8 dsp;
  1752. u8 radio;
  1753. };
  1754. static const struct gain_entry gain_table[2][108] = {
  1755. /* 5.2GHz power gain index table */
  1756. {
  1757. {123, 0x3F}, /* highest txpower */
  1758. {117, 0x3F},
  1759. {110, 0x3F},
  1760. {104, 0x3F},
  1761. {98, 0x3F},
  1762. {110, 0x3E},
  1763. {104, 0x3E},
  1764. {98, 0x3E},
  1765. {110, 0x3D},
  1766. {104, 0x3D},
  1767. {98, 0x3D},
  1768. {110, 0x3C},
  1769. {104, 0x3C},
  1770. {98, 0x3C},
  1771. {110, 0x3B},
  1772. {104, 0x3B},
  1773. {98, 0x3B},
  1774. {110, 0x3A},
  1775. {104, 0x3A},
  1776. {98, 0x3A},
  1777. {110, 0x39},
  1778. {104, 0x39},
  1779. {98, 0x39},
  1780. {110, 0x38},
  1781. {104, 0x38},
  1782. {98, 0x38},
  1783. {110, 0x37},
  1784. {104, 0x37},
  1785. {98, 0x37},
  1786. {110, 0x36},
  1787. {104, 0x36},
  1788. {98, 0x36},
  1789. {110, 0x35},
  1790. {104, 0x35},
  1791. {98, 0x35},
  1792. {110, 0x34},
  1793. {104, 0x34},
  1794. {98, 0x34},
  1795. {110, 0x33},
  1796. {104, 0x33},
  1797. {98, 0x33},
  1798. {110, 0x32},
  1799. {104, 0x32},
  1800. {98, 0x32},
  1801. {110, 0x31},
  1802. {104, 0x31},
  1803. {98, 0x31},
  1804. {110, 0x30},
  1805. {104, 0x30},
  1806. {98, 0x30},
  1807. {110, 0x25},
  1808. {104, 0x25},
  1809. {98, 0x25},
  1810. {110, 0x24},
  1811. {104, 0x24},
  1812. {98, 0x24},
  1813. {110, 0x23},
  1814. {104, 0x23},
  1815. {98, 0x23},
  1816. {110, 0x22},
  1817. {104, 0x18},
  1818. {98, 0x18},
  1819. {110, 0x17},
  1820. {104, 0x17},
  1821. {98, 0x17},
  1822. {110, 0x16},
  1823. {104, 0x16},
  1824. {98, 0x16},
  1825. {110, 0x15},
  1826. {104, 0x15},
  1827. {98, 0x15},
  1828. {110, 0x14},
  1829. {104, 0x14},
  1830. {98, 0x14},
  1831. {110, 0x13},
  1832. {104, 0x13},
  1833. {98, 0x13},
  1834. {110, 0x12},
  1835. {104, 0x08},
  1836. {98, 0x08},
  1837. {110, 0x07},
  1838. {104, 0x07},
  1839. {98, 0x07},
  1840. {110, 0x06},
  1841. {104, 0x06},
  1842. {98, 0x06},
  1843. {110, 0x05},
  1844. {104, 0x05},
  1845. {98, 0x05},
  1846. {110, 0x04},
  1847. {104, 0x04},
  1848. {98, 0x04},
  1849. {110, 0x03},
  1850. {104, 0x03},
  1851. {98, 0x03},
  1852. {110, 0x02},
  1853. {104, 0x02},
  1854. {98, 0x02},
  1855. {110, 0x01},
  1856. {104, 0x01},
  1857. {98, 0x01},
  1858. {110, 0x00},
  1859. {104, 0x00},
  1860. {98, 0x00},
  1861. {93, 0x00},
  1862. {88, 0x00},
  1863. {83, 0x00},
  1864. {78, 0x00},
  1865. },
  1866. /* 2.4GHz power gain index table */
  1867. {
  1868. {110, 0x3f}, /* highest txpower */
  1869. {104, 0x3f},
  1870. {98, 0x3f},
  1871. {110, 0x3e},
  1872. {104, 0x3e},
  1873. {98, 0x3e},
  1874. {110, 0x3d},
  1875. {104, 0x3d},
  1876. {98, 0x3d},
  1877. {110, 0x3c},
  1878. {104, 0x3c},
  1879. {98, 0x3c},
  1880. {110, 0x3b},
  1881. {104, 0x3b},
  1882. {98, 0x3b},
  1883. {110, 0x3a},
  1884. {104, 0x3a},
  1885. {98, 0x3a},
  1886. {110, 0x39},
  1887. {104, 0x39},
  1888. {98, 0x39},
  1889. {110, 0x38},
  1890. {104, 0x38},
  1891. {98, 0x38},
  1892. {110, 0x37},
  1893. {104, 0x37},
  1894. {98, 0x37},
  1895. {110, 0x36},
  1896. {104, 0x36},
  1897. {98, 0x36},
  1898. {110, 0x35},
  1899. {104, 0x35},
  1900. {98, 0x35},
  1901. {110, 0x34},
  1902. {104, 0x34},
  1903. {98, 0x34},
  1904. {110, 0x33},
  1905. {104, 0x33},
  1906. {98, 0x33},
  1907. {110, 0x32},
  1908. {104, 0x32},
  1909. {98, 0x32},
  1910. {110, 0x31},
  1911. {104, 0x31},
  1912. {98, 0x31},
  1913. {110, 0x30},
  1914. {104, 0x30},
  1915. {98, 0x30},
  1916. {110, 0x6},
  1917. {104, 0x6},
  1918. {98, 0x6},
  1919. {110, 0x5},
  1920. {104, 0x5},
  1921. {98, 0x5},
  1922. {110, 0x4},
  1923. {104, 0x4},
  1924. {98, 0x4},
  1925. {110, 0x3},
  1926. {104, 0x3},
  1927. {98, 0x3},
  1928. {110, 0x2},
  1929. {104, 0x2},
  1930. {98, 0x2},
  1931. {110, 0x1},
  1932. {104, 0x1},
  1933. {98, 0x1},
  1934. {110, 0x0},
  1935. {104, 0x0},
  1936. {98, 0x0},
  1937. {97, 0},
  1938. {96, 0},
  1939. {95, 0},
  1940. {94, 0},
  1941. {93, 0},
  1942. {92, 0},
  1943. {91, 0},
  1944. {90, 0},
  1945. {89, 0},
  1946. {88, 0},
  1947. {87, 0},
  1948. {86, 0},
  1949. {85, 0},
  1950. {84, 0},
  1951. {83, 0},
  1952. {82, 0},
  1953. {81, 0},
  1954. {80, 0},
  1955. {79, 0},
  1956. {78, 0},
  1957. {77, 0},
  1958. {76, 0},
  1959. {75, 0},
  1960. {74, 0},
  1961. {73, 0},
  1962. {72, 0},
  1963. {71, 0},
  1964. {70, 0},
  1965. {69, 0},
  1966. {68, 0},
  1967. {67, 0},
  1968. {66, 0},
  1969. {65, 0},
  1970. {64, 0},
  1971. {63, 0},
  1972. {62, 0},
  1973. {61, 0},
  1974. {60, 0},
  1975. {59, 0},
  1976. }
  1977. };
  1978. static int iwl4965_fill_txpower_tbl(struct iwl4965_priv *priv, u8 band, u16 channel,
  1979. u8 is_fat, u8 ctrl_chan_high,
  1980. struct iwl4965_tx_power_db *tx_power_tbl)
  1981. {
  1982. u8 saturation_power;
  1983. s32 target_power;
  1984. s32 user_target_power;
  1985. s32 power_limit;
  1986. s32 current_temp;
  1987. s32 reg_limit;
  1988. s32 current_regulatory;
  1989. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  1990. int i;
  1991. int c;
  1992. const struct iwl4965_channel_info *ch_info = NULL;
  1993. struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
  1994. const struct iwl4965_eeprom_calib_measure *measurement;
  1995. s16 voltage;
  1996. s32 init_voltage;
  1997. s32 voltage_compensation;
  1998. s32 degrees_per_05db_num;
  1999. s32 degrees_per_05db_denom;
  2000. s32 factory_temp;
  2001. s32 temperature_comp[2];
  2002. s32 factory_gain_index[2];
  2003. s32 factory_actual_pwr[2];
  2004. s32 power_index;
  2005. /* Sanity check requested level (dBm) */
  2006. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  2007. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  2008. priv->user_txpower_limit);
  2009. return -EINVAL;
  2010. }
  2011. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  2012. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  2013. priv->user_txpower_limit);
  2014. return -EINVAL;
  2015. }
  2016. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  2017. * are used for indexing into txpower table) */
  2018. user_target_power = 2 * priv->user_txpower_limit;
  2019. /* Get current (RXON) channel, band, width */
  2020. ch_info =
  2021. iwl4965_get_channel_txpower_info(priv, priv->phymode, channel);
  2022. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  2023. is_fat);
  2024. if (!ch_info)
  2025. return -EINVAL;
  2026. /* get txatten group, used to select 1) thermal txpower adjustment
  2027. * and 2) mimo txpower balance between Tx chains. */
  2028. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  2029. if (txatten_grp < 0)
  2030. return -EINVAL;
  2031. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  2032. channel, txatten_grp);
  2033. if (is_fat) {
  2034. if (ctrl_chan_high)
  2035. channel -= 2;
  2036. else
  2037. channel += 2;
  2038. }
  2039. /* hardware txpower limits ...
  2040. * saturation (clipping distortion) txpowers are in half-dBm */
  2041. if (band)
  2042. saturation_power = priv->eeprom.calib_info.saturation_power24;
  2043. else
  2044. saturation_power = priv->eeprom.calib_info.saturation_power52;
  2045. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  2046. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  2047. if (band)
  2048. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  2049. else
  2050. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  2051. }
  2052. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  2053. * max_power_avg values are in dBm, convert * 2 */
  2054. if (is_fat)
  2055. reg_limit = ch_info->fat_max_power_avg * 2;
  2056. else
  2057. reg_limit = ch_info->max_power_avg * 2;
  2058. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  2059. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  2060. if (band)
  2061. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  2062. else
  2063. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  2064. }
  2065. /* Interpolate txpower calibration values for this channel,
  2066. * based on factory calibration tests on spaced channels. */
  2067. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  2068. /* calculate tx gain adjustment based on power supply voltage */
  2069. voltage = priv->eeprom.calib_info.voltage;
  2070. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  2071. voltage_compensation =
  2072. iwl4965_get_voltage_compensation(voltage, init_voltage);
  2073. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  2074. init_voltage,
  2075. voltage, voltage_compensation);
  2076. /* get current temperature (Celsius) */
  2077. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  2078. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  2079. current_temp = KELVIN_TO_CELSIUS(current_temp);
  2080. /* select thermal txpower adjustment params, based on channel group
  2081. * (same frequency group used for mimo txatten adjustment) */
  2082. degrees_per_05db_num =
  2083. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  2084. degrees_per_05db_denom =
  2085. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  2086. /* get per-chain txpower values from factory measurements */
  2087. for (c = 0; c < 2; c++) {
  2088. measurement = &ch_eeprom_info.measurements[c][1];
  2089. /* txgain adjustment (in half-dB steps) based on difference
  2090. * between factory and current temperature */
  2091. factory_temp = measurement->temperature;
  2092. iwl4965_math_div_round((current_temp - factory_temp) *
  2093. degrees_per_05db_denom,
  2094. degrees_per_05db_num,
  2095. &temperature_comp[c]);
  2096. factory_gain_index[c] = measurement->gain_idx;
  2097. factory_actual_pwr[c] = measurement->actual_pow;
  2098. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  2099. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  2100. "curr tmp %d, comp %d steps\n",
  2101. factory_temp, current_temp,
  2102. temperature_comp[c]);
  2103. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  2104. factory_gain_index[c],
  2105. factory_actual_pwr[c]);
  2106. }
  2107. /* for each of 33 bit-rates (including 1 for CCK) */
  2108. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  2109. u8 is_mimo_rate;
  2110. union iwl4965_tx_power_dual_stream tx_power;
  2111. /* for mimo, reduce each chain's txpower by half
  2112. * (3dB, 6 steps), so total output power is regulatory
  2113. * compliant. */
  2114. if (i & 0x8) {
  2115. current_regulatory = reg_limit -
  2116. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  2117. is_mimo_rate = 1;
  2118. } else {
  2119. current_regulatory = reg_limit;
  2120. is_mimo_rate = 0;
  2121. }
  2122. /* find txpower limit, either hardware or regulatory */
  2123. power_limit = saturation_power - back_off_table[i];
  2124. if (power_limit > current_regulatory)
  2125. power_limit = current_regulatory;
  2126. /* reduce user's txpower request if necessary
  2127. * for this rate on this channel */
  2128. target_power = user_target_power;
  2129. if (target_power > power_limit)
  2130. target_power = power_limit;
  2131. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  2132. i, saturation_power - back_off_table[i],
  2133. current_regulatory, user_target_power,
  2134. target_power);
  2135. /* for each of 2 Tx chains (radio transmitters) */
  2136. for (c = 0; c < 2; c++) {
  2137. s32 atten_value;
  2138. if (is_mimo_rate)
  2139. atten_value =
  2140. (s32)le32_to_cpu(priv->card_alive_init.
  2141. tx_atten[txatten_grp][c]);
  2142. else
  2143. atten_value = 0;
  2144. /* calculate index; higher index means lower txpower */
  2145. power_index = (u8) (factory_gain_index[c] -
  2146. (target_power -
  2147. factory_actual_pwr[c]) -
  2148. temperature_comp[c] -
  2149. voltage_compensation +
  2150. atten_value);
  2151. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  2152. power_index); */
  2153. if (power_index < get_min_power_index(i, band))
  2154. power_index = get_min_power_index(i, band);
  2155. /* adjust 5 GHz index to support negative indexes */
  2156. if (!band)
  2157. power_index += 9;
  2158. /* CCK, rate 32, reduce txpower for CCK */
  2159. if (i == POWER_TABLE_CCK_ENTRY)
  2160. power_index +=
  2161. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  2162. /* stay within the table! */
  2163. if (power_index > 107) {
  2164. IWL_WARNING("txpower index %d > 107\n",
  2165. power_index);
  2166. power_index = 107;
  2167. }
  2168. if (power_index < 0) {
  2169. IWL_WARNING("txpower index %d < 0\n",
  2170. power_index);
  2171. power_index = 0;
  2172. }
  2173. /* fill txpower command for this rate/chain */
  2174. tx_power.s.radio_tx_gain[c] =
  2175. gain_table[band][power_index].radio;
  2176. tx_power.s.dsp_predis_atten[c] =
  2177. gain_table[band][power_index].dsp;
  2178. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  2179. "gain 0x%02x dsp %d\n",
  2180. c, atten_value, power_index,
  2181. tx_power.s.radio_tx_gain[c],
  2182. tx_power.s.dsp_predis_atten[c]);
  2183. }/* for each chain */
  2184. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  2185. }/* for each rate */
  2186. return 0;
  2187. }
  2188. /**
  2189. * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
  2190. *
  2191. * Uses the active RXON for channel, band, and characteristics (fat, high)
  2192. * The power limit is taken from priv->user_txpower_limit.
  2193. */
  2194. int iwl4965_hw_reg_send_txpower(struct iwl4965_priv *priv)
  2195. {
  2196. struct iwl4965_txpowertable_cmd cmd = { 0 };
  2197. int rc = 0;
  2198. u8 band = 0;
  2199. u8 is_fat = 0;
  2200. u8 ctrl_chan_high = 0;
  2201. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2202. /* If this gets hit a lot, switch it to a BUG() and catch
  2203. * the stack trace to find out who is calling this during
  2204. * a scan. */
  2205. IWL_WARNING("TX Power requested while scanning!\n");
  2206. return -EAGAIN;
  2207. }
  2208. band = ((priv->phymode == MODE_IEEE80211B) ||
  2209. (priv->phymode == MODE_IEEE80211G));
  2210. is_fat = is_fat_channel(priv->active_rxon.flags);
  2211. if (is_fat &&
  2212. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2213. ctrl_chan_high = 1;
  2214. cmd.band = band;
  2215. cmd.channel = priv->active_rxon.channel;
  2216. rc = iwl4965_fill_txpower_tbl(priv, band,
  2217. le16_to_cpu(priv->active_rxon.channel),
  2218. is_fat, ctrl_chan_high, &cmd.tx_power);
  2219. if (rc)
  2220. return rc;
  2221. rc = iwl4965_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  2222. return rc;
  2223. }
  2224. int iwl4965_hw_channel_switch(struct iwl4965_priv *priv, u16 channel)
  2225. {
  2226. int rc;
  2227. u8 band = 0;
  2228. u8 is_fat = 0;
  2229. u8 ctrl_chan_high = 0;
  2230. struct iwl4965_channel_switch_cmd cmd = { 0 };
  2231. const struct iwl4965_channel_info *ch_info;
  2232. band = ((priv->phymode == MODE_IEEE80211B) ||
  2233. (priv->phymode == MODE_IEEE80211G));
  2234. ch_info = iwl4965_get_channel_info(priv, priv->phymode, channel);
  2235. is_fat = is_fat_channel(priv->staging_rxon.flags);
  2236. if (is_fat &&
  2237. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2238. ctrl_chan_high = 1;
  2239. cmd.band = band;
  2240. cmd.expect_beacon = 0;
  2241. cmd.channel = cpu_to_le16(channel);
  2242. cmd.rxon_flags = priv->active_rxon.flags;
  2243. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  2244. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  2245. if (ch_info)
  2246. cmd.expect_beacon = is_channel_radar(ch_info);
  2247. else
  2248. cmd.expect_beacon = 1;
  2249. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  2250. ctrl_chan_high, &cmd.tx_power);
  2251. if (rc) {
  2252. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  2253. return rc;
  2254. }
  2255. rc = iwl4965_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  2256. return rc;
  2257. }
  2258. #define RTS_HCCA_RETRY_LIMIT 3
  2259. #define RTS_DFAULT_RETRY_LIMIT 60
  2260. void iwl4965_hw_build_tx_cmd_rate(struct iwl4965_priv *priv,
  2261. struct iwl4965_cmd *cmd,
  2262. struct ieee80211_tx_control *ctrl,
  2263. struct ieee80211_hdr *hdr, int sta_id,
  2264. int is_hcca)
  2265. {
  2266. struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
  2267. u8 rts_retry_limit = 0;
  2268. u8 data_retry_limit = 0;
  2269. u16 fc = le16_to_cpu(hdr->frame_control);
  2270. u8 rate_plcp;
  2271. u16 rate_flags = 0;
  2272. int rate_idx = min(ctrl->tx_rate & 0xffff, IWL_RATE_COUNT - 1);
  2273. rate_plcp = iwl4965_rates[rate_idx].plcp;
  2274. rts_retry_limit = (is_hcca) ?
  2275. RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
  2276. if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
  2277. rate_flags |= RATE_MCS_CCK_MSK;
  2278. if (ieee80211_is_probe_response(fc)) {
  2279. data_retry_limit = 3;
  2280. if (data_retry_limit < rts_retry_limit)
  2281. rts_retry_limit = data_retry_limit;
  2282. } else
  2283. data_retry_limit = IWL_DEFAULT_TX_RETRY;
  2284. if (priv->data_retry_limit != -1)
  2285. data_retry_limit = priv->data_retry_limit;
  2286. if (ieee80211_is_data(fc)) {
  2287. tx->initial_rate_index = 0;
  2288. tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
  2289. } else {
  2290. switch (fc & IEEE80211_FCTL_STYPE) {
  2291. case IEEE80211_STYPE_AUTH:
  2292. case IEEE80211_STYPE_DEAUTH:
  2293. case IEEE80211_STYPE_ASSOC_REQ:
  2294. case IEEE80211_STYPE_REASSOC_REQ:
  2295. if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
  2296. tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2297. tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
  2298. }
  2299. break;
  2300. default:
  2301. break;
  2302. }
  2303. /* Alternate between antenna A and B for successive frames */
  2304. if (priv->use_ant_b_for_management_frame) {
  2305. priv->use_ant_b_for_management_frame = 0;
  2306. rate_flags |= RATE_MCS_ANT_B_MSK;
  2307. } else {
  2308. priv->use_ant_b_for_management_frame = 1;
  2309. rate_flags |= RATE_MCS_ANT_A_MSK;
  2310. }
  2311. }
  2312. tx->rts_retry_limit = rts_retry_limit;
  2313. tx->data_retry_limit = data_retry_limit;
  2314. tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
  2315. }
  2316. int iwl4965_hw_get_rx_read(struct iwl4965_priv *priv)
  2317. {
  2318. struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
  2319. return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
  2320. }
  2321. int iwl4965_hw_get_temperature(struct iwl4965_priv *priv)
  2322. {
  2323. return priv->temperature;
  2324. }
  2325. unsigned int iwl4965_hw_get_beacon_cmd(struct iwl4965_priv *priv,
  2326. struct iwl4965_frame *frame, u8 rate)
  2327. {
  2328. struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
  2329. unsigned int frame_size;
  2330. tx_beacon_cmd = &frame->u.beacon;
  2331. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  2332. tx_beacon_cmd->tx.sta_id = IWL4965_BROADCAST_ID;
  2333. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2334. frame_size = iwl4965_fill_beacon_frame(priv,
  2335. tx_beacon_cmd->frame,
  2336. iwl4965_broadcast_addr,
  2337. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  2338. BUG_ON(frame_size > MAX_MPDU_SIZE);
  2339. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  2340. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  2341. tx_beacon_cmd->tx.rate_n_flags =
  2342. iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  2343. else
  2344. tx_beacon_cmd->tx.rate_n_flags =
  2345. iwl4965_hw_set_rate_n_flags(rate, 0);
  2346. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  2347. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  2348. return (sizeof(*tx_beacon_cmd) + frame_size);
  2349. }
  2350. /*
  2351. * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
  2352. * given Tx queue, and enable the DMA channel used for that queue.
  2353. *
  2354. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  2355. * channels supported in hardware.
  2356. */
  2357. int iwl4965_hw_tx_queue_init(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
  2358. {
  2359. int rc;
  2360. unsigned long flags;
  2361. int txq_id = txq->q.id;
  2362. spin_lock_irqsave(&priv->lock, flags);
  2363. rc = iwl4965_grab_nic_access(priv);
  2364. if (rc) {
  2365. spin_unlock_irqrestore(&priv->lock, flags);
  2366. return rc;
  2367. }
  2368. /* Circular buffer (TFD queue in DRAM) physical base address */
  2369. iwl4965_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  2370. txq->q.dma_addr >> 8);
  2371. /* Enable DMA channel, using same id as for TFD queue */
  2372. iwl4965_write_direct32(
  2373. priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
  2374. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  2375. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
  2376. iwl4965_release_nic_access(priv);
  2377. spin_unlock_irqrestore(&priv->lock, flags);
  2378. return 0;
  2379. }
  2380. int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl4965_priv *priv, void *ptr,
  2381. dma_addr_t addr, u16 len)
  2382. {
  2383. int index, is_odd;
  2384. struct iwl4965_tfd_frame *tfd = ptr;
  2385. u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
  2386. /* Each TFD can point to a maximum 20 Tx buffers */
  2387. if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
  2388. IWL_ERROR("Error can not send more than %d chunks\n",
  2389. MAX_NUM_OF_TBS);
  2390. return -EINVAL;
  2391. }
  2392. index = num_tbs / 2;
  2393. is_odd = num_tbs & 0x1;
  2394. if (!is_odd) {
  2395. tfd->pa[index].tb1_addr = cpu_to_le32(addr);
  2396. IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
  2397. iwl_get_dma_hi_address(addr));
  2398. IWL_SET_BITS(tfd->pa[index], tb1_len, len);
  2399. } else {
  2400. IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
  2401. (u32) (addr & 0xffff));
  2402. IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
  2403. IWL_SET_BITS(tfd->pa[index], tb2_len, len);
  2404. }
  2405. IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
  2406. return 0;
  2407. }
  2408. static void iwl4965_hw_card_show_info(struct iwl4965_priv *priv)
  2409. {
  2410. u16 hw_version = priv->eeprom.board_revision_4965;
  2411. IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
  2412. ((hw_version >> 8) & 0x0F),
  2413. ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
  2414. IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
  2415. priv->eeprom.board_pba_number_4965);
  2416. }
  2417. #define IWL_TX_CRC_SIZE 4
  2418. #define IWL_TX_DELIMITER_SIZE 4
  2419. /**
  2420. * iwl4965_tx_queue_update_wr_ptr - Set up entry in Tx byte-count array
  2421. */
  2422. int iwl4965_tx_queue_update_wr_ptr(struct iwl4965_priv *priv,
  2423. struct iwl4965_tx_queue *txq, u16 byte_cnt)
  2424. {
  2425. int len;
  2426. int txq_id = txq->q.id;
  2427. struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
  2428. if (txq->need_update == 0)
  2429. return 0;
  2430. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  2431. /* Set up byte count within first 256 entries */
  2432. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2433. tfd_offset[txq->q.write_ptr], byte_cnt, len);
  2434. /* If within first 64 entries, duplicate at end */
  2435. if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
  2436. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2437. tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
  2438. byte_cnt, len);
  2439. return 0;
  2440. }
  2441. /**
  2442. * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  2443. *
  2444. * Selects how many and which Rx receivers/antennas/chains to use.
  2445. * This should not be used for scan command ... it puts data in wrong place.
  2446. */
  2447. void iwl4965_set_rxon_chain(struct iwl4965_priv *priv)
  2448. {
  2449. u8 is_single = is_single_stream(priv);
  2450. u8 idle_state, rx_state;
  2451. priv->staging_rxon.rx_chain = 0;
  2452. rx_state = idle_state = 3;
  2453. /* Tell uCode which antennas are actually connected.
  2454. * Before first association, we assume all antennas are connected.
  2455. * Just after first association, iwl4965_noise_calibration()
  2456. * checks which antennas actually *are* connected. */
  2457. priv->staging_rxon.rx_chain |=
  2458. cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
  2459. /* How many receivers should we use? */
  2460. iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
  2461. priv->staging_rxon.rx_chain |=
  2462. cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
  2463. priv->staging_rxon.rx_chain |=
  2464. cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
  2465. if (!is_single && (rx_state >= 2) &&
  2466. !test_bit(STATUS_POWER_PMI, &priv->status))
  2467. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2468. else
  2469. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2470. IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
  2471. }
  2472. #ifdef CONFIG_IWL4965_HT
  2473. #ifdef CONFIG_IWL4965_HT_AGG
  2474. /*
  2475. get the traffic load value for tid
  2476. */
  2477. static u32 iwl4965_tl_get_load(struct iwl4965_priv *priv, u8 tid)
  2478. {
  2479. u32 load = 0;
  2480. u32 current_time = jiffies_to_msecs(jiffies);
  2481. u32 time_diff;
  2482. s32 index;
  2483. unsigned long flags;
  2484. struct iwl4965_traffic_load *tid_ptr = NULL;
  2485. if (tid >= TID_MAX_LOAD_COUNT)
  2486. return 0;
  2487. tid_ptr = &(priv->lq_mngr.agg_ctrl.traffic_load[tid]);
  2488. current_time -= current_time % TID_ROUND_VALUE;
  2489. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2490. if (!(tid_ptr->queue_count))
  2491. goto out;
  2492. time_diff = TIME_WRAP_AROUND(tid_ptr->time_stamp, current_time);
  2493. index = time_diff / TID_QUEUE_CELL_SPACING;
  2494. if (index >= TID_QUEUE_MAX_SIZE) {
  2495. u32 oldest_time = current_time - TID_MAX_TIME_DIFF;
  2496. while (tid_ptr->queue_count &&
  2497. (tid_ptr->time_stamp < oldest_time)) {
  2498. tid_ptr->total -= tid_ptr->packet_count[tid_ptr->head];
  2499. tid_ptr->packet_count[tid_ptr->head] = 0;
  2500. tid_ptr->time_stamp += TID_QUEUE_CELL_SPACING;
  2501. tid_ptr->queue_count--;
  2502. tid_ptr->head++;
  2503. if (tid_ptr->head >= TID_QUEUE_MAX_SIZE)
  2504. tid_ptr->head = 0;
  2505. }
  2506. }
  2507. load = tid_ptr->total;
  2508. out:
  2509. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2510. return load;
  2511. }
  2512. /*
  2513. increment traffic load value for tid and also remove
  2514. any old values if passed the certian time period
  2515. */
  2516. static void iwl4965_tl_add_packet(struct iwl4965_priv *priv, u8 tid)
  2517. {
  2518. u32 current_time = jiffies_to_msecs(jiffies);
  2519. u32 time_diff;
  2520. s32 index;
  2521. unsigned long flags;
  2522. struct iwl4965_traffic_load *tid_ptr = NULL;
  2523. if (tid >= TID_MAX_LOAD_COUNT)
  2524. return;
  2525. tid_ptr = &(priv->lq_mngr.agg_ctrl.traffic_load[tid]);
  2526. current_time -= current_time % TID_ROUND_VALUE;
  2527. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2528. if (!(tid_ptr->queue_count)) {
  2529. tid_ptr->total = 1;
  2530. tid_ptr->time_stamp = current_time;
  2531. tid_ptr->queue_count = 1;
  2532. tid_ptr->head = 0;
  2533. tid_ptr->packet_count[0] = 1;
  2534. goto out;
  2535. }
  2536. time_diff = TIME_WRAP_AROUND(tid_ptr->time_stamp, current_time);
  2537. index = time_diff / TID_QUEUE_CELL_SPACING;
  2538. if (index >= TID_QUEUE_MAX_SIZE) {
  2539. u32 oldest_time = current_time - TID_MAX_TIME_DIFF;
  2540. while (tid_ptr->queue_count &&
  2541. (tid_ptr->time_stamp < oldest_time)) {
  2542. tid_ptr->total -= tid_ptr->packet_count[tid_ptr->head];
  2543. tid_ptr->packet_count[tid_ptr->head] = 0;
  2544. tid_ptr->time_stamp += TID_QUEUE_CELL_SPACING;
  2545. tid_ptr->queue_count--;
  2546. tid_ptr->head++;
  2547. if (tid_ptr->head >= TID_QUEUE_MAX_SIZE)
  2548. tid_ptr->head = 0;
  2549. }
  2550. }
  2551. index = (tid_ptr->head + index) % TID_QUEUE_MAX_SIZE;
  2552. tid_ptr->packet_count[index] = tid_ptr->packet_count[index] + 1;
  2553. tid_ptr->total = tid_ptr->total + 1;
  2554. if ((index + 1) > tid_ptr->queue_count)
  2555. tid_ptr->queue_count = index + 1;
  2556. out:
  2557. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2558. }
  2559. #define MMAC_SCHED_MAX_NUMBER_OF_HT_BACK_FLOWS 7
  2560. enum HT_STATUS {
  2561. BA_STATUS_FAILURE = 0,
  2562. BA_STATUS_INITIATOR_DELBA,
  2563. BA_STATUS_RECIPIENT_DELBA,
  2564. BA_STATUS_RENEW_ADDBA_REQUEST,
  2565. BA_STATUS_ACTIVE,
  2566. };
  2567. /**
  2568. * iwl4964_tl_ba_avail - Find out if an unused aggregation queue is available
  2569. */
  2570. static u8 iwl4964_tl_ba_avail(struct iwl4965_priv *priv)
  2571. {
  2572. int i;
  2573. struct iwl4965_lq_mngr *lq;
  2574. u8 count = 0;
  2575. u16 msk;
  2576. lq = (struct iwl4965_lq_mngr *)&(priv->lq_mngr);
  2577. /* Find out how many agg queues are in use */
  2578. for (i = 0; i < TID_MAX_LOAD_COUNT ; i++) {
  2579. msk = 1 << i;
  2580. if ((lq->agg_ctrl.granted_ba & msk) ||
  2581. (lq->agg_ctrl.wait_for_agg_status & msk))
  2582. count++;
  2583. }
  2584. if (count < MMAC_SCHED_MAX_NUMBER_OF_HT_BACK_FLOWS)
  2585. return 1;
  2586. return 0;
  2587. }
  2588. static void iwl4965_ba_status(struct iwl4965_priv *priv,
  2589. u8 tid, enum HT_STATUS status);
  2590. static int iwl4965_perform_addba(struct iwl4965_priv *priv, u8 tid, u32 length,
  2591. u32 ba_timeout)
  2592. {
  2593. int rc;
  2594. rc = ieee80211_start_BA_session(priv->hw, priv->bssid, tid);
  2595. if (rc)
  2596. iwl4965_ba_status(priv, tid, BA_STATUS_FAILURE);
  2597. return rc;
  2598. }
  2599. static int iwl4965_perform_delba(struct iwl4965_priv *priv, u8 tid)
  2600. {
  2601. int rc;
  2602. rc = ieee80211_stop_BA_session(priv->hw, priv->bssid, tid);
  2603. if (rc)
  2604. iwl4965_ba_status(priv, tid, BA_STATUS_FAILURE);
  2605. return rc;
  2606. }
  2607. static void iwl4965_turn_on_agg_for_tid(struct iwl4965_priv *priv,
  2608. struct iwl4965_lq_mngr *lq,
  2609. u8 auto_agg, u8 tid)
  2610. {
  2611. u32 tid_msk = (1 << tid);
  2612. unsigned long flags;
  2613. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2614. /*
  2615. if ((auto_agg) && (!lq->enable_counter)){
  2616. lq->agg_ctrl.next_retry = 0;
  2617. lq->agg_ctrl.tid_retry = 0;
  2618. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2619. return;
  2620. }
  2621. */
  2622. if (!(lq->agg_ctrl.granted_ba & tid_msk) &&
  2623. (lq->agg_ctrl.requested_ba & tid_msk)) {
  2624. u8 available_queues;
  2625. u32 load;
  2626. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2627. available_queues = iwl4964_tl_ba_avail(priv);
  2628. load = iwl4965_tl_get_load(priv, tid);
  2629. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2630. if (!available_queues) {
  2631. if (auto_agg)
  2632. lq->agg_ctrl.tid_retry |= tid_msk;
  2633. else {
  2634. lq->agg_ctrl.requested_ba &= ~tid_msk;
  2635. lq->agg_ctrl.wait_for_agg_status &= ~tid_msk;
  2636. }
  2637. } else if ((auto_agg) &&
  2638. ((load <= lq->agg_ctrl.tid_traffic_load_threshold) ||
  2639. ((lq->agg_ctrl.wait_for_agg_status & tid_msk))))
  2640. lq->agg_ctrl.tid_retry |= tid_msk;
  2641. else {
  2642. lq->agg_ctrl.wait_for_agg_status |= tid_msk;
  2643. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2644. iwl4965_perform_addba(priv, tid, 0x40,
  2645. lq->agg_ctrl.ba_timeout);
  2646. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2647. }
  2648. }
  2649. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2650. }
  2651. static void iwl4965_turn_on_agg(struct iwl4965_priv *priv, u8 tid)
  2652. {
  2653. struct iwl4965_lq_mngr *lq;
  2654. unsigned long flags;
  2655. lq = (struct iwl4965_lq_mngr *)&(priv->lq_mngr);
  2656. if ((tid < TID_MAX_LOAD_COUNT))
  2657. iwl4965_turn_on_agg_for_tid(priv, lq, lq->agg_ctrl.auto_agg,
  2658. tid);
  2659. else if (tid == TID_ALL_SPECIFIED) {
  2660. if (lq->agg_ctrl.requested_ba) {
  2661. for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++)
  2662. iwl4965_turn_on_agg_for_tid(priv, lq,
  2663. lq->agg_ctrl.auto_agg, tid);
  2664. } else {
  2665. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2666. lq->agg_ctrl.tid_retry = 0;
  2667. lq->agg_ctrl.next_retry = 0;
  2668. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2669. }
  2670. }
  2671. }
  2672. void iwl4965_turn_off_agg(struct iwl4965_priv *priv, u8 tid)
  2673. {
  2674. u32 tid_msk;
  2675. struct iwl4965_lq_mngr *lq;
  2676. unsigned long flags;
  2677. lq = (struct iwl4965_lq_mngr *)&(priv->lq_mngr);
  2678. if ((tid < TID_MAX_LOAD_COUNT)) {
  2679. tid_msk = 1 << tid;
  2680. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2681. lq->agg_ctrl.wait_for_agg_status |= tid_msk;
  2682. lq->agg_ctrl.requested_ba &= ~tid_msk;
  2683. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2684. iwl4965_perform_delba(priv, tid);
  2685. } else if (tid == TID_ALL_SPECIFIED) {
  2686. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2687. for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++) {
  2688. tid_msk = 1 << tid;
  2689. lq->agg_ctrl.wait_for_agg_status |= tid_msk;
  2690. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2691. iwl4965_perform_delba(priv, tid);
  2692. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2693. }
  2694. lq->agg_ctrl.requested_ba = 0;
  2695. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2696. }
  2697. }
  2698. /**
  2699. * iwl4965_ba_status - Update driver's link quality mgr with tid's HT status
  2700. */
  2701. static void iwl4965_ba_status(struct iwl4965_priv *priv,
  2702. u8 tid, enum HT_STATUS status)
  2703. {
  2704. struct iwl4965_lq_mngr *lq;
  2705. u32 tid_msk = (1 << tid);
  2706. unsigned long flags;
  2707. lq = (struct iwl4965_lq_mngr *)&(priv->lq_mngr);
  2708. if ((tid >= TID_MAX_LOAD_COUNT))
  2709. goto out;
  2710. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2711. switch (status) {
  2712. case BA_STATUS_ACTIVE:
  2713. if (!(lq->agg_ctrl.granted_ba & tid_msk))
  2714. lq->agg_ctrl.granted_ba |= tid_msk;
  2715. break;
  2716. default:
  2717. if ((lq->agg_ctrl.granted_ba & tid_msk))
  2718. lq->agg_ctrl.granted_ba &= ~tid_msk;
  2719. break;
  2720. }
  2721. lq->agg_ctrl.wait_for_agg_status &= ~tid_msk;
  2722. if (status != BA_STATUS_ACTIVE) {
  2723. if (lq->agg_ctrl.auto_agg) {
  2724. lq->agg_ctrl.tid_retry |= tid_msk;
  2725. lq->agg_ctrl.next_retry =
  2726. jiffies + msecs_to_jiffies(500);
  2727. } else
  2728. lq->agg_ctrl.requested_ba &= ~tid_msk;
  2729. }
  2730. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2731. out:
  2732. return;
  2733. }
  2734. static void iwl4965_bg_agg_work(struct work_struct *work)
  2735. {
  2736. struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
  2737. agg_work);
  2738. u32 tid;
  2739. u32 retry_tid;
  2740. u32 tid_msk;
  2741. unsigned long flags;
  2742. struct iwl4965_lq_mngr *lq = (struct iwl4965_lq_mngr *)&(priv->lq_mngr);
  2743. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2744. retry_tid = lq->agg_ctrl.tid_retry;
  2745. lq->agg_ctrl.tid_retry = 0;
  2746. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2747. if (retry_tid == TID_ALL_SPECIFIED)
  2748. iwl4965_turn_on_agg(priv, TID_ALL_SPECIFIED);
  2749. else {
  2750. for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++) {
  2751. tid_msk = (1 << tid);
  2752. if (retry_tid & tid_msk)
  2753. iwl4965_turn_on_agg(priv, tid);
  2754. }
  2755. }
  2756. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2757. if (lq->agg_ctrl.tid_retry)
  2758. lq->agg_ctrl.next_retry = jiffies + msecs_to_jiffies(500);
  2759. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2760. return;
  2761. }
  2762. /* TODO: move this functionality to rate scaling */
  2763. void iwl4965_tl_get_stats(struct iwl4965_priv *priv,
  2764. struct ieee80211_hdr *hdr)
  2765. {
  2766. __le16 *qc = ieee80211_get_qos_ctrl(hdr);
  2767. if (qc &&
  2768. (priv->iw_mode != IEEE80211_IF_TYPE_IBSS)) {
  2769. u8 tid = 0;
  2770. tid = (u8) (le16_to_cpu(*qc) & 0xF);
  2771. if (tid < TID_MAX_LOAD_COUNT)
  2772. iwl4965_tl_add_packet(priv, tid);
  2773. }
  2774. if (priv->lq_mngr.agg_ctrl.next_retry &&
  2775. (time_after(priv->lq_mngr.agg_ctrl.next_retry, jiffies))) {
  2776. unsigned long flags;
  2777. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2778. priv->lq_mngr.agg_ctrl.next_retry = 0;
  2779. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2780. schedule_work(&priv->agg_work);
  2781. }
  2782. }
  2783. #endif /*CONFIG_IWL4965_HT_AGG */
  2784. #endif /* CONFIG_IWL4965_HT */
  2785. /**
  2786. * sign_extend - Sign extend a value using specified bit as sign-bit
  2787. *
  2788. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  2789. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  2790. *
  2791. * @param oper value to sign extend
  2792. * @param index 0 based bit index (0<=index<32) to sign bit
  2793. */
  2794. static s32 sign_extend(u32 oper, int index)
  2795. {
  2796. u8 shift = 31 - index;
  2797. return (s32)(oper << shift) >> shift;
  2798. }
  2799. /**
  2800. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  2801. * @statistics: Provides the temperature reading from the uCode
  2802. *
  2803. * A return of <0 indicates bogus data in the statistics
  2804. */
  2805. int iwl4965_get_temperature(const struct iwl4965_priv *priv)
  2806. {
  2807. s32 temperature;
  2808. s32 vt;
  2809. s32 R1, R2, R3;
  2810. u32 R4;
  2811. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  2812. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  2813. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  2814. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  2815. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  2816. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  2817. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  2818. } else {
  2819. IWL_DEBUG_TEMP("Running temperature calibration\n");
  2820. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  2821. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  2822. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  2823. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  2824. }
  2825. /*
  2826. * Temperature is only 23 bits, so sign extend out to 32.
  2827. *
  2828. * NOTE If we haven't received a statistics notification yet
  2829. * with an updated temperature, use R4 provided to us in the
  2830. * "initialize" ALIVE response.
  2831. */
  2832. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  2833. vt = sign_extend(R4, 23);
  2834. else
  2835. vt = sign_extend(
  2836. le32_to_cpu(priv->statistics.general.temperature), 23);
  2837. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  2838. R1, R2, R3, vt);
  2839. if (R3 == R1) {
  2840. IWL_ERROR("Calibration conflict R1 == R3\n");
  2841. return -1;
  2842. }
  2843. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  2844. * Add offset to center the adjustment around 0 degrees Centigrade. */
  2845. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  2846. temperature /= (R3 - R1);
  2847. temperature = (temperature * 97) / 100 +
  2848. TEMPERATURE_CALIB_KELVIN_OFFSET;
  2849. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  2850. KELVIN_TO_CELSIUS(temperature));
  2851. return temperature;
  2852. }
  2853. /* Adjust Txpower only if temperature variance is greater than threshold. */
  2854. #define IWL_TEMPERATURE_THRESHOLD 3
  2855. /**
  2856. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  2857. *
  2858. * If the temperature changed has changed sufficiently, then a recalibration
  2859. * is needed.
  2860. *
  2861. * Assumes caller will replace priv->last_temperature once calibration
  2862. * executed.
  2863. */
  2864. static int iwl4965_is_temp_calib_needed(struct iwl4965_priv *priv)
  2865. {
  2866. int temp_diff;
  2867. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  2868. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  2869. return 0;
  2870. }
  2871. temp_diff = priv->temperature - priv->last_temperature;
  2872. /* get absolute value */
  2873. if (temp_diff < 0) {
  2874. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  2875. temp_diff = -temp_diff;
  2876. } else if (temp_diff == 0)
  2877. IWL_DEBUG_POWER("Same temp, \n");
  2878. else
  2879. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  2880. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  2881. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  2882. return 0;
  2883. }
  2884. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  2885. return 1;
  2886. }
  2887. /* Calculate noise level, based on measurements during network silence just
  2888. * before arriving beacon. This measurement can be done only if we know
  2889. * exactly when to expect beacons, therefore only when we're associated. */
  2890. static void iwl4965_rx_calc_noise(struct iwl4965_priv *priv)
  2891. {
  2892. struct statistics_rx_non_phy *rx_info
  2893. = &(priv->statistics.rx.general);
  2894. int num_active_rx = 0;
  2895. int total_silence = 0;
  2896. int bcn_silence_a =
  2897. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  2898. int bcn_silence_b =
  2899. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  2900. int bcn_silence_c =
  2901. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  2902. if (bcn_silence_a) {
  2903. total_silence += bcn_silence_a;
  2904. num_active_rx++;
  2905. }
  2906. if (bcn_silence_b) {
  2907. total_silence += bcn_silence_b;
  2908. num_active_rx++;
  2909. }
  2910. if (bcn_silence_c) {
  2911. total_silence += bcn_silence_c;
  2912. num_active_rx++;
  2913. }
  2914. /* Average among active antennas */
  2915. if (num_active_rx)
  2916. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  2917. else
  2918. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2919. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  2920. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  2921. priv->last_rx_noise);
  2922. }
  2923. void iwl4965_hw_rx_statistics(struct iwl4965_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
  2924. {
  2925. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  2926. int change;
  2927. s32 temp;
  2928. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  2929. (int)sizeof(priv->statistics), pkt->len);
  2930. change = ((priv->statistics.general.temperature !=
  2931. pkt->u.stats.general.temperature) ||
  2932. ((priv->statistics.flag &
  2933. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  2934. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  2935. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  2936. set_bit(STATUS_STATISTICS, &priv->status);
  2937. /* Reschedule the statistics timer to occur in
  2938. * REG_RECALIB_PERIOD seconds to ensure we get a
  2939. * thermal update even if the uCode doesn't give
  2940. * us one */
  2941. mod_timer(&priv->statistics_periodic, jiffies +
  2942. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  2943. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2944. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  2945. iwl4965_rx_calc_noise(priv);
  2946. #ifdef CONFIG_IWL4965_SENSITIVITY
  2947. queue_work(priv->workqueue, &priv->sensitivity_work);
  2948. #endif
  2949. }
  2950. /* If the hardware hasn't reported a change in
  2951. * temperature then don't bother computing a
  2952. * calibrated temperature value */
  2953. if (!change)
  2954. return;
  2955. temp = iwl4965_get_temperature(priv);
  2956. if (temp < 0)
  2957. return;
  2958. if (priv->temperature != temp) {
  2959. if (priv->temperature)
  2960. IWL_DEBUG_TEMP("Temperature changed "
  2961. "from %dC to %dC\n",
  2962. KELVIN_TO_CELSIUS(priv->temperature),
  2963. KELVIN_TO_CELSIUS(temp));
  2964. else
  2965. IWL_DEBUG_TEMP("Temperature "
  2966. "initialized to %dC\n",
  2967. KELVIN_TO_CELSIUS(temp));
  2968. }
  2969. priv->temperature = temp;
  2970. set_bit(STATUS_TEMPERATURE, &priv->status);
  2971. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2972. iwl4965_is_temp_calib_needed(priv))
  2973. queue_work(priv->workqueue, &priv->txpower_work);
  2974. }
  2975. static void iwl4965_add_radiotap(struct iwl4965_priv *priv,
  2976. struct sk_buff *skb,
  2977. struct iwl4965_rx_phy_res *rx_start,
  2978. struct ieee80211_rx_status *stats,
  2979. u32 ampdu_status)
  2980. {
  2981. s8 signal = stats->ssi;
  2982. s8 noise = 0;
  2983. int rate = stats->rate;
  2984. u64 tsf = stats->mactime;
  2985. __le16 phy_flags_hw = rx_start->phy_flags;
  2986. struct iwl4965_rt_rx_hdr {
  2987. struct ieee80211_radiotap_header rt_hdr;
  2988. __le64 rt_tsf; /* TSF */
  2989. u8 rt_flags; /* radiotap packet flags */
  2990. u8 rt_rate; /* rate in 500kb/s */
  2991. __le16 rt_channelMHz; /* channel in MHz */
  2992. __le16 rt_chbitmask; /* channel bitfield */
  2993. s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
  2994. s8 rt_dbmnoise;
  2995. u8 rt_antenna; /* antenna number */
  2996. } __attribute__ ((packed)) *iwl4965_rt;
  2997. /* TODO: We won't have enough headroom for HT frames. Fix it later. */
  2998. if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
  2999. if (net_ratelimit())
  3000. printk(KERN_ERR "not enough headroom [%d] for "
  3001. "radiotap head [%zd]\n",
  3002. skb_headroom(skb), sizeof(*iwl4965_rt));
  3003. return;
  3004. }
  3005. /* put radiotap header in front of 802.11 header and data */
  3006. iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
  3007. /* initialise radiotap header */
  3008. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  3009. iwl4965_rt->rt_hdr.it_pad = 0;
  3010. /* total header + data */
  3011. put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
  3012. &iwl4965_rt->rt_hdr.it_len);
  3013. /* Indicate all the fields we add to the radiotap header */
  3014. put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  3015. (1 << IEEE80211_RADIOTAP_FLAGS) |
  3016. (1 << IEEE80211_RADIOTAP_RATE) |
  3017. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  3018. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  3019. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  3020. (1 << IEEE80211_RADIOTAP_ANTENNA)),
  3021. &iwl4965_rt->rt_hdr.it_present);
  3022. /* Zero the flags, we'll add to them as we go */
  3023. iwl4965_rt->rt_flags = 0;
  3024. put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
  3025. iwl4965_rt->rt_dbmsignal = signal;
  3026. iwl4965_rt->rt_dbmnoise = noise;
  3027. /* Convert the channel frequency and set the flags */
  3028. put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
  3029. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  3030. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  3031. IEEE80211_CHAN_5GHZ),
  3032. &iwl4965_rt->rt_chbitmask);
  3033. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  3034. put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
  3035. IEEE80211_CHAN_2GHZ),
  3036. &iwl4965_rt->rt_chbitmask);
  3037. else /* 802.11g */
  3038. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  3039. IEEE80211_CHAN_2GHZ),
  3040. &iwl4965_rt->rt_chbitmask);
  3041. rate = iwl4965_rate_index_from_plcp(rate);
  3042. if (rate == -1)
  3043. iwl4965_rt->rt_rate = 0;
  3044. else
  3045. iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
  3046. /*
  3047. * "antenna number"
  3048. *
  3049. * It seems that the antenna field in the phy flags value
  3050. * is actually a bitfield. This is undefined by radiotap,
  3051. * it wants an actual antenna number but I always get "7"
  3052. * for most legacy frames I receive indicating that the
  3053. * same frame was received on all three RX chains.
  3054. *
  3055. * I think this field should be removed in favour of a
  3056. * new 802.11n radiotap field "RX chains" that is defined
  3057. * as a bitmask.
  3058. */
  3059. iwl4965_rt->rt_antenna =
  3060. le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  3061. /* set the preamble flag if appropriate */
  3062. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  3063. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  3064. stats->flag |= RX_FLAG_RADIOTAP;
  3065. }
  3066. static void iwl4965_handle_data_packet(struct iwl4965_priv *priv, int is_data,
  3067. int include_phy,
  3068. struct iwl4965_rx_mem_buffer *rxb,
  3069. struct ieee80211_rx_status *stats)
  3070. {
  3071. struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
  3072. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  3073. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  3074. struct ieee80211_hdr *hdr;
  3075. u16 len;
  3076. __le32 *rx_end;
  3077. unsigned int skblen;
  3078. u32 ampdu_status;
  3079. if (!include_phy && priv->last_phy_res[0])
  3080. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  3081. if (!rx_start) {
  3082. IWL_ERROR("MPDU frame without a PHY data\n");
  3083. return;
  3084. }
  3085. if (include_phy) {
  3086. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  3087. rx_start->cfg_phy_cnt);
  3088. len = le16_to_cpu(rx_start->byte_count);
  3089. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  3090. sizeof(struct iwl4965_rx_phy_res) +
  3091. rx_start->cfg_phy_cnt + len);
  3092. } else {
  3093. struct iwl4965_rx_mpdu_res_start *amsdu =
  3094. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  3095. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  3096. sizeof(struct iwl4965_rx_mpdu_res_start));
  3097. len = le16_to_cpu(amsdu->byte_count);
  3098. rx_start->byte_count = amsdu->byte_count;
  3099. rx_end = (__le32 *) (((u8 *) hdr) + len);
  3100. }
  3101. if (len > priv->hw_setting.max_pkt_size || len < 16) {
  3102. IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
  3103. return;
  3104. }
  3105. ampdu_status = le32_to_cpu(*rx_end);
  3106. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  3107. /* start from MAC */
  3108. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  3109. skb_put(rxb->skb, len); /* end where data ends */
  3110. /* We only process data packets if the interface is open */
  3111. if (unlikely(!priv->is_open)) {
  3112. IWL_DEBUG_DROP_LIMIT
  3113. ("Dropping packet while interface is not open.\n");
  3114. return;
  3115. }
  3116. stats->flag = 0;
  3117. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  3118. if (iwl4965_param_hwcrypto)
  3119. iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
  3120. if (priv->add_radiotap)
  3121. iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
  3122. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  3123. priv->alloc_rxb_skb--;
  3124. rxb->skb = NULL;
  3125. #ifdef LED
  3126. priv->led_packets += len;
  3127. iwl4965_setup_activity_timer(priv);
  3128. #endif
  3129. }
  3130. /* Calc max signal level (dBm) among 3 possible receivers */
  3131. static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
  3132. {
  3133. /* data from PHY/DSP regarding signal strength, etc.,
  3134. * contents are always there, not configurable by host. */
  3135. struct iwl4965_rx_non_cfg_phy *ncphy =
  3136. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  3137. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  3138. >> IWL_AGC_DB_POS;
  3139. u32 valid_antennae =
  3140. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  3141. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  3142. u8 max_rssi = 0;
  3143. u32 i;
  3144. /* Find max rssi among 3 possible receivers.
  3145. * These values are measured by the digital signal processor (DSP).
  3146. * They should stay fairly constant even as the signal strength varies,
  3147. * if the radio's automatic gain control (AGC) is working right.
  3148. * AGC value (see below) will provide the "interesting" info. */
  3149. for (i = 0; i < 3; i++)
  3150. if (valid_antennae & (1 << i))
  3151. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  3152. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  3153. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  3154. max_rssi, agc);
  3155. /* dBm = max_rssi dB - agc dB - constant.
  3156. * Higher AGC (higher radio gain) means lower signal. */
  3157. return (max_rssi - agc - IWL_RSSI_OFFSET);
  3158. }
  3159. #ifdef CONFIG_IWL4965_HT
  3160. /* Parsed Information Elements */
  3161. struct ieee802_11_elems {
  3162. u8 *ds_params;
  3163. u8 ds_params_len;
  3164. u8 *tim;
  3165. u8 tim_len;
  3166. u8 *ibss_params;
  3167. u8 ibss_params_len;
  3168. u8 *erp_info;
  3169. u8 erp_info_len;
  3170. u8 *ht_cap_param;
  3171. u8 ht_cap_param_len;
  3172. u8 *ht_extra_param;
  3173. u8 ht_extra_param_len;
  3174. };
  3175. static int parse_elems(u8 *start, size_t len, struct ieee802_11_elems *elems)
  3176. {
  3177. size_t left = len;
  3178. u8 *pos = start;
  3179. int unknown = 0;
  3180. memset(elems, 0, sizeof(*elems));
  3181. while (left >= 2) {
  3182. u8 id, elen;
  3183. id = *pos++;
  3184. elen = *pos++;
  3185. left -= 2;
  3186. if (elen > left)
  3187. return -1;
  3188. switch (id) {
  3189. case WLAN_EID_DS_PARAMS:
  3190. elems->ds_params = pos;
  3191. elems->ds_params_len = elen;
  3192. break;
  3193. case WLAN_EID_TIM:
  3194. elems->tim = pos;
  3195. elems->tim_len = elen;
  3196. break;
  3197. case WLAN_EID_IBSS_PARAMS:
  3198. elems->ibss_params = pos;
  3199. elems->ibss_params_len = elen;
  3200. break;
  3201. case WLAN_EID_ERP_INFO:
  3202. elems->erp_info = pos;
  3203. elems->erp_info_len = elen;
  3204. break;
  3205. case WLAN_EID_HT_CAPABILITY:
  3206. elems->ht_cap_param = pos;
  3207. elems->ht_cap_param_len = elen;
  3208. break;
  3209. case WLAN_EID_HT_EXTRA_INFO:
  3210. elems->ht_extra_param = pos;
  3211. elems->ht_extra_param_len = elen;
  3212. break;
  3213. default:
  3214. unknown++;
  3215. break;
  3216. }
  3217. left -= elen;
  3218. pos += elen;
  3219. }
  3220. return 0;
  3221. }
  3222. void iwl4965_init_ht_hw_capab(struct ieee80211_ht_info *ht_info, int mode)
  3223. {
  3224. ht_info->cap = 0;
  3225. memset(ht_info->supp_mcs_set, 0, 16);
  3226. ht_info->ht_supported = 1;
  3227. if (mode == MODE_IEEE80211A) {
  3228. ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
  3229. ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
  3230. ht_info->supp_mcs_set[4] = 0x01;
  3231. }
  3232. ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
  3233. ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
  3234. ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
  3235. (IWL_MIMO_PS_NONE << 2));
  3236. if (iwl4965_param_amsdu_size_8K) {
  3237. printk(KERN_DEBUG "iwl4965 in A-MSDU 8K support mode\n");
  3238. ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
  3239. }
  3240. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  3241. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  3242. ht_info->supp_mcs_set[0] = 0xFF;
  3243. ht_info->supp_mcs_set[1] = 0xFF;
  3244. }
  3245. #endif /* CONFIG_IWL4965_HT */
  3246. static void iwl4965_sta_modify_ps_wake(struct iwl4965_priv *priv, int sta_id)
  3247. {
  3248. unsigned long flags;
  3249. spin_lock_irqsave(&priv->sta_lock, flags);
  3250. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  3251. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  3252. priv->stations[sta_id].sta.sta.modify_mask = 0;
  3253. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3254. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3255. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3256. }
  3257. static void iwl4965_update_ps_mode(struct iwl4965_priv *priv, u16 ps_bit, u8 *addr)
  3258. {
  3259. /* FIXME: need locking over ps_status ??? */
  3260. u8 sta_id = iwl4965_hw_find_station(priv, addr);
  3261. if (sta_id != IWL_INVALID_STATION) {
  3262. u8 sta_awake = priv->stations[sta_id].
  3263. ps_status == STA_PS_STATUS_WAKE;
  3264. if (sta_awake && ps_bit)
  3265. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  3266. else if (!sta_awake && !ps_bit) {
  3267. iwl4965_sta_modify_ps_wake(priv, sta_id);
  3268. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  3269. }
  3270. }
  3271. }
  3272. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  3273. /* Called for REPLY_4965_RX (legacy ABG frames), or
  3274. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  3275. static void iwl4965_rx_reply_rx(struct iwl4965_priv *priv,
  3276. struct iwl4965_rx_mem_buffer *rxb)
  3277. {
  3278. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3279. /* Use phy data (Rx signal strength, etc.) contained within
  3280. * this rx packet for legacy frames,
  3281. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  3282. int include_phy = (pkt->hdr.cmd == REPLY_4965_RX);
  3283. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  3284. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  3285. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  3286. __le32 *rx_end;
  3287. unsigned int len = 0;
  3288. struct ieee80211_hdr *header;
  3289. u16 fc;
  3290. struct ieee80211_rx_status stats = {
  3291. .mactime = le64_to_cpu(rx_start->timestamp),
  3292. .channel = le16_to_cpu(rx_start->channel),
  3293. .phymode =
  3294. (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  3295. MODE_IEEE80211G : MODE_IEEE80211A,
  3296. .antenna = 0,
  3297. .rate = iwl4965_hw_get_rate(rx_start->rate_n_flags),
  3298. .flag = 0,
  3299. };
  3300. u8 network_packet;
  3301. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  3302. IWL_DEBUG_DROP
  3303. ("dsp size out of range [0,20]: "
  3304. "%d/n", rx_start->cfg_phy_cnt);
  3305. return;
  3306. }
  3307. if (!include_phy) {
  3308. if (priv->last_phy_res[0])
  3309. rx_start = (struct iwl4965_rx_phy_res *)
  3310. &priv->last_phy_res[1];
  3311. else
  3312. rx_start = NULL;
  3313. }
  3314. if (!rx_start) {
  3315. IWL_ERROR("MPDU frame without a PHY data\n");
  3316. return;
  3317. }
  3318. if (include_phy) {
  3319. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  3320. + rx_start->cfg_phy_cnt);
  3321. len = le16_to_cpu(rx_start->byte_count);
  3322. rx_end = (__le32 *) (pkt->u.raw + rx_start->cfg_phy_cnt +
  3323. sizeof(struct iwl4965_rx_phy_res) + len);
  3324. } else {
  3325. struct iwl4965_rx_mpdu_res_start *amsdu =
  3326. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  3327. header = (void *)(pkt->u.raw +
  3328. sizeof(struct iwl4965_rx_mpdu_res_start));
  3329. len = le16_to_cpu(amsdu->byte_count);
  3330. rx_end = (__le32 *) (pkt->u.raw +
  3331. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  3332. }
  3333. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  3334. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  3335. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  3336. le32_to_cpu(*rx_end));
  3337. return;
  3338. }
  3339. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  3340. stats.freq = ieee80211chan2mhz(stats.channel);
  3341. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  3342. stats.ssi = iwl4965_calc_rssi(rx_start);
  3343. /* Meaningful noise values are available only from beacon statistics,
  3344. * which are gathered only when associated, and indicate noise
  3345. * only for the associated network channel ...
  3346. * Ignore these noise values while scanning (other channels) */
  3347. if (iwl4965_is_associated(priv) &&
  3348. !test_bit(STATUS_SCANNING, &priv->status)) {
  3349. stats.noise = priv->last_rx_noise;
  3350. stats.signal = iwl4965_calc_sig_qual(stats.ssi, stats.noise);
  3351. } else {
  3352. stats.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3353. stats.signal = iwl4965_calc_sig_qual(stats.ssi, 0);
  3354. }
  3355. /* Reset beacon noise level if not associated. */
  3356. if (!iwl4965_is_associated(priv))
  3357. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3358. #ifdef CONFIG_IWL4965_DEBUG
  3359. /* TODO: Parts of iwl4965_report_frame are broken for 4965 */
  3360. if (iwl4965_debug_level & (IWL_DL_RX))
  3361. /* Set "1" to report good data frames in groups of 100 */
  3362. iwl4965_report_frame(priv, pkt, header, 1);
  3363. if (iwl4965_debug_level & (IWL_DL_RX | IWL_DL_STATS))
  3364. IWL_DEBUG_RX("Rssi %d, noise %d, qual %d, TSF %lu\n",
  3365. stats.ssi, stats.noise, stats.signal,
  3366. (long unsigned int)le64_to_cpu(rx_start->timestamp));
  3367. #endif
  3368. network_packet = iwl4965_is_network_packet(priv, header);
  3369. if (network_packet) {
  3370. priv->last_rx_rssi = stats.ssi;
  3371. priv->last_beacon_time = priv->ucode_beacon_time;
  3372. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  3373. }
  3374. fc = le16_to_cpu(header->frame_control);
  3375. switch (fc & IEEE80211_FCTL_FTYPE) {
  3376. case IEEE80211_FTYPE_MGMT:
  3377. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3378. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3379. header->addr2);
  3380. switch (fc & IEEE80211_FCTL_STYPE) {
  3381. case IEEE80211_STYPE_PROBE_RESP:
  3382. case IEEE80211_STYPE_BEACON:
  3383. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA &&
  3384. !compare_ether_addr(header->addr2, priv->bssid)) ||
  3385. (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
  3386. !compare_ether_addr(header->addr3, priv->bssid))) {
  3387. struct ieee80211_mgmt *mgmt =
  3388. (struct ieee80211_mgmt *)header;
  3389. u64 timestamp =
  3390. le64_to_cpu(mgmt->u.beacon.timestamp);
  3391. priv->timestamp0 = timestamp & 0xFFFFFFFF;
  3392. priv->timestamp1 =
  3393. (timestamp >> 32) & 0xFFFFFFFF;
  3394. priv->beacon_int = le16_to_cpu(
  3395. mgmt->u.beacon.beacon_int);
  3396. if (priv->call_post_assoc_from_beacon &&
  3397. (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
  3398. priv->call_post_assoc_from_beacon = 0;
  3399. queue_work(priv->workqueue,
  3400. &priv->post_associate.work);
  3401. }
  3402. }
  3403. break;
  3404. case IEEE80211_STYPE_ACTION:
  3405. break;
  3406. /*
  3407. * TODO: Use the new callback function from
  3408. * mac80211 instead of sniffing these packets.
  3409. */
  3410. case IEEE80211_STYPE_ASSOC_RESP:
  3411. case IEEE80211_STYPE_REASSOC_RESP:
  3412. if (network_packet) {
  3413. #ifdef CONFIG_IWL4965_HT
  3414. u8 *pos = NULL;
  3415. struct ieee802_11_elems elems;
  3416. #endif /*CONFIG_IWL4965_HT */
  3417. struct ieee80211_mgmt *mgnt =
  3418. (struct ieee80211_mgmt *)header;
  3419. /* We have just associated, give some
  3420. * time for the 4-way handshake if
  3421. * any. Don't start scan too early. */
  3422. priv->next_scan_jiffies = jiffies +
  3423. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  3424. priv->assoc_id = (~((1 << 15) | (1 << 14))
  3425. & le16_to_cpu(mgnt->u.assoc_resp.aid));
  3426. priv->assoc_capability =
  3427. le16_to_cpu(
  3428. mgnt->u.assoc_resp.capab_info);
  3429. #ifdef CONFIG_IWL4965_HT
  3430. pos = mgnt->u.assoc_resp.variable;
  3431. if (!parse_elems(pos,
  3432. len - (pos - (u8 *) mgnt),
  3433. &elems)) {
  3434. if (elems.ht_extra_param &&
  3435. elems.ht_cap_param)
  3436. break;
  3437. }
  3438. #endif /*CONFIG_IWL4965_HT */
  3439. /* assoc_id is 0 no association */
  3440. if (!priv->assoc_id)
  3441. break;
  3442. if (priv->beacon_int)
  3443. queue_work(priv->workqueue,
  3444. &priv->post_associate.work);
  3445. else
  3446. priv->call_post_assoc_from_beacon = 1;
  3447. }
  3448. break;
  3449. case IEEE80211_STYPE_PROBE_REQ:
  3450. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  3451. !iwl4965_is_associated(priv)) {
  3452. DECLARE_MAC_BUF(mac1);
  3453. DECLARE_MAC_BUF(mac2);
  3454. DECLARE_MAC_BUF(mac3);
  3455. IWL_DEBUG_DROP("Dropping (non network): "
  3456. "%s, %s, %s\n",
  3457. print_mac(mac1, header->addr1),
  3458. print_mac(mac2, header->addr2),
  3459. print_mac(mac3, header->addr3));
  3460. return;
  3461. }
  3462. }
  3463. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &stats);
  3464. break;
  3465. case IEEE80211_FTYPE_CTL:
  3466. #ifdef CONFIG_IWL4965_HT
  3467. switch (fc & IEEE80211_FCTL_STYPE) {
  3468. case IEEE80211_STYPE_BACK_REQ:
  3469. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  3470. iwl4965_handle_data_packet(priv, 0, include_phy,
  3471. rxb, &stats);
  3472. break;
  3473. default:
  3474. break;
  3475. }
  3476. #endif
  3477. break;
  3478. case IEEE80211_FTYPE_DATA: {
  3479. DECLARE_MAC_BUF(mac1);
  3480. DECLARE_MAC_BUF(mac2);
  3481. DECLARE_MAC_BUF(mac3);
  3482. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3483. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3484. header->addr2);
  3485. if (unlikely(!network_packet))
  3486. IWL_DEBUG_DROP("Dropping (non network): "
  3487. "%s, %s, %s\n",
  3488. print_mac(mac1, header->addr1),
  3489. print_mac(mac2, header->addr2),
  3490. print_mac(mac3, header->addr3));
  3491. else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
  3492. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  3493. print_mac(mac1, header->addr1),
  3494. print_mac(mac2, header->addr2),
  3495. print_mac(mac3, header->addr3));
  3496. else
  3497. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  3498. &stats);
  3499. break;
  3500. }
  3501. default:
  3502. break;
  3503. }
  3504. }
  3505. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  3506. * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  3507. static void iwl4965_rx_reply_rx_phy(struct iwl4965_priv *priv,
  3508. struct iwl4965_rx_mem_buffer *rxb)
  3509. {
  3510. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3511. priv->last_phy_res[0] = 1;
  3512. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  3513. sizeof(struct iwl4965_rx_phy_res));
  3514. }
  3515. static void iwl4965_rx_missed_beacon_notif(struct iwl4965_priv *priv,
  3516. struct iwl4965_rx_mem_buffer *rxb)
  3517. {
  3518. #ifdef CONFIG_IWL4965_SENSITIVITY
  3519. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3520. struct iwl4965_missed_beacon_notif *missed_beacon;
  3521. missed_beacon = &pkt->u.missed_beacon;
  3522. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  3523. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  3524. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  3525. le32_to_cpu(missed_beacon->total_missed_becons),
  3526. le32_to_cpu(missed_beacon->num_recvd_beacons),
  3527. le32_to_cpu(missed_beacon->num_expected_beacons));
  3528. priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
  3529. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
  3530. queue_work(priv->workqueue, &priv->sensitivity_work);
  3531. }
  3532. #endif /*CONFIG_IWL4965_SENSITIVITY*/
  3533. }
  3534. #ifdef CONFIG_IWL4965_HT
  3535. #ifdef CONFIG_IWL4965_HT_AGG
  3536. /**
  3537. * iwl4965_set_tx_status - Update driver's record of one Tx frame's status
  3538. *
  3539. * This will get sent to mac80211.
  3540. */
  3541. static void iwl4965_set_tx_status(struct iwl4965_priv *priv, int txq_id, int idx,
  3542. u32 status, u32 retry_count, u32 rate)
  3543. {
  3544. struct ieee80211_tx_status *tx_status =
  3545. &(priv->txq[txq_id].txb[idx].status);
  3546. tx_status->flags = status ? IEEE80211_TX_STATUS_ACK : 0;
  3547. tx_status->retry_count += retry_count;
  3548. tx_status->control.tx_rate = rate;
  3549. }
  3550. #endif/* CONFIG_IWL4965_HT_AGG */
  3551. /**
  3552. * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
  3553. */
  3554. static void iwl4965_sta_modify_enable_tid_tx(struct iwl4965_priv *priv,
  3555. int sta_id, int tid)
  3556. {
  3557. unsigned long flags;
  3558. /* Remove "disable" flag, to enable Tx for this TID */
  3559. spin_lock_irqsave(&priv->sta_lock, flags);
  3560. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
  3561. priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
  3562. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3563. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3564. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3565. }
  3566. /**
  3567. * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
  3568. *
  3569. * Go through block-ack's bitmap of ACK'd frames, update driver's record of
  3570. * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
  3571. */
  3572. static int iwl4965_tx_status_reply_compressed_ba(struct iwl4965_priv *priv,
  3573. struct iwl4965_ht_agg *agg,
  3574. struct iwl4965_compressed_ba_resp*
  3575. ba_resp)
  3576. {
  3577. int i, sh, ack;
  3578. u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
  3579. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  3580. u64 bitmap;
  3581. int successes = 0;
  3582. struct ieee80211_tx_status *tx_status;
  3583. if (unlikely(!agg->wait_for_ba)) {
  3584. IWL_ERROR("Received BA when not expected\n");
  3585. return -EINVAL;
  3586. }
  3587. /* Mark that the expected block-ack response arrived */
  3588. agg->wait_for_ba = 0;
  3589. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
  3590. /* Calculate shift to align block-ack bits with our Tx window bits */
  3591. sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
  3592. if (sh < 0) /* tbw something is wrong with indices */
  3593. sh += 0x100;
  3594. /* don't use 64-bit values for now */
  3595. bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
  3596. if (agg->frame_count > (64 - sh)) {
  3597. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  3598. return -1;
  3599. }
  3600. /* check for success or failure according to the
  3601. * transmitted bitmap and block-ack bitmap */
  3602. bitmap &= agg->bitmap;
  3603. /* For each frame attempted in aggregation,
  3604. * update driver's record of tx frame's status. */
  3605. for (i = 0; i < agg->frame_count ; i++) {
  3606. ack = bitmap & (1 << i);
  3607. successes += !!ack;
  3608. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  3609. ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
  3610. agg->start_idx + i);
  3611. }
  3612. tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
  3613. tx_status->flags = IEEE80211_TX_STATUS_ACK;
  3614. tx_status->retry_count++;
  3615. #ifdef CONFIG_IWL4965_HT_AGG
  3616. tx_status->flags |= IEEE80211_TX_STATUS_AGG_STATS;
  3617. tx_status->successes = successes;
  3618. tx_status->frame_count = agg->frame_count;
  3619. #endif /* CONFIG_IWL4965_HT_AGG */
  3620. tx_status->control.tx_rate = agg->rate_n_flags;
  3621. IWL_DEBUG_TX_REPLY("Bitmap %llx\n", bitmap);
  3622. return 0;
  3623. }
  3624. /**
  3625. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  3626. */
  3627. static void iwl4965_tx_queue_stop_scheduler(struct iwl4965_priv *priv,
  3628. u16 txq_id)
  3629. {
  3630. /* Simply stop the queue, but don't change any configuration;
  3631. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  3632. iwl4965_write_prph(priv,
  3633. KDR_SCD_QUEUE_STATUS_BITS(txq_id),
  3634. (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  3635. (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  3636. }
  3637. /**
  3638. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  3639. */
  3640. static int iwl4965_tx_queue_agg_disable(struct iwl4965_priv *priv, u16 txq_id,
  3641. u16 ssn_idx, u8 tx_fifo)
  3642. {
  3643. if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
  3644. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3645. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3646. return -EINVAL;
  3647. }
  3648. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3649. iwl4965_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  3650. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  3651. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  3652. /* supposes that ssn_idx is valid (!= 0xFFF) */
  3653. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3654. iwl4965_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
  3655. iwl4965_txq_ctx_deactivate(priv, txq_id);
  3656. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  3657. return 0;
  3658. }
  3659. int iwl4965_check_empty_hw_queue(struct iwl4965_priv *priv, int sta_id,
  3660. u8 tid, int txq_id)
  3661. {
  3662. struct iwl4965_queue *q = &priv->txq[txq_id].q;
  3663. u8 *addr = priv->stations[sta_id].sta.sta.addr;
  3664. struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
  3665. switch (priv->stations[sta_id].tid[tid].agg.state) {
  3666. case IWL_EMPTYING_HW_QUEUE_DELBA:
  3667. /* We are reclaiming the last packet of the */
  3668. /* aggregated HW queue */
  3669. if (txq_id == tid_data->agg.txq_id &&
  3670. q->read_ptr == q->write_ptr) {
  3671. u16 ssn = SEQ_TO_SN(tid_data->seq_number);
  3672. int tx_fifo = default_tid_to_tx_fifo[tid];
  3673. IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
  3674. iwl4965_tx_queue_agg_disable(priv, txq_id,
  3675. ssn, tx_fifo);
  3676. tid_data->agg.state = IWL_AGG_OFF;
  3677. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  3678. }
  3679. break;
  3680. case IWL_EMPTYING_HW_QUEUE_ADDBA:
  3681. /* We are reclaiming the last packet of the queue */
  3682. if (tid_data->tfds_in_queue == 0) {
  3683. IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
  3684. tid_data->agg.state = IWL_AGG_ON;
  3685. ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  3686. }
  3687. break;
  3688. }
  3689. return 0;
  3690. }
  3691. /**
  3692. * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
  3693. * @index -- current index
  3694. * @n_bd -- total number of entries in queue (s/b power of 2)
  3695. */
  3696. static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
  3697. {
  3698. return (index == 0) ? n_bd - 1 : index - 1;
  3699. }
  3700. /**
  3701. * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
  3702. *
  3703. * Handles block-acknowledge notification from device, which reports success
  3704. * of frames sent via aggregation.
  3705. */
  3706. static void iwl4965_rx_reply_compressed_ba(struct iwl4965_priv *priv,
  3707. struct iwl4965_rx_mem_buffer *rxb)
  3708. {
  3709. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3710. struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  3711. int index;
  3712. struct iwl4965_tx_queue *txq = NULL;
  3713. struct iwl4965_ht_agg *agg;
  3714. DECLARE_MAC_BUF(mac);
  3715. /* "flow" corresponds to Tx queue */
  3716. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  3717. /* "ssn" is start of block-ack Tx window, corresponds to index
  3718. * (in Tx queue's circular buffer) of first TFD/frame in window */
  3719. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  3720. if (scd_flow >= ARRAY_SIZE(priv->txq)) {
  3721. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  3722. return;
  3723. }
  3724. txq = &priv->txq[scd_flow];
  3725. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  3726. /* Find index just before block-ack window */
  3727. index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  3728. /* TODO: Need to get this copy more safely - now good for debug */
  3729. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  3730. "sta_id = %d\n",
  3731. agg->wait_for_ba,
  3732. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  3733. ba_resp->sta_id);
  3734. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
  3735. "%d, scd_ssn = %d\n",
  3736. ba_resp->tid,
  3737. ba_resp->seq_ctl,
  3738. ba_resp->bitmap,
  3739. ba_resp->scd_flow,
  3740. ba_resp->scd_ssn);
  3741. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
  3742. agg->start_idx,
  3743. agg->bitmap);
  3744. /* Update driver's record of ACK vs. not for each frame in window */
  3745. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  3746. /* Release all TFDs before the SSN, i.e. all TFDs in front of
  3747. * block-ack window (we assume that they've been successfully
  3748. * transmitted ... if not, it's too late anyway). */
  3749. if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
  3750. int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
  3751. priv->stations[ba_resp->sta_id].
  3752. tid[ba_resp->tid].tfds_in_queue -= freed;
  3753. if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
  3754. priv->mac80211_registered &&
  3755. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
  3756. ieee80211_wake_queue(priv->hw, scd_flow);
  3757. iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
  3758. ba_resp->tid, scd_flow);
  3759. }
  3760. }
  3761. /**
  3762. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  3763. */
  3764. static int iwl4965_tx_queue_set_q2ratid(struct iwl4965_priv *priv, u16 ra_tid,
  3765. u16 txq_id)
  3766. {
  3767. u32 tbl_dw_addr;
  3768. u32 tbl_dw;
  3769. u16 scd_q2ratid;
  3770. scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  3771. tbl_dw_addr = priv->scd_base_addr +
  3772. SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  3773. tbl_dw = iwl4965_read_targ_mem(priv, tbl_dw_addr);
  3774. if (txq_id & 0x1)
  3775. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  3776. else
  3777. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  3778. iwl4965_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  3779. return 0;
  3780. }
  3781. /**
  3782. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  3783. *
  3784. * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
  3785. * i.e. it must be one of the higher queues used for aggregation
  3786. */
  3787. static int iwl4965_tx_queue_agg_enable(struct iwl4965_priv *priv, int txq_id,
  3788. int tx_fifo, int sta_id, int tid,
  3789. u16 ssn_idx)
  3790. {
  3791. unsigned long flags;
  3792. int rc;
  3793. u16 ra_tid;
  3794. if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
  3795. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3796. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3797. ra_tid = BUILD_RAxTID(sta_id, tid);
  3798. /* Modify device's station table to Tx this TID */
  3799. iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
  3800. spin_lock_irqsave(&priv->lock, flags);
  3801. rc = iwl4965_grab_nic_access(priv);
  3802. if (rc) {
  3803. spin_unlock_irqrestore(&priv->lock, flags);
  3804. return rc;
  3805. }
  3806. /* Stop this Tx queue before configuring it */
  3807. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3808. /* Map receiver-address / traffic-ID to this queue */
  3809. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  3810. /* Set this queue as a chain-building queue */
  3811. iwl4965_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  3812. /* Place first TFD at index corresponding to start sequence number.
  3813. * Assumes that ssn_idx is valid (!= 0xFFF) */
  3814. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  3815. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  3816. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3817. /* Set up Tx window size and frame limit for this queue */
  3818. iwl4965_write_targ_mem(priv,
  3819. priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  3820. (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  3821. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  3822. iwl4965_write_targ_mem(priv, priv->scd_base_addr +
  3823. SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  3824. (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  3825. & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  3826. iwl4965_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
  3827. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  3828. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  3829. iwl4965_release_nic_access(priv);
  3830. spin_unlock_irqrestore(&priv->lock, flags);
  3831. return 0;
  3832. }
  3833. #endif /* CONFIG_IWL4965_HT */
  3834. /**
  3835. * iwl4965_add_station - Initialize a station's hardware rate table
  3836. *
  3837. * The uCode's station table contains a table of fallback rates
  3838. * for automatic fallback during transmission.
  3839. *
  3840. * NOTE: This sets up a default set of values. These will be replaced later
  3841. * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
  3842. * rc80211_simple.
  3843. *
  3844. * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
  3845. * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
  3846. * which requires station table entry to exist).
  3847. */
  3848. void iwl4965_add_station(struct iwl4965_priv *priv, const u8 *addr, int is_ap)
  3849. {
  3850. int i, r;
  3851. struct iwl4965_link_quality_cmd link_cmd = {
  3852. .reserved1 = 0,
  3853. };
  3854. u16 rate_flags;
  3855. /* Set up the rate scaling to start at selected rate, fall back
  3856. * all the way down to 1M in IEEE order, and then spin on 1M */
  3857. if (is_ap)
  3858. r = IWL_RATE_54M_INDEX;
  3859. else if (priv->phymode == MODE_IEEE80211A)
  3860. r = IWL_RATE_6M_INDEX;
  3861. else
  3862. r = IWL_RATE_1M_INDEX;
  3863. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  3864. rate_flags = 0;
  3865. if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
  3866. rate_flags |= RATE_MCS_CCK_MSK;
  3867. /* Use Tx antenna B only */
  3868. rate_flags |= RATE_MCS_ANT_B_MSK;
  3869. rate_flags &= ~RATE_MCS_ANT_A_MSK;
  3870. link_cmd.rs_table[i].rate_n_flags =
  3871. iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
  3872. r = iwl4965_get_prev_ieee_rate(r);
  3873. }
  3874. link_cmd.general_params.single_stream_ant_msk = 2;
  3875. link_cmd.general_params.dual_stream_ant_msk = 3;
  3876. link_cmd.agg_params.agg_dis_start_th = 3;
  3877. link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
  3878. /* Update the rate scaling for control frame Tx to AP */
  3879. link_cmd.sta_id = is_ap ? IWL_AP_ID : IWL4965_BROADCAST_ID;
  3880. iwl4965_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd),
  3881. &link_cmd);
  3882. }
  3883. #ifdef CONFIG_IWL4965_HT
  3884. static u8 iwl4965_is_channel_extension(struct iwl4965_priv *priv, int phymode,
  3885. u16 channel, u8 extension_chan_offset)
  3886. {
  3887. const struct iwl4965_channel_info *ch_info;
  3888. ch_info = iwl4965_get_channel_info(priv, phymode, channel);
  3889. if (!is_channel_valid(ch_info))
  3890. return 0;
  3891. if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO)
  3892. return 0;
  3893. if ((ch_info->fat_extension_channel == extension_chan_offset) ||
  3894. (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
  3895. return 1;
  3896. return 0;
  3897. }
  3898. static u8 iwl4965_is_fat_tx_allowed(struct iwl4965_priv *priv,
  3899. struct ieee80211_ht_info *sta_ht_inf)
  3900. {
  3901. struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
  3902. if ((!iwl_ht_conf->is_ht) ||
  3903. (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
  3904. (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO))
  3905. return 0;
  3906. if (sta_ht_inf) {
  3907. if ((!sta_ht_inf->ht_supported) ||
  3908. (!sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH))
  3909. return 0;
  3910. }
  3911. return (iwl4965_is_channel_extension(priv, priv->phymode,
  3912. iwl_ht_conf->control_channel,
  3913. iwl_ht_conf->extension_chan_offset));
  3914. }
  3915. void iwl4965_set_rxon_ht(struct iwl4965_priv *priv, struct iwl_ht_info *ht_info)
  3916. {
  3917. struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
  3918. u32 val;
  3919. if (!ht_info->is_ht)
  3920. return;
  3921. /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
  3922. if (iwl4965_is_fat_tx_allowed(priv, NULL))
  3923. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3924. else
  3925. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
  3926. RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
  3927. if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
  3928. IWL_DEBUG_ASSOC("control diff than current %d %d\n",
  3929. le16_to_cpu(rxon->channel),
  3930. ht_info->control_channel);
  3931. rxon->channel = cpu_to_le16(ht_info->control_channel);
  3932. return;
  3933. }
  3934. /* Note: control channel is opposite of extension channel */
  3935. switch (ht_info->extension_chan_offset) {
  3936. case IWL_EXT_CHANNEL_OFFSET_ABOVE:
  3937. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3938. break;
  3939. case IWL_EXT_CHANNEL_OFFSET_BELOW:
  3940. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3941. break;
  3942. case IWL_EXT_CHANNEL_OFFSET_AUTO:
  3943. rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3944. break;
  3945. default:
  3946. rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3947. break;
  3948. }
  3949. val = ht_info->ht_protection;
  3950. rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
  3951. iwl4965_set_rxon_chain(priv);
  3952. IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
  3953. "rxon flags 0x%X operation mode :0x%X "
  3954. "extension channel offset 0x%x "
  3955. "control chan %d\n",
  3956. ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
  3957. le32_to_cpu(rxon->flags), ht_info->ht_protection,
  3958. ht_info->extension_chan_offset,
  3959. ht_info->control_channel);
  3960. return;
  3961. }
  3962. void iwl4965_set_ht_add_station(struct iwl4965_priv *priv, u8 index,
  3963. struct ieee80211_ht_info *sta_ht_inf)
  3964. {
  3965. __le32 sta_flags;
  3966. u8 mimo_ps_mode;
  3967. if (!sta_ht_inf || !sta_ht_inf->ht_supported)
  3968. goto done;
  3969. mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
  3970. sta_flags = priv->stations[index].sta.station_flags;
  3971. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  3972. switch (mimo_ps_mode) {
  3973. case WLAN_HT_CAP_MIMO_PS_STATIC:
  3974. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  3975. break;
  3976. case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
  3977. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  3978. break;
  3979. case WLAN_HT_CAP_MIMO_PS_DISABLED:
  3980. break;
  3981. default:
  3982. IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
  3983. break;
  3984. }
  3985. sta_flags |= cpu_to_le32(
  3986. (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  3987. sta_flags |= cpu_to_le32(
  3988. (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  3989. if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
  3990. sta_flags |= STA_FLG_FAT_EN_MSK;
  3991. else
  3992. sta_flags &= ~STA_FLG_FAT_EN_MSK;
  3993. priv->stations[index].sta.station_flags = sta_flags;
  3994. done:
  3995. return;
  3996. }
  3997. static void iwl4965_sta_modify_add_ba_tid(struct iwl4965_priv *priv,
  3998. int sta_id, int tid, u16 ssn)
  3999. {
  4000. unsigned long flags;
  4001. spin_lock_irqsave(&priv->sta_lock, flags);
  4002. priv->stations[sta_id].sta.station_flags_msk = 0;
  4003. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  4004. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  4005. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  4006. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  4007. spin_unlock_irqrestore(&priv->sta_lock, flags);
  4008. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  4009. }
  4010. static void iwl4965_sta_modify_del_ba_tid(struct iwl4965_priv *priv,
  4011. int sta_id, int tid)
  4012. {
  4013. unsigned long flags;
  4014. spin_lock_irqsave(&priv->sta_lock, flags);
  4015. priv->stations[sta_id].sta.station_flags_msk = 0;
  4016. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  4017. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  4018. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  4019. spin_unlock_irqrestore(&priv->sta_lock, flags);
  4020. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  4021. }
  4022. /*
  4023. * Find first available (lowest unused) Tx Queue, mark it "active".
  4024. * Called only when finding queue for aggregation.
  4025. * Should never return anything < 7, because they should already
  4026. * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
  4027. */
  4028. static int iwl4965_txq_ctx_activate_free(struct iwl4965_priv *priv)
  4029. {
  4030. int txq_id;
  4031. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  4032. if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
  4033. return txq_id;
  4034. return -1;
  4035. }
  4036. static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
  4037. u16 tid, u16 *start_seq_num)
  4038. {
  4039. struct iwl4965_priv *priv = hw->priv;
  4040. int sta_id;
  4041. int tx_fifo;
  4042. int txq_id;
  4043. int ssn = -1;
  4044. int rc = 0;
  4045. unsigned long flags;
  4046. struct iwl4965_tid_data *tid_data;
  4047. DECLARE_MAC_BUF(mac);
  4048. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  4049. tx_fifo = default_tid_to_tx_fifo[tid];
  4050. else
  4051. return -EINVAL;
  4052. IWL_WARNING("%s on da = %s tid = %d\n",
  4053. __func__, print_mac(mac, da), tid);
  4054. sta_id = iwl4965_hw_find_station(priv, da);
  4055. if (sta_id == IWL_INVALID_STATION)
  4056. return -ENXIO;
  4057. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
  4058. IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
  4059. return -ENXIO;
  4060. }
  4061. txq_id = iwl4965_txq_ctx_activate_free(priv);
  4062. if (txq_id == -1)
  4063. return -ENXIO;
  4064. spin_lock_irqsave(&priv->sta_lock, flags);
  4065. tid_data = &priv->stations[sta_id].tid[tid];
  4066. ssn = SEQ_TO_SN(tid_data->seq_number);
  4067. tid_data->agg.txq_id = txq_id;
  4068. spin_unlock_irqrestore(&priv->sta_lock, flags);
  4069. *start_seq_num = ssn;
  4070. rc = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
  4071. sta_id, tid, ssn);
  4072. if (rc)
  4073. return rc;
  4074. rc = 0;
  4075. if (tid_data->tfds_in_queue == 0) {
  4076. printk(KERN_ERR "HW queue is empty\n");
  4077. tid_data->agg.state = IWL_AGG_ON;
  4078. ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
  4079. } else {
  4080. IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
  4081. tid_data->tfds_in_queue);
  4082. tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
  4083. }
  4084. return rc;
  4085. }
  4086. static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
  4087. u16 tid)
  4088. {
  4089. struct iwl4965_priv *priv = hw->priv;
  4090. int tx_fifo_id, txq_id, sta_id, ssn = -1;
  4091. struct iwl4965_tid_data *tid_data;
  4092. int rc, write_ptr, read_ptr;
  4093. unsigned long flags;
  4094. DECLARE_MAC_BUF(mac);
  4095. if (!da) {
  4096. IWL_ERROR("da = NULL\n");
  4097. return -EINVAL;
  4098. }
  4099. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  4100. tx_fifo_id = default_tid_to_tx_fifo[tid];
  4101. else
  4102. return -EINVAL;
  4103. sta_id = iwl4965_hw_find_station(priv, da);
  4104. if (sta_id == IWL_INVALID_STATION)
  4105. return -ENXIO;
  4106. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
  4107. IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
  4108. tid_data = &priv->stations[sta_id].tid[tid];
  4109. ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
  4110. txq_id = tid_data->agg.txq_id;
  4111. write_ptr = priv->txq[txq_id].q.write_ptr;
  4112. read_ptr = priv->txq[txq_id].q.read_ptr;
  4113. /* The queue is not empty */
  4114. if (write_ptr != read_ptr) {
  4115. IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
  4116. priv->stations[sta_id].tid[tid].agg.state =
  4117. IWL_EMPTYING_HW_QUEUE_DELBA;
  4118. return 0;
  4119. }
  4120. IWL_DEBUG_HT("HW queue empty\n");;
  4121. priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
  4122. spin_lock_irqsave(&priv->lock, flags);
  4123. rc = iwl4965_grab_nic_access(priv);
  4124. if (rc) {
  4125. spin_unlock_irqrestore(&priv->lock, flags);
  4126. return rc;
  4127. }
  4128. rc = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
  4129. iwl4965_release_nic_access(priv);
  4130. spin_unlock_irqrestore(&priv->lock, flags);
  4131. if (rc)
  4132. return rc;
  4133. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
  4134. IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
  4135. print_mac(mac, da), tid);
  4136. return 0;
  4137. }
  4138. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  4139. enum ieee80211_ampdu_mlme_action action,
  4140. const u8 *addr, u16 tid, u16 *ssn)
  4141. {
  4142. struct iwl4965_priv *priv = hw->priv;
  4143. int sta_id;
  4144. DECLARE_MAC_BUF(mac);
  4145. IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
  4146. print_mac(mac, addr), tid);
  4147. sta_id = iwl4965_hw_find_station(priv, addr);
  4148. switch (action) {
  4149. case IEEE80211_AMPDU_RX_START:
  4150. IWL_DEBUG_HT("start Rx\n");
  4151. iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
  4152. break;
  4153. case IEEE80211_AMPDU_RX_STOP:
  4154. IWL_DEBUG_HT("stop Rx\n");
  4155. iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
  4156. break;
  4157. case IEEE80211_AMPDU_TX_START:
  4158. IWL_DEBUG_HT("start Tx\n");
  4159. return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
  4160. case IEEE80211_AMPDU_TX_STOP:
  4161. IWL_DEBUG_HT("stop Tx\n");
  4162. return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
  4163. default:
  4164. IWL_DEBUG_HT("unknown\n");
  4165. return -EINVAL;
  4166. break;
  4167. }
  4168. return 0;
  4169. }
  4170. #endif /* CONFIG_IWL4965_HT */
  4171. /* Set up 4965-specific Rx frame reply handlers */
  4172. void iwl4965_hw_rx_handler_setup(struct iwl4965_priv *priv)
  4173. {
  4174. /* Legacy Rx frames */
  4175. priv->rx_handlers[REPLY_4965_RX] = iwl4965_rx_reply_rx;
  4176. /* High-throughput (HT) Rx frames */
  4177. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
  4178. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
  4179. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  4180. iwl4965_rx_missed_beacon_notif;
  4181. #ifdef CONFIG_IWL4965_HT
  4182. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  4183. #endif /* CONFIG_IWL4965_HT */
  4184. }
  4185. void iwl4965_hw_setup_deferred_work(struct iwl4965_priv *priv)
  4186. {
  4187. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  4188. INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
  4189. #ifdef CONFIG_IWL4965_SENSITIVITY
  4190. INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
  4191. #endif
  4192. #ifdef CONFIG_IWL4965_HT
  4193. #ifdef CONFIG_IWL4965_HT_AGG
  4194. INIT_WORK(&priv->agg_work, iwl4965_bg_agg_work);
  4195. #endif /* CONFIG_IWL4965_HT_AGG */
  4196. #endif /* CONFIG_IWL4965_HT */
  4197. init_timer(&priv->statistics_periodic);
  4198. priv->statistics_periodic.data = (unsigned long)priv;
  4199. priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
  4200. }
  4201. void iwl4965_hw_cancel_deferred_work(struct iwl4965_priv *priv)
  4202. {
  4203. del_timer_sync(&priv->statistics_periodic);
  4204. cancel_delayed_work(&priv->init_alive_start);
  4205. }
  4206. struct pci_device_id iwl4965_hw_card_ids[] = {
  4207. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4229)},
  4208. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4230)},
  4209. {0}
  4210. };
  4211. /*
  4212. * The device's EEPROM semaphore prevents conflicts between driver and uCode
  4213. * when accessing the EEPROM; each access is a series of pulses to/from the
  4214. * EEPROM chip, not a single event, so even reads could conflict if they
  4215. * weren't arbitrated by the semaphore.
  4216. */
  4217. int iwl4965_eeprom_acquire_semaphore(struct iwl4965_priv *priv)
  4218. {
  4219. u16 count;
  4220. int rc;
  4221. for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
  4222. /* Request semaphore */
  4223. iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  4224. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
  4225. /* See if we got it */
  4226. rc = iwl4965_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  4227. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
  4228. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
  4229. EEPROM_SEM_TIMEOUT);
  4230. if (rc >= 0) {
  4231. IWL_DEBUG_IO("Acquired semaphore after %d tries.\n",
  4232. count+1);
  4233. return rc;
  4234. }
  4235. }
  4236. return rc;
  4237. }
  4238. MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);