cnic.c 123 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x/bnx2x_reg.h"
  40. #include "bnx2x/bnx2x_fw_defs.h"
  41. #include "bnx2x/bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. static LIST_HEAD(cnic_dev_list);
  55. static DEFINE_RWLOCK(cnic_dev_lock);
  56. static DEFINE_MUTEX(cnic_lock);
  57. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  58. static int cnic_service_bnx2(void *, void *);
  59. static int cnic_service_bnx2x(void *, void *);
  60. static int cnic_ctl(void *, struct cnic_ctl_info *);
  61. static struct cnic_ops cnic_bnx2_ops = {
  62. .cnic_owner = THIS_MODULE,
  63. .cnic_handler = cnic_service_bnx2,
  64. .cnic_ctl = cnic_ctl,
  65. };
  66. static struct cnic_ops cnic_bnx2x_ops = {
  67. .cnic_owner = THIS_MODULE,
  68. .cnic_handler = cnic_service_bnx2x,
  69. .cnic_ctl = cnic_ctl,
  70. };
  71. static struct workqueue_struct *cnic_wq;
  72. static void cnic_shutdown_rings(struct cnic_dev *);
  73. static void cnic_init_rings(struct cnic_dev *);
  74. static int cnic_cm_set_pg(struct cnic_sock *);
  75. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  76. {
  77. struct cnic_dev *dev = uinfo->priv;
  78. struct cnic_local *cp = dev->cnic_priv;
  79. if (!capable(CAP_NET_ADMIN))
  80. return -EPERM;
  81. if (cp->uio_dev != -1)
  82. return -EBUSY;
  83. rtnl_lock();
  84. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  85. rtnl_unlock();
  86. return -ENODEV;
  87. }
  88. cp->uio_dev = iminor(inode);
  89. cnic_init_rings(dev);
  90. rtnl_unlock();
  91. return 0;
  92. }
  93. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  94. {
  95. struct cnic_dev *dev = uinfo->priv;
  96. struct cnic_local *cp = dev->cnic_priv;
  97. cnic_shutdown_rings(dev);
  98. cp->uio_dev = -1;
  99. return 0;
  100. }
  101. static inline void cnic_hold(struct cnic_dev *dev)
  102. {
  103. atomic_inc(&dev->ref_count);
  104. }
  105. static inline void cnic_put(struct cnic_dev *dev)
  106. {
  107. atomic_dec(&dev->ref_count);
  108. }
  109. static inline void csk_hold(struct cnic_sock *csk)
  110. {
  111. atomic_inc(&csk->ref_count);
  112. }
  113. static inline void csk_put(struct cnic_sock *csk)
  114. {
  115. atomic_dec(&csk->ref_count);
  116. }
  117. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  118. {
  119. struct cnic_dev *cdev;
  120. read_lock(&cnic_dev_lock);
  121. list_for_each_entry(cdev, &cnic_dev_list, list) {
  122. if (netdev == cdev->netdev) {
  123. cnic_hold(cdev);
  124. read_unlock(&cnic_dev_lock);
  125. return cdev;
  126. }
  127. }
  128. read_unlock(&cnic_dev_lock);
  129. return NULL;
  130. }
  131. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  132. {
  133. atomic_inc(&ulp_ops->ref_count);
  134. }
  135. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  136. {
  137. atomic_dec(&ulp_ops->ref_count);
  138. }
  139. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  140. {
  141. struct cnic_local *cp = dev->cnic_priv;
  142. struct cnic_eth_dev *ethdev = cp->ethdev;
  143. struct drv_ctl_info info;
  144. struct drv_ctl_io *io = &info.data.io;
  145. info.cmd = DRV_CTL_CTX_WR_CMD;
  146. io->cid_addr = cid_addr;
  147. io->offset = off;
  148. io->data = val;
  149. ethdev->drv_ctl(dev->netdev, &info);
  150. }
  151. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  152. {
  153. struct cnic_local *cp = dev->cnic_priv;
  154. struct cnic_eth_dev *ethdev = cp->ethdev;
  155. struct drv_ctl_info info;
  156. struct drv_ctl_io *io = &info.data.io;
  157. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  158. io->offset = off;
  159. io->dma_addr = addr;
  160. ethdev->drv_ctl(dev->netdev, &info);
  161. }
  162. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  163. {
  164. struct cnic_local *cp = dev->cnic_priv;
  165. struct cnic_eth_dev *ethdev = cp->ethdev;
  166. struct drv_ctl_info info;
  167. struct drv_ctl_l2_ring *ring = &info.data.ring;
  168. if (start)
  169. info.cmd = DRV_CTL_START_L2_CMD;
  170. else
  171. info.cmd = DRV_CTL_STOP_L2_CMD;
  172. ring->cid = cid;
  173. ring->client_id = cl_id;
  174. ethdev->drv_ctl(dev->netdev, &info);
  175. }
  176. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  177. {
  178. struct cnic_local *cp = dev->cnic_priv;
  179. struct cnic_eth_dev *ethdev = cp->ethdev;
  180. struct drv_ctl_info info;
  181. struct drv_ctl_io *io = &info.data.io;
  182. info.cmd = DRV_CTL_IO_WR_CMD;
  183. io->offset = off;
  184. io->data = val;
  185. ethdev->drv_ctl(dev->netdev, &info);
  186. }
  187. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  188. {
  189. struct cnic_local *cp = dev->cnic_priv;
  190. struct cnic_eth_dev *ethdev = cp->ethdev;
  191. struct drv_ctl_info info;
  192. struct drv_ctl_io *io = &info.data.io;
  193. info.cmd = DRV_CTL_IO_RD_CMD;
  194. io->offset = off;
  195. ethdev->drv_ctl(dev->netdev, &info);
  196. return io->data;
  197. }
  198. static int cnic_in_use(struct cnic_sock *csk)
  199. {
  200. return test_bit(SK_F_INUSE, &csk->flags);
  201. }
  202. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  203. {
  204. struct cnic_local *cp = dev->cnic_priv;
  205. struct cnic_eth_dev *ethdev = cp->ethdev;
  206. struct drv_ctl_info info;
  207. info.cmd = cmd;
  208. info.data.credit.credit_count = count;
  209. ethdev->drv_ctl(dev->netdev, &info);
  210. }
  211. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  212. {
  213. u32 i;
  214. for (i = 0; i < cp->max_cid_space; i++) {
  215. if (cp->ctx_tbl[i].cid == cid) {
  216. *l5_cid = i;
  217. return 0;
  218. }
  219. }
  220. return -EINVAL;
  221. }
  222. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  223. struct cnic_sock *csk)
  224. {
  225. struct iscsi_path path_req;
  226. char *buf = NULL;
  227. u16 len = 0;
  228. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  229. struct cnic_ulp_ops *ulp_ops;
  230. if (cp->uio_dev == -1)
  231. return -ENODEV;
  232. if (csk) {
  233. len = sizeof(path_req);
  234. buf = (char *) &path_req;
  235. memset(&path_req, 0, len);
  236. msg_type = ISCSI_KEVENT_PATH_REQ;
  237. path_req.handle = (u64) csk->l5_cid;
  238. if (test_bit(SK_F_IPV6, &csk->flags)) {
  239. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  240. sizeof(struct in6_addr));
  241. path_req.ip_addr_len = 16;
  242. } else {
  243. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  244. sizeof(struct in_addr));
  245. path_req.ip_addr_len = 4;
  246. }
  247. path_req.vlan_id = csk->vlan_id;
  248. path_req.pmtu = csk->mtu;
  249. }
  250. rcu_read_lock();
  251. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  252. if (ulp_ops)
  253. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  254. rcu_read_unlock();
  255. return 0;
  256. }
  257. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  258. char *buf, u16 len)
  259. {
  260. int rc = -EINVAL;
  261. switch (msg_type) {
  262. case ISCSI_UEVENT_PATH_UPDATE: {
  263. struct cnic_local *cp;
  264. u32 l5_cid;
  265. struct cnic_sock *csk;
  266. struct iscsi_path *path_resp;
  267. if (len < sizeof(*path_resp))
  268. break;
  269. path_resp = (struct iscsi_path *) buf;
  270. cp = dev->cnic_priv;
  271. l5_cid = (u32) path_resp->handle;
  272. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  273. break;
  274. rcu_read_lock();
  275. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  276. rc = -ENODEV;
  277. rcu_read_unlock();
  278. break;
  279. }
  280. csk = &cp->csk_tbl[l5_cid];
  281. csk_hold(csk);
  282. if (cnic_in_use(csk)) {
  283. memcpy(csk->ha, path_resp->mac_addr, 6);
  284. if (test_bit(SK_F_IPV6, &csk->flags))
  285. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  286. sizeof(struct in6_addr));
  287. else
  288. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  289. sizeof(struct in_addr));
  290. if (is_valid_ether_addr(csk->ha))
  291. cnic_cm_set_pg(csk);
  292. }
  293. csk_put(csk);
  294. rcu_read_unlock();
  295. rc = 0;
  296. }
  297. }
  298. return rc;
  299. }
  300. static int cnic_offld_prep(struct cnic_sock *csk)
  301. {
  302. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  303. return 0;
  304. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  305. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  306. return 0;
  307. }
  308. return 1;
  309. }
  310. static int cnic_close_prep(struct cnic_sock *csk)
  311. {
  312. clear_bit(SK_F_CONNECT_START, &csk->flags);
  313. smp_mb__after_clear_bit();
  314. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  315. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  316. msleep(1);
  317. return 1;
  318. }
  319. return 0;
  320. }
  321. static int cnic_abort_prep(struct cnic_sock *csk)
  322. {
  323. clear_bit(SK_F_CONNECT_START, &csk->flags);
  324. smp_mb__after_clear_bit();
  325. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  326. msleep(1);
  327. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  328. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  329. return 1;
  330. }
  331. return 0;
  332. }
  333. static void cnic_uio_stop(void)
  334. {
  335. struct cnic_dev *dev;
  336. read_lock(&cnic_dev_lock);
  337. list_for_each_entry(dev, &cnic_dev_list, list) {
  338. struct cnic_local *cp = dev->cnic_priv;
  339. if (cp->cnic_uinfo)
  340. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  341. }
  342. read_unlock(&cnic_dev_lock);
  343. }
  344. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  345. {
  346. struct cnic_dev *dev;
  347. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  348. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  349. return -EINVAL;
  350. }
  351. mutex_lock(&cnic_lock);
  352. if (cnic_ulp_tbl[ulp_type]) {
  353. pr_err("%s: Type %d has already been registered\n",
  354. __func__, ulp_type);
  355. mutex_unlock(&cnic_lock);
  356. return -EBUSY;
  357. }
  358. read_lock(&cnic_dev_lock);
  359. list_for_each_entry(dev, &cnic_dev_list, list) {
  360. struct cnic_local *cp = dev->cnic_priv;
  361. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  362. }
  363. read_unlock(&cnic_dev_lock);
  364. atomic_set(&ulp_ops->ref_count, 0);
  365. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  366. mutex_unlock(&cnic_lock);
  367. /* Prevent race conditions with netdev_event */
  368. rtnl_lock();
  369. read_lock(&cnic_dev_lock);
  370. list_for_each_entry(dev, &cnic_dev_list, list) {
  371. struct cnic_local *cp = dev->cnic_priv;
  372. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  373. ulp_ops->cnic_init(dev);
  374. }
  375. read_unlock(&cnic_dev_lock);
  376. rtnl_unlock();
  377. return 0;
  378. }
  379. int cnic_unregister_driver(int ulp_type)
  380. {
  381. struct cnic_dev *dev;
  382. struct cnic_ulp_ops *ulp_ops;
  383. int i = 0;
  384. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  385. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  386. return -EINVAL;
  387. }
  388. mutex_lock(&cnic_lock);
  389. ulp_ops = cnic_ulp_tbl[ulp_type];
  390. if (!ulp_ops) {
  391. pr_err("%s: Type %d has not been registered\n",
  392. __func__, ulp_type);
  393. goto out_unlock;
  394. }
  395. read_lock(&cnic_dev_lock);
  396. list_for_each_entry(dev, &cnic_dev_list, list) {
  397. struct cnic_local *cp = dev->cnic_priv;
  398. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  399. pr_err("%s: Type %d still has devices registered\n",
  400. __func__, ulp_type);
  401. read_unlock(&cnic_dev_lock);
  402. goto out_unlock;
  403. }
  404. }
  405. read_unlock(&cnic_dev_lock);
  406. if (ulp_type == CNIC_ULP_ISCSI)
  407. cnic_uio_stop();
  408. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  409. mutex_unlock(&cnic_lock);
  410. synchronize_rcu();
  411. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  412. msleep(100);
  413. i++;
  414. }
  415. if (atomic_read(&ulp_ops->ref_count) != 0)
  416. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  417. return 0;
  418. out_unlock:
  419. mutex_unlock(&cnic_lock);
  420. return -EINVAL;
  421. }
  422. static int cnic_start_hw(struct cnic_dev *);
  423. static void cnic_stop_hw(struct cnic_dev *);
  424. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  425. void *ulp_ctx)
  426. {
  427. struct cnic_local *cp = dev->cnic_priv;
  428. struct cnic_ulp_ops *ulp_ops;
  429. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  430. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  431. return -EINVAL;
  432. }
  433. mutex_lock(&cnic_lock);
  434. if (cnic_ulp_tbl[ulp_type] == NULL) {
  435. pr_err("%s: Driver with type %d has not been registered\n",
  436. __func__, ulp_type);
  437. mutex_unlock(&cnic_lock);
  438. return -EAGAIN;
  439. }
  440. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  441. pr_err("%s: Type %d has already been registered to this device\n",
  442. __func__, ulp_type);
  443. mutex_unlock(&cnic_lock);
  444. return -EBUSY;
  445. }
  446. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  447. cp->ulp_handle[ulp_type] = ulp_ctx;
  448. ulp_ops = cnic_ulp_tbl[ulp_type];
  449. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  450. cnic_hold(dev);
  451. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  452. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  453. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  454. mutex_unlock(&cnic_lock);
  455. return 0;
  456. }
  457. EXPORT_SYMBOL(cnic_register_driver);
  458. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  459. {
  460. struct cnic_local *cp = dev->cnic_priv;
  461. int i = 0;
  462. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  463. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  464. return -EINVAL;
  465. }
  466. mutex_lock(&cnic_lock);
  467. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  468. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  469. cnic_put(dev);
  470. } else {
  471. pr_err("%s: device not registered to this ulp type %d\n",
  472. __func__, ulp_type);
  473. mutex_unlock(&cnic_lock);
  474. return -EINVAL;
  475. }
  476. mutex_unlock(&cnic_lock);
  477. synchronize_rcu();
  478. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  479. i < 20) {
  480. msleep(100);
  481. i++;
  482. }
  483. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  484. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  485. return 0;
  486. }
  487. EXPORT_SYMBOL(cnic_unregister_driver);
  488. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  489. {
  490. id_tbl->start = start_id;
  491. id_tbl->max = size;
  492. id_tbl->next = 0;
  493. spin_lock_init(&id_tbl->lock);
  494. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  495. if (!id_tbl->table)
  496. return -ENOMEM;
  497. return 0;
  498. }
  499. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  500. {
  501. kfree(id_tbl->table);
  502. id_tbl->table = NULL;
  503. }
  504. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  505. {
  506. int ret = -1;
  507. id -= id_tbl->start;
  508. if (id >= id_tbl->max)
  509. return ret;
  510. spin_lock(&id_tbl->lock);
  511. if (!test_bit(id, id_tbl->table)) {
  512. set_bit(id, id_tbl->table);
  513. ret = 0;
  514. }
  515. spin_unlock(&id_tbl->lock);
  516. return ret;
  517. }
  518. /* Returns -1 if not successful */
  519. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  520. {
  521. u32 id;
  522. spin_lock(&id_tbl->lock);
  523. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  524. if (id >= id_tbl->max) {
  525. id = -1;
  526. if (id_tbl->next != 0) {
  527. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  528. if (id >= id_tbl->next)
  529. id = -1;
  530. }
  531. }
  532. if (id < id_tbl->max) {
  533. set_bit(id, id_tbl->table);
  534. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  535. id += id_tbl->start;
  536. }
  537. spin_unlock(&id_tbl->lock);
  538. return id;
  539. }
  540. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  541. {
  542. if (id == -1)
  543. return;
  544. id -= id_tbl->start;
  545. if (id >= id_tbl->max)
  546. return;
  547. clear_bit(id, id_tbl->table);
  548. }
  549. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  550. {
  551. int i;
  552. if (!dma->pg_arr)
  553. return;
  554. for (i = 0; i < dma->num_pages; i++) {
  555. if (dma->pg_arr[i]) {
  556. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  557. dma->pg_arr[i], dma->pg_map_arr[i]);
  558. dma->pg_arr[i] = NULL;
  559. }
  560. }
  561. if (dma->pgtbl) {
  562. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  563. dma->pgtbl, dma->pgtbl_map);
  564. dma->pgtbl = NULL;
  565. }
  566. kfree(dma->pg_arr);
  567. dma->pg_arr = NULL;
  568. dma->num_pages = 0;
  569. }
  570. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  571. {
  572. int i;
  573. u32 *page_table = dma->pgtbl;
  574. for (i = 0; i < dma->num_pages; i++) {
  575. /* Each entry needs to be in big endian format. */
  576. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  577. page_table++;
  578. *page_table = (u32) dma->pg_map_arr[i];
  579. page_table++;
  580. }
  581. }
  582. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  583. {
  584. int i;
  585. u32 *page_table = dma->pgtbl;
  586. for (i = 0; i < dma->num_pages; i++) {
  587. /* Each entry needs to be in little endian format. */
  588. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  589. page_table++;
  590. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  591. page_table++;
  592. }
  593. }
  594. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  595. int pages, int use_pg_tbl)
  596. {
  597. int i, size;
  598. struct cnic_local *cp = dev->cnic_priv;
  599. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  600. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  601. if (dma->pg_arr == NULL)
  602. return -ENOMEM;
  603. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  604. dma->num_pages = pages;
  605. for (i = 0; i < pages; i++) {
  606. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  607. BCM_PAGE_SIZE,
  608. &dma->pg_map_arr[i],
  609. GFP_ATOMIC);
  610. if (dma->pg_arr[i] == NULL)
  611. goto error;
  612. }
  613. if (!use_pg_tbl)
  614. return 0;
  615. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  616. ~(BCM_PAGE_SIZE - 1);
  617. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  618. &dma->pgtbl_map, GFP_ATOMIC);
  619. if (dma->pgtbl == NULL)
  620. goto error;
  621. cp->setup_pgtbl(dev, dma);
  622. return 0;
  623. error:
  624. cnic_free_dma(dev, dma);
  625. return -ENOMEM;
  626. }
  627. static void cnic_free_context(struct cnic_dev *dev)
  628. {
  629. struct cnic_local *cp = dev->cnic_priv;
  630. int i;
  631. for (i = 0; i < cp->ctx_blks; i++) {
  632. if (cp->ctx_arr[i].ctx) {
  633. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  634. cp->ctx_arr[i].ctx,
  635. cp->ctx_arr[i].mapping);
  636. cp->ctx_arr[i].ctx = NULL;
  637. }
  638. }
  639. }
  640. static void cnic_free_resc(struct cnic_dev *dev)
  641. {
  642. struct cnic_local *cp = dev->cnic_priv;
  643. int i = 0;
  644. if (cp->cnic_uinfo) {
  645. while (cp->uio_dev != -1 && i < 15) {
  646. msleep(100);
  647. i++;
  648. }
  649. uio_unregister_device(cp->cnic_uinfo);
  650. kfree(cp->cnic_uinfo);
  651. cp->cnic_uinfo = NULL;
  652. }
  653. if (cp->l2_buf) {
  654. dma_free_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  655. cp->l2_buf, cp->l2_buf_map);
  656. cp->l2_buf = NULL;
  657. }
  658. if (cp->l2_ring) {
  659. dma_free_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  660. cp->l2_ring, cp->l2_ring_map);
  661. cp->l2_ring = NULL;
  662. }
  663. cnic_free_context(dev);
  664. kfree(cp->ctx_arr);
  665. cp->ctx_arr = NULL;
  666. cp->ctx_blks = 0;
  667. cnic_free_dma(dev, &cp->gbl_buf_info);
  668. cnic_free_dma(dev, &cp->conn_buf_info);
  669. cnic_free_dma(dev, &cp->kwq_info);
  670. cnic_free_dma(dev, &cp->kwq_16_data_info);
  671. cnic_free_dma(dev, &cp->kcq1.dma);
  672. kfree(cp->iscsi_tbl);
  673. cp->iscsi_tbl = NULL;
  674. kfree(cp->ctx_tbl);
  675. cp->ctx_tbl = NULL;
  676. cnic_free_id_tbl(&cp->cid_tbl);
  677. }
  678. static int cnic_alloc_context(struct cnic_dev *dev)
  679. {
  680. struct cnic_local *cp = dev->cnic_priv;
  681. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  682. int i, k, arr_size;
  683. cp->ctx_blk_size = BCM_PAGE_SIZE;
  684. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  685. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  686. sizeof(struct cnic_ctx);
  687. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  688. if (cp->ctx_arr == NULL)
  689. return -ENOMEM;
  690. k = 0;
  691. for (i = 0; i < 2; i++) {
  692. u32 j, reg, off, lo, hi;
  693. if (i == 0)
  694. off = BNX2_PG_CTX_MAP;
  695. else
  696. off = BNX2_ISCSI_CTX_MAP;
  697. reg = cnic_reg_rd_ind(dev, off);
  698. lo = reg >> 16;
  699. hi = reg & 0xffff;
  700. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  701. cp->ctx_arr[k].cid = j;
  702. }
  703. cp->ctx_blks = k;
  704. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  705. cp->ctx_blks = 0;
  706. return -ENOMEM;
  707. }
  708. for (i = 0; i < cp->ctx_blks; i++) {
  709. cp->ctx_arr[i].ctx =
  710. dma_alloc_coherent(&dev->pcidev->dev,
  711. BCM_PAGE_SIZE,
  712. &cp->ctx_arr[i].mapping,
  713. GFP_KERNEL);
  714. if (cp->ctx_arr[i].ctx == NULL)
  715. return -ENOMEM;
  716. }
  717. }
  718. return 0;
  719. }
  720. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  721. {
  722. int err, i, is_bnx2 = 0;
  723. struct kcqe **kcq;
  724. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  725. is_bnx2 = 1;
  726. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  727. if (err)
  728. return err;
  729. kcq = (struct kcqe **) info->dma.pg_arr;
  730. info->kcq = kcq;
  731. if (is_bnx2)
  732. return 0;
  733. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  734. struct bnx2x_bd_chain_next *next =
  735. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  736. int j = i + 1;
  737. if (j >= KCQ_PAGE_CNT)
  738. j = 0;
  739. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  740. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  741. }
  742. return 0;
  743. }
  744. static int cnic_alloc_l2_rings(struct cnic_dev *dev, int pages)
  745. {
  746. struct cnic_local *cp = dev->cnic_priv;
  747. cp->l2_ring_size = pages * BCM_PAGE_SIZE;
  748. cp->l2_ring = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  749. &cp->l2_ring_map,
  750. GFP_KERNEL | __GFP_COMP);
  751. if (!cp->l2_ring)
  752. return -ENOMEM;
  753. cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  754. cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
  755. cp->l2_buf = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  756. &cp->l2_buf_map,
  757. GFP_KERNEL | __GFP_COMP);
  758. if (!cp->l2_buf)
  759. return -ENOMEM;
  760. return 0;
  761. }
  762. static int cnic_alloc_uio(struct cnic_dev *dev) {
  763. struct cnic_local *cp = dev->cnic_priv;
  764. struct uio_info *uinfo;
  765. int ret;
  766. uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
  767. if (!uinfo)
  768. return -ENOMEM;
  769. uinfo->mem[0].addr = dev->netdev->base_addr;
  770. uinfo->mem[0].internal_addr = dev->regview;
  771. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  772. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  773. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  774. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  775. PAGE_MASK;
  776. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  777. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  778. else
  779. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  780. uinfo->name = "bnx2_cnic";
  781. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  782. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  783. PAGE_MASK;
  784. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  785. uinfo->name = "bnx2x_cnic";
  786. }
  787. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  788. uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
  789. uinfo->mem[2].size = cp->l2_ring_size;
  790. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  791. uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
  792. uinfo->mem[3].size = cp->l2_buf_size;
  793. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  794. uinfo->version = CNIC_MODULE_VERSION;
  795. uinfo->irq = UIO_IRQ_CUSTOM;
  796. uinfo->open = cnic_uio_open;
  797. uinfo->release = cnic_uio_close;
  798. uinfo->priv = dev;
  799. ret = uio_register_device(&dev->pcidev->dev, uinfo);
  800. if (ret) {
  801. kfree(uinfo);
  802. return ret;
  803. }
  804. cp->cnic_uinfo = uinfo;
  805. return 0;
  806. }
  807. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  808. {
  809. struct cnic_local *cp = dev->cnic_priv;
  810. int ret;
  811. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  812. if (ret)
  813. goto error;
  814. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  815. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  816. if (ret)
  817. goto error;
  818. ret = cnic_alloc_context(dev);
  819. if (ret)
  820. goto error;
  821. ret = cnic_alloc_l2_rings(dev, 2);
  822. if (ret)
  823. goto error;
  824. ret = cnic_alloc_uio(dev);
  825. if (ret)
  826. goto error;
  827. return 0;
  828. error:
  829. cnic_free_resc(dev);
  830. return ret;
  831. }
  832. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  833. {
  834. struct cnic_local *cp = dev->cnic_priv;
  835. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  836. int total_mem, blks, i;
  837. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  838. blks = total_mem / ctx_blk_size;
  839. if (total_mem % ctx_blk_size)
  840. blks++;
  841. if (blks > cp->ethdev->ctx_tbl_len)
  842. return -ENOMEM;
  843. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  844. if (cp->ctx_arr == NULL)
  845. return -ENOMEM;
  846. cp->ctx_blks = blks;
  847. cp->ctx_blk_size = ctx_blk_size;
  848. if (BNX2X_CHIP_IS_E1H(cp->chip_id))
  849. cp->ctx_align = 0;
  850. else
  851. cp->ctx_align = ctx_blk_size;
  852. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  853. for (i = 0; i < blks; i++) {
  854. cp->ctx_arr[i].ctx =
  855. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  856. &cp->ctx_arr[i].mapping,
  857. GFP_KERNEL);
  858. if (cp->ctx_arr[i].ctx == NULL)
  859. return -ENOMEM;
  860. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  861. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  862. cnic_free_context(dev);
  863. cp->ctx_blk_size += cp->ctx_align;
  864. i = -1;
  865. continue;
  866. }
  867. }
  868. }
  869. return 0;
  870. }
  871. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  872. {
  873. struct cnic_local *cp = dev->cnic_priv;
  874. struct cnic_eth_dev *ethdev = cp->ethdev;
  875. u32 start_cid = ethdev->starting_cid;
  876. int i, j, n, ret, pages;
  877. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  878. cp->iro_arr = ethdev->iro_arr;
  879. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  880. cp->iscsi_start_cid = start_cid;
  881. if (start_cid < BNX2X_ISCSI_START_CID) {
  882. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  883. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  884. cp->max_cid_space += delta;
  885. }
  886. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  887. GFP_KERNEL);
  888. if (!cp->iscsi_tbl)
  889. goto error;
  890. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  891. cp->max_cid_space, GFP_KERNEL);
  892. if (!cp->ctx_tbl)
  893. goto error;
  894. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  895. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  896. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  897. }
  898. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  899. PAGE_SIZE;
  900. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  901. if (ret)
  902. return -ENOMEM;
  903. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  904. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  905. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  906. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  907. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  908. off;
  909. if ((i % n) == (n - 1))
  910. j++;
  911. }
  912. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  913. if (ret)
  914. goto error;
  915. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  916. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  917. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  918. if (ret)
  919. goto error;
  920. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  921. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  922. if (ret)
  923. goto error;
  924. ret = cnic_alloc_bnx2x_context(dev);
  925. if (ret)
  926. goto error;
  927. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  928. cp->l2_rx_ring_size = 15;
  929. ret = cnic_alloc_l2_rings(dev, 4);
  930. if (ret)
  931. goto error;
  932. ret = cnic_alloc_uio(dev);
  933. if (ret)
  934. goto error;
  935. return 0;
  936. error:
  937. cnic_free_resc(dev);
  938. return -ENOMEM;
  939. }
  940. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  941. {
  942. return cp->max_kwq_idx -
  943. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  944. }
  945. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  946. u32 num_wqes)
  947. {
  948. struct cnic_local *cp = dev->cnic_priv;
  949. struct kwqe *prod_qe;
  950. u16 prod, sw_prod, i;
  951. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  952. return -EAGAIN; /* bnx2 is down */
  953. spin_lock_bh(&cp->cnic_ulp_lock);
  954. if (num_wqes > cnic_kwq_avail(cp) &&
  955. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  956. spin_unlock_bh(&cp->cnic_ulp_lock);
  957. return -EAGAIN;
  958. }
  959. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  960. prod = cp->kwq_prod_idx;
  961. sw_prod = prod & MAX_KWQ_IDX;
  962. for (i = 0; i < num_wqes; i++) {
  963. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  964. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  965. prod++;
  966. sw_prod = prod & MAX_KWQ_IDX;
  967. }
  968. cp->kwq_prod_idx = prod;
  969. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  970. spin_unlock_bh(&cp->cnic_ulp_lock);
  971. return 0;
  972. }
  973. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  974. union l5cm_specific_data *l5_data)
  975. {
  976. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  977. dma_addr_t map;
  978. map = ctx->kwqe_data_mapping;
  979. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  980. l5_data->phy_address.hi = (u64) map >> 32;
  981. return ctx->kwqe_data;
  982. }
  983. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  984. u32 type, union l5cm_specific_data *l5_data)
  985. {
  986. struct cnic_local *cp = dev->cnic_priv;
  987. struct l5cm_spe kwqe;
  988. struct kwqe_16 *kwq[1];
  989. int ret;
  990. kwqe.hdr.conn_and_cmd_data =
  991. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  992. BNX2X_HW_CID(cp, cid)));
  993. kwqe.hdr.type = cpu_to_le16(type);
  994. kwqe.hdr.reserved1 = 0;
  995. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  996. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  997. kwq[0] = (struct kwqe_16 *) &kwqe;
  998. spin_lock_bh(&cp->cnic_ulp_lock);
  999. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1000. spin_unlock_bh(&cp->cnic_ulp_lock);
  1001. if (ret == 1)
  1002. return 0;
  1003. return -EBUSY;
  1004. }
  1005. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1006. struct kcqe *cqes[], u32 num_cqes)
  1007. {
  1008. struct cnic_local *cp = dev->cnic_priv;
  1009. struct cnic_ulp_ops *ulp_ops;
  1010. rcu_read_lock();
  1011. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1012. if (likely(ulp_ops)) {
  1013. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1014. cqes, num_cqes);
  1015. }
  1016. rcu_read_unlock();
  1017. }
  1018. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1019. {
  1020. struct cnic_local *cp = dev->cnic_priv;
  1021. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1022. int hq_bds, pages;
  1023. u32 pfid = cp->pfid;
  1024. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1025. cp->num_ccells = req1->num_ccells_per_conn;
  1026. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1027. cp->num_iscsi_tasks;
  1028. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1029. BNX2X_ISCSI_R2TQE_SIZE;
  1030. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1031. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1032. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1033. cp->num_cqs = req1->num_cqs;
  1034. if (!dev->max_iscsi_conn)
  1035. return 0;
  1036. /* init Tstorm RAM */
  1037. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1038. req1->rq_num_wqes);
  1039. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1040. PAGE_SIZE);
  1041. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1042. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1043. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1044. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1045. req1->num_tasks_per_conn);
  1046. /* init Ustorm RAM */
  1047. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1048. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1049. req1->rq_buffer_size);
  1050. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1051. PAGE_SIZE);
  1052. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1053. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1054. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1055. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1056. req1->num_tasks_per_conn);
  1057. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1058. req1->rq_num_wqes);
  1059. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1060. req1->cq_num_wqes);
  1061. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1062. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1063. /* init Xstorm RAM */
  1064. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1065. PAGE_SIZE);
  1066. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1067. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1068. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1069. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1070. req1->num_tasks_per_conn);
  1071. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1072. hq_bds);
  1073. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1074. req1->num_tasks_per_conn);
  1075. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1076. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1077. /* init Cstorm RAM */
  1078. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1079. PAGE_SIZE);
  1080. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1081. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1082. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1083. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1084. req1->num_tasks_per_conn);
  1085. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1086. req1->cq_num_wqes);
  1087. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1088. hq_bds);
  1089. return 0;
  1090. }
  1091. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1092. {
  1093. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1094. struct cnic_local *cp = dev->cnic_priv;
  1095. u32 pfid = cp->pfid;
  1096. struct iscsi_kcqe kcqe;
  1097. struct kcqe *cqes[1];
  1098. memset(&kcqe, 0, sizeof(kcqe));
  1099. if (!dev->max_iscsi_conn) {
  1100. kcqe.completion_status =
  1101. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1102. goto done;
  1103. }
  1104. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1105. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1106. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1107. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1108. req2->error_bit_map[1]);
  1109. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1110. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1111. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1112. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1113. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1114. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1115. req2->error_bit_map[1]);
  1116. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1117. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1118. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1119. done:
  1120. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1121. cqes[0] = (struct kcqe *) &kcqe;
  1122. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1123. return 0;
  1124. }
  1125. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1126. {
  1127. struct cnic_local *cp = dev->cnic_priv;
  1128. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1129. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1130. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1131. cnic_free_dma(dev, &iscsi->hq_info);
  1132. cnic_free_dma(dev, &iscsi->r2tq_info);
  1133. cnic_free_dma(dev, &iscsi->task_array_info);
  1134. }
  1135. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1136. ctx->cid = 0;
  1137. }
  1138. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1139. {
  1140. u32 cid;
  1141. int ret, pages;
  1142. struct cnic_local *cp = dev->cnic_priv;
  1143. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1144. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1145. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1146. if (cid == -1) {
  1147. ret = -ENOMEM;
  1148. goto error;
  1149. }
  1150. ctx->cid = cid;
  1151. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1152. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1153. if (ret)
  1154. goto error;
  1155. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1156. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1157. if (ret)
  1158. goto error;
  1159. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1160. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1161. if (ret)
  1162. goto error;
  1163. return 0;
  1164. error:
  1165. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1166. return ret;
  1167. }
  1168. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1169. struct regpair *ctx_addr)
  1170. {
  1171. struct cnic_local *cp = dev->cnic_priv;
  1172. struct cnic_eth_dev *ethdev = cp->ethdev;
  1173. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1174. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1175. unsigned long align_off = 0;
  1176. dma_addr_t ctx_map;
  1177. void *ctx;
  1178. if (cp->ctx_align) {
  1179. unsigned long mask = cp->ctx_align - 1;
  1180. if (cp->ctx_arr[blk].mapping & mask)
  1181. align_off = cp->ctx_align -
  1182. (cp->ctx_arr[blk].mapping & mask);
  1183. }
  1184. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1185. (off * BNX2X_CONTEXT_MEM_SIZE);
  1186. ctx = cp->ctx_arr[blk].ctx + align_off +
  1187. (off * BNX2X_CONTEXT_MEM_SIZE);
  1188. if (init)
  1189. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1190. ctx_addr->lo = ctx_map & 0xffffffff;
  1191. ctx_addr->hi = (u64) ctx_map >> 32;
  1192. return ctx;
  1193. }
  1194. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1195. u32 num)
  1196. {
  1197. struct cnic_local *cp = dev->cnic_priv;
  1198. struct iscsi_kwqe_conn_offload1 *req1 =
  1199. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1200. struct iscsi_kwqe_conn_offload2 *req2 =
  1201. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1202. struct iscsi_kwqe_conn_offload3 *req3;
  1203. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1204. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1205. u32 cid = ctx->cid;
  1206. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1207. struct iscsi_context *ictx;
  1208. struct regpair context_addr;
  1209. int i, j, n = 2, n_max;
  1210. ctx->ctx_flags = 0;
  1211. if (!req2->num_additional_wqes)
  1212. return -EINVAL;
  1213. n_max = req2->num_additional_wqes + 2;
  1214. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1215. if (ictx == NULL)
  1216. return -ENOMEM;
  1217. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1218. ictx->xstorm_ag_context.hq_prod = 1;
  1219. ictx->xstorm_st_context.iscsi.first_burst_length =
  1220. ISCSI_DEF_FIRST_BURST_LEN;
  1221. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1222. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1223. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1224. req1->sq_page_table_addr_lo;
  1225. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1226. req1->sq_page_table_addr_hi;
  1227. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1228. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1229. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1230. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1231. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1232. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1233. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1234. iscsi->hq_info.pgtbl[0];
  1235. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1236. iscsi->hq_info.pgtbl[1];
  1237. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1238. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1239. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1240. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1241. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1242. iscsi->r2tq_info.pgtbl[0];
  1243. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1244. iscsi->r2tq_info.pgtbl[1];
  1245. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1246. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1247. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1248. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1249. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1250. BNX2X_ISCSI_PBL_NOT_CACHED;
  1251. ictx->xstorm_st_context.iscsi.flags.flags |=
  1252. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1253. ictx->xstorm_st_context.iscsi.flags.flags |=
  1254. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1255. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1256. /* TSTORM requires the base address of RQ DB & not PTE */
  1257. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1258. req2->rq_page_table_addr_lo & PAGE_MASK;
  1259. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1260. req2->rq_page_table_addr_hi;
  1261. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1262. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1263. ictx->tstorm_st_context.tcp.flags2 |=
  1264. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1265. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1266. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1267. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1268. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1269. req2->rq_page_table_addr_lo;
  1270. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1271. req2->rq_page_table_addr_hi;
  1272. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1273. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1274. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1275. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1276. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1277. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1278. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1279. iscsi->r2tq_info.pgtbl[0];
  1280. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1281. iscsi->r2tq_info.pgtbl[1];
  1282. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1283. req1->cq_page_table_addr_lo;
  1284. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1285. req1->cq_page_table_addr_hi;
  1286. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1287. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1288. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1289. ictx->ustorm_st_context.task_pbe_cache_index =
  1290. BNX2X_ISCSI_PBL_NOT_CACHED;
  1291. ictx->ustorm_st_context.task_pdu_cache_index =
  1292. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1293. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1294. if (j == 3) {
  1295. if (n >= n_max)
  1296. break;
  1297. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1298. j = 0;
  1299. }
  1300. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1301. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1302. req3->qp_first_pte[j].hi;
  1303. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1304. req3->qp_first_pte[j].lo;
  1305. }
  1306. ictx->ustorm_st_context.task_pbl_base.lo =
  1307. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1308. ictx->ustorm_st_context.task_pbl_base.hi =
  1309. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1310. ictx->ustorm_st_context.tce_phy_addr.lo =
  1311. iscsi->task_array_info.pgtbl[0];
  1312. ictx->ustorm_st_context.tce_phy_addr.hi =
  1313. iscsi->task_array_info.pgtbl[1];
  1314. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1315. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1316. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1317. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1318. ISCSI_DEF_MAX_BURST_LEN;
  1319. ictx->ustorm_st_context.negotiated_rx |=
  1320. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1321. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1322. ictx->cstorm_st_context.hq_pbl_base.lo =
  1323. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1324. ictx->cstorm_st_context.hq_pbl_base.hi =
  1325. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1326. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1327. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1328. ictx->cstorm_st_context.task_pbl_base.lo =
  1329. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1330. ictx->cstorm_st_context.task_pbl_base.hi =
  1331. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1332. /* CSTORM and USTORM initialization is different, CSTORM requires
  1333. * CQ DB base & not PTE addr */
  1334. ictx->cstorm_st_context.cq_db_base.lo =
  1335. req1->cq_page_table_addr_lo & PAGE_MASK;
  1336. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1337. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1338. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1339. for (i = 0; i < cp->num_cqs; i++) {
  1340. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1341. ISCSI_INITIAL_SN;
  1342. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1343. ISCSI_INITIAL_SN;
  1344. }
  1345. ictx->xstorm_ag_context.cdu_reserved =
  1346. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1347. ISCSI_CONNECTION_TYPE);
  1348. ictx->ustorm_ag_context.cdu_usage =
  1349. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1350. ISCSI_CONNECTION_TYPE);
  1351. return 0;
  1352. }
  1353. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1354. u32 num, int *work)
  1355. {
  1356. struct iscsi_kwqe_conn_offload1 *req1;
  1357. struct iscsi_kwqe_conn_offload2 *req2;
  1358. struct cnic_local *cp = dev->cnic_priv;
  1359. struct cnic_context *ctx;
  1360. struct iscsi_kcqe kcqe;
  1361. struct kcqe *cqes[1];
  1362. u32 l5_cid;
  1363. int ret = 0;
  1364. if (num < 2) {
  1365. *work = num;
  1366. return -EINVAL;
  1367. }
  1368. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1369. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1370. if ((num - 2) < req2->num_additional_wqes) {
  1371. *work = num;
  1372. return -EINVAL;
  1373. }
  1374. *work = 2 + req2->num_additional_wqes;;
  1375. l5_cid = req1->iscsi_conn_id;
  1376. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1377. return -EINVAL;
  1378. memset(&kcqe, 0, sizeof(kcqe));
  1379. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1380. kcqe.iscsi_conn_id = l5_cid;
  1381. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1382. ctx = &cp->ctx_tbl[l5_cid];
  1383. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1384. kcqe.completion_status =
  1385. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1386. goto done;
  1387. }
  1388. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1389. atomic_dec(&cp->iscsi_conn);
  1390. goto done;
  1391. }
  1392. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1393. if (ret) {
  1394. atomic_dec(&cp->iscsi_conn);
  1395. ret = 0;
  1396. goto done;
  1397. }
  1398. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1399. if (ret < 0) {
  1400. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1401. atomic_dec(&cp->iscsi_conn);
  1402. goto done;
  1403. }
  1404. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1405. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1406. done:
  1407. cqes[0] = (struct kcqe *) &kcqe;
  1408. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1409. return ret;
  1410. }
  1411. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1412. {
  1413. struct cnic_local *cp = dev->cnic_priv;
  1414. struct iscsi_kwqe_conn_update *req =
  1415. (struct iscsi_kwqe_conn_update *) kwqe;
  1416. void *data;
  1417. union l5cm_specific_data l5_data;
  1418. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1419. int ret;
  1420. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1421. return -EINVAL;
  1422. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1423. if (!data)
  1424. return -ENOMEM;
  1425. memcpy(data, kwqe, sizeof(struct kwqe));
  1426. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1427. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1428. return ret;
  1429. }
  1430. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1431. {
  1432. struct cnic_local *cp = dev->cnic_priv;
  1433. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1434. union l5cm_specific_data l5_data;
  1435. int ret;
  1436. u32 hw_cid, type;
  1437. init_waitqueue_head(&ctx->waitq);
  1438. ctx->wait_cond = 0;
  1439. memset(&l5_data, 0, sizeof(l5_data));
  1440. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1441. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  1442. & SPE_HDR_CONN_TYPE;
  1443. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1444. SPE_HDR_FUNCTION_ID);
  1445. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1446. hw_cid, type, &l5_data);
  1447. if (ret == 0)
  1448. wait_event(ctx->waitq, ctx->wait_cond);
  1449. return ret;
  1450. }
  1451. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1452. {
  1453. struct cnic_local *cp = dev->cnic_priv;
  1454. struct iscsi_kwqe_conn_destroy *req =
  1455. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1456. u32 l5_cid = req->reserved0;
  1457. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1458. int ret = 0;
  1459. struct iscsi_kcqe kcqe;
  1460. struct kcqe *cqes[1];
  1461. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1462. goto skip_cfc_delete;
  1463. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1464. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1465. if (delta > (2 * HZ))
  1466. delta = 0;
  1467. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1468. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1469. goto destroy_reply;
  1470. }
  1471. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1472. skip_cfc_delete:
  1473. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1474. atomic_dec(&cp->iscsi_conn);
  1475. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1476. destroy_reply:
  1477. memset(&kcqe, 0, sizeof(kcqe));
  1478. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1479. kcqe.iscsi_conn_id = l5_cid;
  1480. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1481. kcqe.iscsi_conn_context_id = req->context_id;
  1482. cqes[0] = (struct kcqe *) &kcqe;
  1483. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1484. return ret;
  1485. }
  1486. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1487. struct l4_kwq_connect_req1 *kwqe1,
  1488. struct l4_kwq_connect_req3 *kwqe3,
  1489. struct l5cm_active_conn_buffer *conn_buf)
  1490. {
  1491. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1492. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1493. &conn_buf->xstorm_conn_buffer;
  1494. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1495. &conn_buf->tstorm_conn_buffer;
  1496. struct regpair context_addr;
  1497. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1498. struct in6_addr src_ip, dst_ip;
  1499. int i;
  1500. u32 *addrp;
  1501. addrp = (u32 *) &conn_addr->local_ip_addr;
  1502. for (i = 0; i < 4; i++, addrp++)
  1503. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1504. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1505. for (i = 0; i < 4; i++, addrp++)
  1506. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1507. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1508. xstorm_buf->context_addr.hi = context_addr.hi;
  1509. xstorm_buf->context_addr.lo = context_addr.lo;
  1510. xstorm_buf->mss = 0xffff;
  1511. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1512. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1513. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1514. xstorm_buf->pseudo_header_checksum =
  1515. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1516. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1517. tstorm_buf->params |=
  1518. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1519. if (kwqe3->ka_timeout) {
  1520. tstorm_buf->ka_enable = 1;
  1521. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1522. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1523. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1524. }
  1525. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1526. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1527. tstorm_buf->max_rt_time = 0xffffffff;
  1528. }
  1529. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1530. {
  1531. struct cnic_local *cp = dev->cnic_priv;
  1532. u32 pfid = cp->pfid;
  1533. u8 *mac = dev->mac_addr;
  1534. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1535. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1536. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1537. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1538. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1539. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1540. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1541. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1542. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1543. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1544. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1545. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1546. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1547. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1548. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1549. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1550. mac[4]);
  1551. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1552. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1553. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1554. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1555. mac[2]);
  1556. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1557. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1558. mac[1]);
  1559. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1560. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1561. mac[0]);
  1562. }
  1563. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1564. {
  1565. struct cnic_local *cp = dev->cnic_priv;
  1566. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1567. u16 tstorm_flags = 0;
  1568. if (tcp_ts) {
  1569. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1570. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1571. }
  1572. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1573. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1574. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1575. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1576. }
  1577. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1578. u32 num, int *work)
  1579. {
  1580. struct cnic_local *cp = dev->cnic_priv;
  1581. struct l4_kwq_connect_req1 *kwqe1 =
  1582. (struct l4_kwq_connect_req1 *) wqes[0];
  1583. struct l4_kwq_connect_req3 *kwqe3;
  1584. struct l5cm_active_conn_buffer *conn_buf;
  1585. struct l5cm_conn_addr_params *conn_addr;
  1586. union l5cm_specific_data l5_data;
  1587. u32 l5_cid = kwqe1->pg_cid;
  1588. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1589. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1590. int ret;
  1591. if (num < 2) {
  1592. *work = num;
  1593. return -EINVAL;
  1594. }
  1595. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1596. *work = 3;
  1597. else
  1598. *work = 2;
  1599. if (num < *work) {
  1600. *work = num;
  1601. return -EINVAL;
  1602. }
  1603. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1604. netdev_err(dev->netdev, "conn_buf size too big\n");
  1605. return -ENOMEM;
  1606. }
  1607. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1608. if (!conn_buf)
  1609. return -ENOMEM;
  1610. memset(conn_buf, 0, sizeof(*conn_buf));
  1611. conn_addr = &conn_buf->conn_addr_buf;
  1612. conn_addr->remote_addr_0 = csk->ha[0];
  1613. conn_addr->remote_addr_1 = csk->ha[1];
  1614. conn_addr->remote_addr_2 = csk->ha[2];
  1615. conn_addr->remote_addr_3 = csk->ha[3];
  1616. conn_addr->remote_addr_4 = csk->ha[4];
  1617. conn_addr->remote_addr_5 = csk->ha[5];
  1618. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1619. struct l4_kwq_connect_req2 *kwqe2 =
  1620. (struct l4_kwq_connect_req2 *) wqes[1];
  1621. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1622. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1623. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1624. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1625. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1626. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1627. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1628. }
  1629. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1630. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1631. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1632. conn_addr->local_tcp_port = kwqe1->src_port;
  1633. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1634. conn_addr->pmtu = kwqe3->pmtu;
  1635. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1636. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1637. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1638. cnic_bnx2x_set_tcp_timestamp(dev,
  1639. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1640. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1641. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1642. if (!ret)
  1643. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1644. return ret;
  1645. }
  1646. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1647. {
  1648. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1649. union l5cm_specific_data l5_data;
  1650. int ret;
  1651. memset(&l5_data, 0, sizeof(l5_data));
  1652. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1653. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1654. return ret;
  1655. }
  1656. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1657. {
  1658. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1659. union l5cm_specific_data l5_data;
  1660. int ret;
  1661. memset(&l5_data, 0, sizeof(l5_data));
  1662. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1663. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1664. return ret;
  1665. }
  1666. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1667. {
  1668. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1669. struct l4_kcq kcqe;
  1670. struct kcqe *cqes[1];
  1671. memset(&kcqe, 0, sizeof(kcqe));
  1672. kcqe.pg_host_opaque = req->host_opaque;
  1673. kcqe.pg_cid = req->host_opaque;
  1674. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1675. cqes[0] = (struct kcqe *) &kcqe;
  1676. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1677. return 0;
  1678. }
  1679. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1680. {
  1681. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1682. struct l4_kcq kcqe;
  1683. struct kcqe *cqes[1];
  1684. memset(&kcqe, 0, sizeof(kcqe));
  1685. kcqe.pg_host_opaque = req->pg_host_opaque;
  1686. kcqe.pg_cid = req->pg_cid;
  1687. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1688. cqes[0] = (struct kcqe *) &kcqe;
  1689. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1690. return 0;
  1691. }
  1692. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1693. u32 num_wqes)
  1694. {
  1695. int i, work, ret;
  1696. u32 opcode;
  1697. struct kwqe *kwqe;
  1698. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1699. return -EAGAIN; /* bnx2 is down */
  1700. for (i = 0; i < num_wqes; ) {
  1701. kwqe = wqes[i];
  1702. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1703. work = 1;
  1704. switch (opcode) {
  1705. case ISCSI_KWQE_OPCODE_INIT1:
  1706. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1707. break;
  1708. case ISCSI_KWQE_OPCODE_INIT2:
  1709. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1710. break;
  1711. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1712. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1713. num_wqes - i, &work);
  1714. break;
  1715. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1716. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1717. break;
  1718. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1719. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1720. break;
  1721. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1722. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1723. &work);
  1724. break;
  1725. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1726. ret = cnic_bnx2x_close(dev, kwqe);
  1727. break;
  1728. case L4_KWQE_OPCODE_VALUE_RESET:
  1729. ret = cnic_bnx2x_reset(dev, kwqe);
  1730. break;
  1731. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1732. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1733. break;
  1734. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1735. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1736. break;
  1737. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1738. ret = 0;
  1739. break;
  1740. default:
  1741. ret = 0;
  1742. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  1743. opcode);
  1744. break;
  1745. }
  1746. if (ret < 0)
  1747. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  1748. opcode);
  1749. i += work;
  1750. }
  1751. return 0;
  1752. }
  1753. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1754. {
  1755. struct cnic_local *cp = dev->cnic_priv;
  1756. int i, j, comp = 0;
  1757. i = 0;
  1758. j = 1;
  1759. while (num_cqes) {
  1760. struct cnic_ulp_ops *ulp_ops;
  1761. int ulp_type;
  1762. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1763. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1764. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1765. comp++;
  1766. while (j < num_cqes) {
  1767. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1768. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1769. break;
  1770. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1771. comp++;
  1772. j++;
  1773. }
  1774. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1775. ulp_type = CNIC_ULP_RDMA;
  1776. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1777. ulp_type = CNIC_ULP_ISCSI;
  1778. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1779. ulp_type = CNIC_ULP_L4;
  1780. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1781. goto end;
  1782. else {
  1783. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  1784. kcqe_op_flag);
  1785. goto end;
  1786. }
  1787. rcu_read_lock();
  1788. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1789. if (likely(ulp_ops)) {
  1790. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1791. cp->completed_kcq + i, j);
  1792. }
  1793. rcu_read_unlock();
  1794. end:
  1795. num_cqes -= j;
  1796. i += j;
  1797. j = 1;
  1798. }
  1799. if (unlikely(comp))
  1800. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  1801. }
  1802. static u16 cnic_bnx2_next_idx(u16 idx)
  1803. {
  1804. return idx + 1;
  1805. }
  1806. static u16 cnic_bnx2_hw_idx(u16 idx)
  1807. {
  1808. return idx;
  1809. }
  1810. static u16 cnic_bnx2x_next_idx(u16 idx)
  1811. {
  1812. idx++;
  1813. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1814. idx++;
  1815. return idx;
  1816. }
  1817. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1818. {
  1819. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1820. idx++;
  1821. return idx;
  1822. }
  1823. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  1824. {
  1825. struct cnic_local *cp = dev->cnic_priv;
  1826. u16 i, ri, hw_prod, last;
  1827. struct kcqe *kcqe;
  1828. int kcqe_cnt = 0, last_cnt = 0;
  1829. i = ri = last = info->sw_prod_idx;
  1830. ri &= MAX_KCQ_IDX;
  1831. hw_prod = *info->hw_prod_idx_ptr;
  1832. hw_prod = cp->hw_idx(hw_prod);
  1833. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1834. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1835. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1836. i = cp->next_idx(i);
  1837. ri = i & MAX_KCQ_IDX;
  1838. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1839. last_cnt = kcqe_cnt;
  1840. last = i;
  1841. }
  1842. }
  1843. info->sw_prod_idx = last;
  1844. return last_cnt;
  1845. }
  1846. static int cnic_l2_completion(struct cnic_local *cp)
  1847. {
  1848. u16 hw_cons, sw_cons;
  1849. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  1850. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  1851. u32 cmd;
  1852. int comp = 0;
  1853. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  1854. return 0;
  1855. hw_cons = *cp->rx_cons_ptr;
  1856. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  1857. hw_cons++;
  1858. sw_cons = cp->rx_cons;
  1859. while (sw_cons != hw_cons) {
  1860. u8 cqe_fp_flags;
  1861. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  1862. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  1863. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  1864. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  1865. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  1866. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  1867. cmd == RAMROD_CMD_ID_ETH_HALT)
  1868. comp++;
  1869. }
  1870. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  1871. }
  1872. return comp;
  1873. }
  1874. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1875. {
  1876. u16 rx_cons, tx_cons;
  1877. int comp = 0;
  1878. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  1879. return;
  1880. rx_cons = *cp->rx_cons_ptr;
  1881. tx_cons = *cp->tx_cons_ptr;
  1882. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1883. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  1884. comp = cnic_l2_completion(cp);
  1885. cp->tx_cons = tx_cons;
  1886. cp->rx_cons = rx_cons;
  1887. uio_event_notify(cp->cnic_uinfo);
  1888. }
  1889. if (comp)
  1890. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  1891. }
  1892. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  1893. {
  1894. struct cnic_local *cp = dev->cnic_priv;
  1895. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1896. int kcqe_cnt;
  1897. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1898. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  1899. service_kcqes(dev, kcqe_cnt);
  1900. /* Tell compiler that status_blk fields can change. */
  1901. barrier();
  1902. if (status_idx != *cp->kcq1.status_idx_ptr) {
  1903. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1904. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1905. } else
  1906. break;
  1907. }
  1908. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  1909. cnic_chk_pkt_rings(cp);
  1910. return status_idx;
  1911. }
  1912. static int cnic_service_bnx2(void *data, void *status_blk)
  1913. {
  1914. struct cnic_dev *dev = data;
  1915. struct cnic_local *cp = dev->cnic_priv;
  1916. u32 status_idx = *cp->kcq1.status_idx_ptr;
  1917. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1918. return status_idx;
  1919. return cnic_service_bnx2_queues(dev);
  1920. }
  1921. static void cnic_service_bnx2_msix(unsigned long data)
  1922. {
  1923. struct cnic_dev *dev = (struct cnic_dev *) data;
  1924. struct cnic_local *cp = dev->cnic_priv;
  1925. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  1926. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1927. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1928. }
  1929. static void cnic_doirq(struct cnic_dev *dev)
  1930. {
  1931. struct cnic_local *cp = dev->cnic_priv;
  1932. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  1933. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  1934. prefetch(cp->status_blk.gen);
  1935. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1936. tasklet_schedule(&cp->cnic_irq_task);
  1937. }
  1938. }
  1939. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1940. {
  1941. struct cnic_dev *dev = dev_instance;
  1942. struct cnic_local *cp = dev->cnic_priv;
  1943. if (cp->ack_int)
  1944. cp->ack_int(dev);
  1945. cnic_doirq(dev);
  1946. return IRQ_HANDLED;
  1947. }
  1948. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1949. u16 index, u8 op, u8 update)
  1950. {
  1951. struct cnic_local *cp = dev->cnic_priv;
  1952. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1953. COMMAND_REG_INT_ACK);
  1954. struct igu_ack_register igu_ack;
  1955. igu_ack.status_block_index = index;
  1956. igu_ack.sb_id_and_flags =
  1957. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  1958. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  1959. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  1960. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  1961. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  1962. }
  1963. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  1964. {
  1965. struct cnic_local *cp = dev->cnic_priv;
  1966. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  1967. IGU_INT_DISABLE, 0);
  1968. }
  1969. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  1970. {
  1971. u32 last_status = *info->status_idx_ptr;
  1972. int kcqe_cnt;
  1973. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  1974. service_kcqes(dev, kcqe_cnt);
  1975. /* Tell compiler that sblk fields can change. */
  1976. barrier();
  1977. if (last_status == *info->status_idx_ptr)
  1978. break;
  1979. last_status = *info->status_idx_ptr;
  1980. }
  1981. return last_status;
  1982. }
  1983. static void cnic_service_bnx2x_bh(unsigned long data)
  1984. {
  1985. struct cnic_dev *dev = (struct cnic_dev *) data;
  1986. struct cnic_local *cp = dev->cnic_priv;
  1987. u32 status_idx;
  1988. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1989. return;
  1990. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  1991. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  1992. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  1993. status_idx, IGU_INT_ENABLE, 1);
  1994. }
  1995. static int cnic_service_bnx2x(void *data, void *status_blk)
  1996. {
  1997. struct cnic_dev *dev = data;
  1998. struct cnic_local *cp = dev->cnic_priv;
  1999. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2000. cnic_doirq(dev);
  2001. cnic_chk_pkt_rings(cp);
  2002. return 0;
  2003. }
  2004. static void cnic_ulp_stop(struct cnic_dev *dev)
  2005. {
  2006. struct cnic_local *cp = dev->cnic_priv;
  2007. int if_type;
  2008. if (cp->cnic_uinfo)
  2009. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2010. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2011. struct cnic_ulp_ops *ulp_ops;
  2012. mutex_lock(&cnic_lock);
  2013. ulp_ops = cp->ulp_ops[if_type];
  2014. if (!ulp_ops) {
  2015. mutex_unlock(&cnic_lock);
  2016. continue;
  2017. }
  2018. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2019. mutex_unlock(&cnic_lock);
  2020. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2021. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2022. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2023. }
  2024. }
  2025. static void cnic_ulp_start(struct cnic_dev *dev)
  2026. {
  2027. struct cnic_local *cp = dev->cnic_priv;
  2028. int if_type;
  2029. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2030. struct cnic_ulp_ops *ulp_ops;
  2031. mutex_lock(&cnic_lock);
  2032. ulp_ops = cp->ulp_ops[if_type];
  2033. if (!ulp_ops || !ulp_ops->cnic_start) {
  2034. mutex_unlock(&cnic_lock);
  2035. continue;
  2036. }
  2037. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2038. mutex_unlock(&cnic_lock);
  2039. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2040. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2041. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2042. }
  2043. }
  2044. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2045. {
  2046. struct cnic_dev *dev = data;
  2047. switch (info->cmd) {
  2048. case CNIC_CTL_STOP_CMD:
  2049. cnic_hold(dev);
  2050. cnic_ulp_stop(dev);
  2051. cnic_stop_hw(dev);
  2052. cnic_put(dev);
  2053. break;
  2054. case CNIC_CTL_START_CMD:
  2055. cnic_hold(dev);
  2056. if (!cnic_start_hw(dev))
  2057. cnic_ulp_start(dev);
  2058. cnic_put(dev);
  2059. break;
  2060. case CNIC_CTL_COMPLETION_CMD: {
  2061. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2062. u32 l5_cid;
  2063. struct cnic_local *cp = dev->cnic_priv;
  2064. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2065. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2066. ctx->wait_cond = 1;
  2067. wake_up(&ctx->waitq);
  2068. }
  2069. break;
  2070. }
  2071. default:
  2072. return -EINVAL;
  2073. }
  2074. return 0;
  2075. }
  2076. static void cnic_ulp_init(struct cnic_dev *dev)
  2077. {
  2078. int i;
  2079. struct cnic_local *cp = dev->cnic_priv;
  2080. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2081. struct cnic_ulp_ops *ulp_ops;
  2082. mutex_lock(&cnic_lock);
  2083. ulp_ops = cnic_ulp_tbl[i];
  2084. if (!ulp_ops || !ulp_ops->cnic_init) {
  2085. mutex_unlock(&cnic_lock);
  2086. continue;
  2087. }
  2088. ulp_get(ulp_ops);
  2089. mutex_unlock(&cnic_lock);
  2090. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2091. ulp_ops->cnic_init(dev);
  2092. ulp_put(ulp_ops);
  2093. }
  2094. }
  2095. static void cnic_ulp_exit(struct cnic_dev *dev)
  2096. {
  2097. int i;
  2098. struct cnic_local *cp = dev->cnic_priv;
  2099. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2100. struct cnic_ulp_ops *ulp_ops;
  2101. mutex_lock(&cnic_lock);
  2102. ulp_ops = cnic_ulp_tbl[i];
  2103. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2104. mutex_unlock(&cnic_lock);
  2105. continue;
  2106. }
  2107. ulp_get(ulp_ops);
  2108. mutex_unlock(&cnic_lock);
  2109. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2110. ulp_ops->cnic_exit(dev);
  2111. ulp_put(ulp_ops);
  2112. }
  2113. }
  2114. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2115. {
  2116. struct cnic_dev *dev = csk->dev;
  2117. struct l4_kwq_offload_pg *l4kwqe;
  2118. struct kwqe *wqes[1];
  2119. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2120. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2121. wqes[0] = (struct kwqe *) l4kwqe;
  2122. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2123. l4kwqe->flags =
  2124. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2125. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2126. l4kwqe->da0 = csk->ha[0];
  2127. l4kwqe->da1 = csk->ha[1];
  2128. l4kwqe->da2 = csk->ha[2];
  2129. l4kwqe->da3 = csk->ha[3];
  2130. l4kwqe->da4 = csk->ha[4];
  2131. l4kwqe->da5 = csk->ha[5];
  2132. l4kwqe->sa0 = dev->mac_addr[0];
  2133. l4kwqe->sa1 = dev->mac_addr[1];
  2134. l4kwqe->sa2 = dev->mac_addr[2];
  2135. l4kwqe->sa3 = dev->mac_addr[3];
  2136. l4kwqe->sa4 = dev->mac_addr[4];
  2137. l4kwqe->sa5 = dev->mac_addr[5];
  2138. l4kwqe->etype = ETH_P_IP;
  2139. l4kwqe->ipid_start = DEF_IPID_START;
  2140. l4kwqe->host_opaque = csk->l5_cid;
  2141. if (csk->vlan_id) {
  2142. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2143. l4kwqe->vlan_tag = csk->vlan_id;
  2144. l4kwqe->l2hdr_nbytes += 4;
  2145. }
  2146. return dev->submit_kwqes(dev, wqes, 1);
  2147. }
  2148. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2149. {
  2150. struct cnic_dev *dev = csk->dev;
  2151. struct l4_kwq_update_pg *l4kwqe;
  2152. struct kwqe *wqes[1];
  2153. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2154. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2155. wqes[0] = (struct kwqe *) l4kwqe;
  2156. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2157. l4kwqe->flags =
  2158. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2159. l4kwqe->pg_cid = csk->pg_cid;
  2160. l4kwqe->da0 = csk->ha[0];
  2161. l4kwqe->da1 = csk->ha[1];
  2162. l4kwqe->da2 = csk->ha[2];
  2163. l4kwqe->da3 = csk->ha[3];
  2164. l4kwqe->da4 = csk->ha[4];
  2165. l4kwqe->da5 = csk->ha[5];
  2166. l4kwqe->pg_host_opaque = csk->l5_cid;
  2167. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2168. return dev->submit_kwqes(dev, wqes, 1);
  2169. }
  2170. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2171. {
  2172. struct cnic_dev *dev = csk->dev;
  2173. struct l4_kwq_upload *l4kwqe;
  2174. struct kwqe *wqes[1];
  2175. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2176. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2177. wqes[0] = (struct kwqe *) l4kwqe;
  2178. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2179. l4kwqe->flags =
  2180. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2181. l4kwqe->cid = csk->pg_cid;
  2182. return dev->submit_kwqes(dev, wqes, 1);
  2183. }
  2184. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2185. {
  2186. struct cnic_dev *dev = csk->dev;
  2187. struct l4_kwq_connect_req1 *l4kwqe1;
  2188. struct l4_kwq_connect_req2 *l4kwqe2;
  2189. struct l4_kwq_connect_req3 *l4kwqe3;
  2190. struct kwqe *wqes[3];
  2191. u8 tcp_flags = 0;
  2192. int num_wqes = 2;
  2193. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2194. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2195. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2196. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2197. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2198. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2199. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2200. l4kwqe3->flags =
  2201. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2202. l4kwqe3->ka_timeout = csk->ka_timeout;
  2203. l4kwqe3->ka_interval = csk->ka_interval;
  2204. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2205. l4kwqe3->tos = csk->tos;
  2206. l4kwqe3->ttl = csk->ttl;
  2207. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2208. l4kwqe3->pmtu = csk->mtu;
  2209. l4kwqe3->rcv_buf = csk->rcv_buf;
  2210. l4kwqe3->snd_buf = csk->snd_buf;
  2211. l4kwqe3->seed = csk->seed;
  2212. wqes[0] = (struct kwqe *) l4kwqe1;
  2213. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2214. wqes[1] = (struct kwqe *) l4kwqe2;
  2215. wqes[2] = (struct kwqe *) l4kwqe3;
  2216. num_wqes = 3;
  2217. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2218. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2219. l4kwqe2->flags =
  2220. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2221. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2222. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2223. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2224. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2225. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2226. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2227. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2228. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2229. sizeof(struct tcphdr);
  2230. } else {
  2231. wqes[1] = (struct kwqe *) l4kwqe3;
  2232. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2233. sizeof(struct tcphdr);
  2234. }
  2235. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2236. l4kwqe1->flags =
  2237. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2238. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2239. l4kwqe1->cid = csk->cid;
  2240. l4kwqe1->pg_cid = csk->pg_cid;
  2241. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2242. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2243. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2244. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2245. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2246. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2247. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2248. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2249. if (csk->tcp_flags & SK_TCP_NAGLE)
  2250. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2251. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2252. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2253. if (csk->tcp_flags & SK_TCP_SACK)
  2254. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2255. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2256. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2257. l4kwqe1->tcp_flags = tcp_flags;
  2258. return dev->submit_kwqes(dev, wqes, num_wqes);
  2259. }
  2260. static int cnic_cm_close_req(struct cnic_sock *csk)
  2261. {
  2262. struct cnic_dev *dev = csk->dev;
  2263. struct l4_kwq_close_req *l4kwqe;
  2264. struct kwqe *wqes[1];
  2265. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2266. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2267. wqes[0] = (struct kwqe *) l4kwqe;
  2268. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2269. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2270. l4kwqe->cid = csk->cid;
  2271. return dev->submit_kwqes(dev, wqes, 1);
  2272. }
  2273. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2274. {
  2275. struct cnic_dev *dev = csk->dev;
  2276. struct l4_kwq_reset_req *l4kwqe;
  2277. struct kwqe *wqes[1];
  2278. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2279. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2280. wqes[0] = (struct kwqe *) l4kwqe;
  2281. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2282. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2283. l4kwqe->cid = csk->cid;
  2284. return dev->submit_kwqes(dev, wqes, 1);
  2285. }
  2286. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2287. u32 l5_cid, struct cnic_sock **csk, void *context)
  2288. {
  2289. struct cnic_local *cp = dev->cnic_priv;
  2290. struct cnic_sock *csk1;
  2291. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2292. return -EINVAL;
  2293. if (cp->ctx_tbl) {
  2294. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2295. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2296. return -EAGAIN;
  2297. }
  2298. csk1 = &cp->csk_tbl[l5_cid];
  2299. if (atomic_read(&csk1->ref_count))
  2300. return -EAGAIN;
  2301. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2302. return -EBUSY;
  2303. csk1->dev = dev;
  2304. csk1->cid = cid;
  2305. csk1->l5_cid = l5_cid;
  2306. csk1->ulp_type = ulp_type;
  2307. csk1->context = context;
  2308. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2309. csk1->ka_interval = DEF_KA_INTERVAL;
  2310. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2311. csk1->tos = DEF_TOS;
  2312. csk1->ttl = DEF_TTL;
  2313. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2314. csk1->rcv_buf = DEF_RCV_BUF;
  2315. csk1->snd_buf = DEF_SND_BUF;
  2316. csk1->seed = DEF_SEED;
  2317. *csk = csk1;
  2318. return 0;
  2319. }
  2320. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2321. {
  2322. if (csk->src_port) {
  2323. struct cnic_dev *dev = csk->dev;
  2324. struct cnic_local *cp = dev->cnic_priv;
  2325. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  2326. csk->src_port = 0;
  2327. }
  2328. }
  2329. static void cnic_close_conn(struct cnic_sock *csk)
  2330. {
  2331. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2332. cnic_cm_upload_pg(csk);
  2333. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2334. }
  2335. cnic_cm_cleanup(csk);
  2336. }
  2337. static int cnic_cm_destroy(struct cnic_sock *csk)
  2338. {
  2339. if (!cnic_in_use(csk))
  2340. return -EINVAL;
  2341. csk_hold(csk);
  2342. clear_bit(SK_F_INUSE, &csk->flags);
  2343. smp_mb__after_clear_bit();
  2344. while (atomic_read(&csk->ref_count) != 1)
  2345. msleep(1);
  2346. cnic_cm_cleanup(csk);
  2347. csk->flags = 0;
  2348. csk_put(csk);
  2349. return 0;
  2350. }
  2351. static inline u16 cnic_get_vlan(struct net_device *dev,
  2352. struct net_device **vlan_dev)
  2353. {
  2354. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2355. *vlan_dev = vlan_dev_real_dev(dev);
  2356. return vlan_dev_vlan_id(dev);
  2357. }
  2358. *vlan_dev = dev;
  2359. return 0;
  2360. }
  2361. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2362. struct dst_entry **dst)
  2363. {
  2364. #if defined(CONFIG_INET)
  2365. struct flowi fl;
  2366. int err;
  2367. struct rtable *rt;
  2368. memset(&fl, 0, sizeof(fl));
  2369. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2370. err = ip_route_output_key(&init_net, &rt, &fl);
  2371. if (!err)
  2372. *dst = &rt->dst;
  2373. return err;
  2374. #else
  2375. return -ENETUNREACH;
  2376. #endif
  2377. }
  2378. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2379. struct dst_entry **dst)
  2380. {
  2381. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2382. struct flowi fl;
  2383. memset(&fl, 0, sizeof(fl));
  2384. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2385. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2386. fl.oif = dst_addr->sin6_scope_id;
  2387. *dst = ip6_route_output(&init_net, NULL, &fl);
  2388. if (*dst)
  2389. return 0;
  2390. #endif
  2391. return -ENETUNREACH;
  2392. }
  2393. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2394. int ulp_type)
  2395. {
  2396. struct cnic_dev *dev = NULL;
  2397. struct dst_entry *dst;
  2398. struct net_device *netdev = NULL;
  2399. int err = -ENETUNREACH;
  2400. if (dst_addr->sin_family == AF_INET)
  2401. err = cnic_get_v4_route(dst_addr, &dst);
  2402. else if (dst_addr->sin_family == AF_INET6) {
  2403. struct sockaddr_in6 *dst_addr6 =
  2404. (struct sockaddr_in6 *) dst_addr;
  2405. err = cnic_get_v6_route(dst_addr6, &dst);
  2406. } else
  2407. return NULL;
  2408. if (err)
  2409. return NULL;
  2410. if (!dst->dev)
  2411. goto done;
  2412. cnic_get_vlan(dst->dev, &netdev);
  2413. dev = cnic_from_netdev(netdev);
  2414. done:
  2415. dst_release(dst);
  2416. if (dev)
  2417. cnic_put(dev);
  2418. return dev;
  2419. }
  2420. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2421. {
  2422. struct cnic_dev *dev = csk->dev;
  2423. struct cnic_local *cp = dev->cnic_priv;
  2424. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2425. }
  2426. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2427. {
  2428. struct cnic_dev *dev = csk->dev;
  2429. struct cnic_local *cp = dev->cnic_priv;
  2430. int is_v6, rc = 0;
  2431. struct dst_entry *dst = NULL;
  2432. struct net_device *realdev;
  2433. u32 local_port;
  2434. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2435. saddr->remote.v6.sin6_family == AF_INET6)
  2436. is_v6 = 1;
  2437. else if (saddr->local.v4.sin_family == AF_INET &&
  2438. saddr->remote.v4.sin_family == AF_INET)
  2439. is_v6 = 0;
  2440. else
  2441. return -EINVAL;
  2442. clear_bit(SK_F_IPV6, &csk->flags);
  2443. if (is_v6) {
  2444. set_bit(SK_F_IPV6, &csk->flags);
  2445. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2446. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2447. sizeof(struct in6_addr));
  2448. csk->dst_port = saddr->remote.v6.sin6_port;
  2449. local_port = saddr->local.v6.sin6_port;
  2450. } else {
  2451. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2452. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2453. csk->dst_port = saddr->remote.v4.sin_port;
  2454. local_port = saddr->local.v4.sin_port;
  2455. }
  2456. csk->vlan_id = 0;
  2457. csk->mtu = dev->netdev->mtu;
  2458. if (dst && dst->dev) {
  2459. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2460. if (realdev == dev->netdev) {
  2461. csk->vlan_id = vlan;
  2462. csk->mtu = dst_mtu(dst);
  2463. }
  2464. }
  2465. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  2466. local_port < CNIC_LOCAL_PORT_MAX) {
  2467. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  2468. local_port = 0;
  2469. } else
  2470. local_port = 0;
  2471. if (!local_port) {
  2472. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  2473. if (local_port == -1) {
  2474. rc = -ENOMEM;
  2475. goto err_out;
  2476. }
  2477. }
  2478. csk->src_port = local_port;
  2479. err_out:
  2480. dst_release(dst);
  2481. return rc;
  2482. }
  2483. static void cnic_init_csk_state(struct cnic_sock *csk)
  2484. {
  2485. csk->state = 0;
  2486. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2487. clear_bit(SK_F_CLOSING, &csk->flags);
  2488. }
  2489. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2490. {
  2491. int err = 0;
  2492. if (!cnic_in_use(csk))
  2493. return -EINVAL;
  2494. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2495. return -EINVAL;
  2496. cnic_init_csk_state(csk);
  2497. err = cnic_get_route(csk, saddr);
  2498. if (err)
  2499. goto err_out;
  2500. err = cnic_resolve_addr(csk, saddr);
  2501. if (!err)
  2502. return 0;
  2503. err_out:
  2504. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2505. return err;
  2506. }
  2507. static int cnic_cm_abort(struct cnic_sock *csk)
  2508. {
  2509. struct cnic_local *cp = csk->dev->cnic_priv;
  2510. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2511. if (!cnic_in_use(csk))
  2512. return -EINVAL;
  2513. if (cnic_abort_prep(csk))
  2514. return cnic_cm_abort_req(csk);
  2515. /* Getting here means that we haven't started connect, or
  2516. * connect was not successful.
  2517. */
  2518. cp->close_conn(csk, opcode);
  2519. if (csk->state != opcode)
  2520. return -EALREADY;
  2521. return 0;
  2522. }
  2523. static int cnic_cm_close(struct cnic_sock *csk)
  2524. {
  2525. if (!cnic_in_use(csk))
  2526. return -EINVAL;
  2527. if (cnic_close_prep(csk)) {
  2528. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2529. return cnic_cm_close_req(csk);
  2530. } else {
  2531. return -EALREADY;
  2532. }
  2533. return 0;
  2534. }
  2535. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2536. u8 opcode)
  2537. {
  2538. struct cnic_ulp_ops *ulp_ops;
  2539. int ulp_type = csk->ulp_type;
  2540. rcu_read_lock();
  2541. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2542. if (ulp_ops) {
  2543. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2544. ulp_ops->cm_connect_complete(csk);
  2545. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2546. ulp_ops->cm_close_complete(csk);
  2547. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2548. ulp_ops->cm_remote_abort(csk);
  2549. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2550. ulp_ops->cm_abort_complete(csk);
  2551. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2552. ulp_ops->cm_remote_close(csk);
  2553. }
  2554. rcu_read_unlock();
  2555. }
  2556. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2557. {
  2558. if (cnic_offld_prep(csk)) {
  2559. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2560. cnic_cm_update_pg(csk);
  2561. else
  2562. cnic_cm_offload_pg(csk);
  2563. }
  2564. return 0;
  2565. }
  2566. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2567. {
  2568. struct cnic_local *cp = dev->cnic_priv;
  2569. u32 l5_cid = kcqe->pg_host_opaque;
  2570. u8 opcode = kcqe->op_code;
  2571. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2572. csk_hold(csk);
  2573. if (!cnic_in_use(csk))
  2574. goto done;
  2575. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2576. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2577. goto done;
  2578. }
  2579. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  2580. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  2581. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2582. cnic_cm_upcall(cp, csk,
  2583. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2584. goto done;
  2585. }
  2586. csk->pg_cid = kcqe->pg_cid;
  2587. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2588. cnic_cm_conn_req(csk);
  2589. done:
  2590. csk_put(csk);
  2591. }
  2592. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2593. {
  2594. struct cnic_local *cp = dev->cnic_priv;
  2595. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2596. u8 opcode = l4kcqe->op_code;
  2597. u32 l5_cid;
  2598. struct cnic_sock *csk;
  2599. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2600. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2601. cnic_cm_process_offld_pg(dev, l4kcqe);
  2602. return;
  2603. }
  2604. l5_cid = l4kcqe->conn_id;
  2605. if (opcode & 0x80)
  2606. l5_cid = l4kcqe->cid;
  2607. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2608. return;
  2609. csk = &cp->csk_tbl[l5_cid];
  2610. csk_hold(csk);
  2611. if (!cnic_in_use(csk)) {
  2612. csk_put(csk);
  2613. return;
  2614. }
  2615. switch (opcode) {
  2616. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  2617. if (l4kcqe->status != 0) {
  2618. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2619. cnic_cm_upcall(cp, csk,
  2620. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2621. }
  2622. break;
  2623. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2624. if (l4kcqe->status == 0)
  2625. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2626. smp_mb__before_clear_bit();
  2627. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2628. cnic_cm_upcall(cp, csk, opcode);
  2629. break;
  2630. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2631. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2632. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2633. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2634. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2635. cp->close_conn(csk, opcode);
  2636. break;
  2637. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2638. cnic_cm_upcall(cp, csk, opcode);
  2639. break;
  2640. }
  2641. csk_put(csk);
  2642. }
  2643. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2644. {
  2645. struct cnic_dev *dev = data;
  2646. int i;
  2647. for (i = 0; i < num; i++)
  2648. cnic_cm_process_kcqe(dev, kcqe[i]);
  2649. }
  2650. static struct cnic_ulp_ops cm_ulp_ops = {
  2651. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2652. };
  2653. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2654. {
  2655. struct cnic_local *cp = dev->cnic_priv;
  2656. kfree(cp->csk_tbl);
  2657. cp->csk_tbl = NULL;
  2658. cnic_free_id_tbl(&cp->csk_port_tbl);
  2659. }
  2660. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2661. {
  2662. struct cnic_local *cp = dev->cnic_priv;
  2663. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2664. GFP_KERNEL);
  2665. if (!cp->csk_tbl)
  2666. return -ENOMEM;
  2667. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2668. CNIC_LOCAL_PORT_MIN)) {
  2669. cnic_cm_free_mem(dev);
  2670. return -ENOMEM;
  2671. }
  2672. return 0;
  2673. }
  2674. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2675. {
  2676. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  2677. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  2678. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  2679. csk->state = opcode;
  2680. }
  2681. /* 1. If event opcode matches the expected event in csk->state
  2682. * 2. If the expected event is CLOSE_COMP, we accept any event
  2683. * 3. If the expected event is 0, meaning the connection was never
  2684. * never established, we accept the opcode from cm_abort.
  2685. */
  2686. if (opcode == csk->state || csk->state == 0 ||
  2687. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  2688. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  2689. if (csk->state == 0)
  2690. csk->state = opcode;
  2691. return 1;
  2692. }
  2693. }
  2694. return 0;
  2695. }
  2696. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2697. {
  2698. struct cnic_dev *dev = csk->dev;
  2699. struct cnic_local *cp = dev->cnic_priv;
  2700. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  2701. cnic_cm_upcall(cp, csk, opcode);
  2702. return;
  2703. }
  2704. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2705. cnic_close_conn(csk);
  2706. csk->state = opcode;
  2707. cnic_cm_upcall(cp, csk, opcode);
  2708. }
  2709. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2710. {
  2711. }
  2712. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2713. {
  2714. u32 seed;
  2715. get_random_bytes(&seed, 4);
  2716. cnic_ctx_wr(dev, 45, 0, seed);
  2717. return 0;
  2718. }
  2719. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2720. {
  2721. struct cnic_dev *dev = csk->dev;
  2722. struct cnic_local *cp = dev->cnic_priv;
  2723. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2724. union l5cm_specific_data l5_data;
  2725. u32 cmd = 0;
  2726. int close_complete = 0;
  2727. switch (opcode) {
  2728. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2729. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2730. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2731. if (cnic_ready_to_close(csk, opcode)) {
  2732. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2733. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2734. else
  2735. close_complete = 1;
  2736. }
  2737. break;
  2738. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2739. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2740. break;
  2741. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2742. close_complete = 1;
  2743. break;
  2744. }
  2745. if (cmd) {
  2746. memset(&l5_data, 0, sizeof(l5_data));
  2747. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2748. &l5_data);
  2749. } else if (close_complete) {
  2750. ctx->timestamp = jiffies;
  2751. cnic_close_conn(csk);
  2752. cnic_cm_upcall(cp, csk, csk->state);
  2753. }
  2754. }
  2755. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2756. {
  2757. struct cnic_local *cp = dev->cnic_priv;
  2758. int i;
  2759. if (!cp->ctx_tbl)
  2760. return;
  2761. if (!netif_running(dev->netdev))
  2762. return;
  2763. for (i = 0; i < cp->max_cid_space; i++) {
  2764. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2765. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2766. msleep(10);
  2767. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2768. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2769. ctx->cid);
  2770. }
  2771. cancel_delayed_work(&cp->delete_task);
  2772. flush_workqueue(cnic_wq);
  2773. if (atomic_read(&cp->iscsi_conn) != 0)
  2774. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  2775. atomic_read(&cp->iscsi_conn));
  2776. }
  2777. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2778. {
  2779. struct cnic_local *cp = dev->cnic_priv;
  2780. u32 pfid = cp->pfid;
  2781. u32 port = CNIC_PORT(cp);
  2782. cnic_init_bnx2x_mac(dev);
  2783. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2784. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2785. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  2786. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2787. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  2788. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2789. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  2790. DEF_MAX_DA_COUNT);
  2791. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2792. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  2793. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2794. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  2795. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2796. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  2797. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2798. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  2799. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  2800. DEF_MAX_CWND);
  2801. return 0;
  2802. }
  2803. static void cnic_delete_task(struct work_struct *work)
  2804. {
  2805. struct cnic_local *cp;
  2806. struct cnic_dev *dev;
  2807. u32 i;
  2808. int need_resched = 0;
  2809. cp = container_of(work, struct cnic_local, delete_task.work);
  2810. dev = cp->dev;
  2811. for (i = 0; i < cp->max_cid_space; i++) {
  2812. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2813. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  2814. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2815. continue;
  2816. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  2817. need_resched = 1;
  2818. continue;
  2819. }
  2820. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2821. continue;
  2822. cnic_bnx2x_destroy_ramrod(dev, i);
  2823. cnic_free_bnx2x_conn_resc(dev, i);
  2824. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  2825. atomic_dec(&cp->iscsi_conn);
  2826. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  2827. }
  2828. if (need_resched)
  2829. queue_delayed_work(cnic_wq, &cp->delete_task,
  2830. msecs_to_jiffies(10));
  2831. }
  2832. static int cnic_cm_open(struct cnic_dev *dev)
  2833. {
  2834. struct cnic_local *cp = dev->cnic_priv;
  2835. int err;
  2836. err = cnic_cm_alloc_mem(dev);
  2837. if (err)
  2838. return err;
  2839. err = cp->start_cm(dev);
  2840. if (err)
  2841. goto err_out;
  2842. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  2843. dev->cm_create = cnic_cm_create;
  2844. dev->cm_destroy = cnic_cm_destroy;
  2845. dev->cm_connect = cnic_cm_connect;
  2846. dev->cm_abort = cnic_cm_abort;
  2847. dev->cm_close = cnic_cm_close;
  2848. dev->cm_select_dev = cnic_cm_select_dev;
  2849. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2850. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2851. return 0;
  2852. err_out:
  2853. cnic_cm_free_mem(dev);
  2854. return err;
  2855. }
  2856. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2857. {
  2858. struct cnic_local *cp = dev->cnic_priv;
  2859. int i;
  2860. cp->stop_cm(dev);
  2861. if (!cp->csk_tbl)
  2862. return 0;
  2863. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2864. struct cnic_sock *csk = &cp->csk_tbl[i];
  2865. clear_bit(SK_F_INUSE, &csk->flags);
  2866. cnic_cm_cleanup(csk);
  2867. }
  2868. cnic_cm_free_mem(dev);
  2869. return 0;
  2870. }
  2871. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2872. {
  2873. u32 cid_addr;
  2874. int i;
  2875. cid_addr = GET_CID_ADDR(cid);
  2876. for (i = 0; i < CTX_SIZE; i += 4)
  2877. cnic_ctx_wr(dev, cid_addr, i, 0);
  2878. }
  2879. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2880. {
  2881. struct cnic_local *cp = dev->cnic_priv;
  2882. int ret = 0, i;
  2883. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2884. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2885. return 0;
  2886. for (i = 0; i < cp->ctx_blks; i++) {
  2887. int j;
  2888. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2889. u32 val;
  2890. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2891. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2892. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2893. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2894. (u64) cp->ctx_arr[i].mapping >> 32);
  2895. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2896. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2897. for (j = 0; j < 10; j++) {
  2898. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2899. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2900. break;
  2901. udelay(5);
  2902. }
  2903. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2904. ret = -EBUSY;
  2905. break;
  2906. }
  2907. }
  2908. return ret;
  2909. }
  2910. static void cnic_free_irq(struct cnic_dev *dev)
  2911. {
  2912. struct cnic_local *cp = dev->cnic_priv;
  2913. struct cnic_eth_dev *ethdev = cp->ethdev;
  2914. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2915. cp->disable_int_sync(dev);
  2916. tasklet_kill(&cp->cnic_irq_task);
  2917. free_irq(ethdev->irq_arr[0].vector, dev);
  2918. }
  2919. }
  2920. static int cnic_request_irq(struct cnic_dev *dev)
  2921. {
  2922. struct cnic_local *cp = dev->cnic_priv;
  2923. struct cnic_eth_dev *ethdev = cp->ethdev;
  2924. int err;
  2925. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  2926. if (err)
  2927. tasklet_disable(&cp->cnic_irq_task);
  2928. return err;
  2929. }
  2930. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2931. {
  2932. struct cnic_local *cp = dev->cnic_priv;
  2933. struct cnic_eth_dev *ethdev = cp->ethdev;
  2934. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2935. int err, i = 0;
  2936. int sblk_num = cp->status_blk_num;
  2937. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  2938. BNX2_HC_SB_CONFIG_1;
  2939. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  2940. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  2941. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  2942. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  2943. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  2944. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  2945. (unsigned long) dev);
  2946. err = cnic_request_irq(dev);
  2947. if (err)
  2948. return err;
  2949. while (cp->status_blk.bnx2->status_completion_producer_index &&
  2950. i < 10) {
  2951. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  2952. 1 << (11 + sblk_num));
  2953. udelay(10);
  2954. i++;
  2955. barrier();
  2956. }
  2957. if (cp->status_blk.bnx2->status_completion_producer_index) {
  2958. cnic_free_irq(dev);
  2959. goto failed;
  2960. }
  2961. } else {
  2962. struct status_block *sblk = cp->status_blk.gen;
  2963. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  2964. int i = 0;
  2965. while (sblk->status_completion_producer_index && i < 10) {
  2966. CNIC_WR(dev, BNX2_HC_COMMAND,
  2967. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2968. udelay(10);
  2969. i++;
  2970. barrier();
  2971. }
  2972. if (sblk->status_completion_producer_index)
  2973. goto failed;
  2974. }
  2975. return 0;
  2976. failed:
  2977. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  2978. return -EBUSY;
  2979. }
  2980. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  2981. {
  2982. struct cnic_local *cp = dev->cnic_priv;
  2983. struct cnic_eth_dev *ethdev = cp->ethdev;
  2984. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2985. return;
  2986. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2987. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2988. }
  2989. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  2990. {
  2991. struct cnic_local *cp = dev->cnic_priv;
  2992. struct cnic_eth_dev *ethdev = cp->ethdev;
  2993. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2994. return;
  2995. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2996. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2997. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  2998. synchronize_irq(ethdev->irq_arr[0].vector);
  2999. }
  3000. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3001. {
  3002. struct cnic_local *cp = dev->cnic_priv;
  3003. struct cnic_eth_dev *ethdev = cp->ethdev;
  3004. u32 cid_addr, tx_cid, sb_id;
  3005. u32 val, offset0, offset1, offset2, offset3;
  3006. int i;
  3007. struct tx_bd *txbd;
  3008. dma_addr_t buf_map;
  3009. struct status_block *s_blk = cp->status_blk.gen;
  3010. sb_id = cp->status_blk_num;
  3011. tx_cid = 20;
  3012. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3013. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3014. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3015. tx_cid = TX_TSS_CID + sb_id - 1;
  3016. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3017. (TX_TSS_CID << 7));
  3018. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3019. }
  3020. cp->tx_cons = *cp->tx_cons_ptr;
  3021. cid_addr = GET_CID_ADDR(tx_cid);
  3022. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3023. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3024. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3025. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3026. offset0 = BNX2_L2CTX_TYPE_XI;
  3027. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3028. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3029. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3030. } else {
  3031. cnic_init_context(dev, tx_cid);
  3032. cnic_init_context(dev, tx_cid + 1);
  3033. offset0 = BNX2_L2CTX_TYPE;
  3034. offset1 = BNX2_L2CTX_CMD_TYPE;
  3035. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3036. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3037. }
  3038. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3039. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3040. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3041. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3042. txbd = (struct tx_bd *) cp->l2_ring;
  3043. buf_map = cp->l2_buf_map;
  3044. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3045. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3046. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3047. }
  3048. val = (u64) cp->l2_ring_map >> 32;
  3049. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3050. txbd->tx_bd_haddr_hi = val;
  3051. val = (u64) cp->l2_ring_map & 0xffffffff;
  3052. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3053. txbd->tx_bd_haddr_lo = val;
  3054. }
  3055. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3056. {
  3057. struct cnic_local *cp = dev->cnic_priv;
  3058. struct cnic_eth_dev *ethdev = cp->ethdev;
  3059. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3060. int i;
  3061. struct rx_bd *rxbd;
  3062. struct status_block *s_blk = cp->status_blk.gen;
  3063. sb_id = cp->status_blk_num;
  3064. cnic_init_context(dev, 2);
  3065. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3066. coal_reg = BNX2_HC_COMMAND;
  3067. coal_val = CNIC_RD(dev, coal_reg);
  3068. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3069. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3070. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3071. coal_reg = BNX2_HC_COALESCE_NOW;
  3072. coal_val = 1 << (11 + sb_id);
  3073. }
  3074. i = 0;
  3075. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3076. CNIC_WR(dev, coal_reg, coal_val);
  3077. udelay(10);
  3078. i++;
  3079. barrier();
  3080. }
  3081. cp->rx_cons = *cp->rx_cons_ptr;
  3082. cid_addr = GET_CID_ADDR(2);
  3083. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3084. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3085. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3086. if (sb_id == 0)
  3087. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3088. else
  3089. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3090. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3091. rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
  3092. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3093. dma_addr_t buf_map;
  3094. int n = (i % cp->l2_rx_ring_size) + 1;
  3095. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3096. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3097. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3098. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3099. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3100. }
  3101. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  3102. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3103. rxbd->rx_bd_haddr_hi = val;
  3104. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3105. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3106. rxbd->rx_bd_haddr_lo = val;
  3107. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3108. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3109. }
  3110. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3111. {
  3112. struct kwqe *wqes[1], l2kwqe;
  3113. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3114. wqes[0] = &l2kwqe;
  3115. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  3116. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3117. KWQE_OPCODE_SHIFT) | 2;
  3118. dev->submit_kwqes(dev, wqes, 1);
  3119. }
  3120. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3121. {
  3122. struct cnic_local *cp = dev->cnic_priv;
  3123. u32 val;
  3124. val = cp->func << 2;
  3125. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3126. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3127. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3128. dev->mac_addr[0] = (u8) (val >> 8);
  3129. dev->mac_addr[1] = (u8) val;
  3130. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3131. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3132. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3133. dev->mac_addr[2] = (u8) (val >> 24);
  3134. dev->mac_addr[3] = (u8) (val >> 16);
  3135. dev->mac_addr[4] = (u8) (val >> 8);
  3136. dev->mac_addr[5] = (u8) val;
  3137. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3138. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3139. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3140. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3141. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3142. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3143. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3144. }
  3145. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3146. {
  3147. struct cnic_local *cp = dev->cnic_priv;
  3148. struct cnic_eth_dev *ethdev = cp->ethdev;
  3149. struct status_block *sblk = cp->status_blk.gen;
  3150. u32 val, kcq_cid_addr, kwq_cid_addr;
  3151. int err;
  3152. cnic_set_bnx2_mac(dev);
  3153. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3154. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3155. if (BCM_PAGE_BITS > 12)
  3156. val |= (12 - 8) << 4;
  3157. else
  3158. val |= (BCM_PAGE_BITS - 8) << 4;
  3159. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3160. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3161. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3162. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3163. err = cnic_setup_5709_context(dev, 1);
  3164. if (err)
  3165. return err;
  3166. cnic_init_context(dev, KWQ_CID);
  3167. cnic_init_context(dev, KCQ_CID);
  3168. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3169. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3170. cp->max_kwq_idx = MAX_KWQ_IDX;
  3171. cp->kwq_prod_idx = 0;
  3172. cp->kwq_con_idx = 0;
  3173. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3174. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3175. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3176. else
  3177. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3178. /* Initialize the kernel work queue context. */
  3179. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3180. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3181. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3182. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3183. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3184. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3185. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3186. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3187. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3188. val = (u32) cp->kwq_info.pgtbl_map;
  3189. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3190. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3191. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3192. cp->kcq1.sw_prod_idx = 0;
  3193. cp->kcq1.hw_prod_idx_ptr =
  3194. (u16 *) &sblk->status_completion_producer_index;
  3195. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3196. /* Initialize the kernel complete queue context. */
  3197. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3198. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3199. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3200. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3201. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3202. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3203. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3204. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3205. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3206. val = (u32) cp->kcq1.dma.pgtbl_map;
  3207. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3208. cp->int_num = 0;
  3209. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3210. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3211. u32 sb_id = cp->status_blk_num;
  3212. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3213. cp->kcq1.hw_prod_idx_ptr =
  3214. (u16 *) &msblk->status_completion_producer_index;
  3215. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3216. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3217. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3218. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3219. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3220. }
  3221. /* Enable Commnad Scheduler notification when we write to the
  3222. * host producer index of the kernel contexts. */
  3223. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3224. /* Enable Command Scheduler notification when we write to either
  3225. * the Send Queue or Receive Queue producer indexes of the kernel
  3226. * bypass contexts. */
  3227. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3228. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3229. /* Notify COM when the driver post an application buffer. */
  3230. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3231. /* Set the CP and COM doorbells. These two processors polls the
  3232. * doorbell for a non zero value before running. This must be done
  3233. * after setting up the kernel queue contexts. */
  3234. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3235. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3236. cnic_init_bnx2_tx_ring(dev);
  3237. cnic_init_bnx2_rx_ring(dev);
  3238. err = cnic_init_bnx2_irq(dev);
  3239. if (err) {
  3240. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3241. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3242. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3243. return err;
  3244. }
  3245. return 0;
  3246. }
  3247. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3248. {
  3249. struct cnic_local *cp = dev->cnic_priv;
  3250. struct cnic_eth_dev *ethdev = cp->ethdev;
  3251. u32 start_offset = ethdev->ctx_tbl_offset;
  3252. int i;
  3253. for (i = 0; i < cp->ctx_blks; i++) {
  3254. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3255. dma_addr_t map = ctx->mapping;
  3256. if (cp->ctx_align) {
  3257. unsigned long mask = cp->ctx_align - 1;
  3258. map = (map + mask) & ~mask;
  3259. }
  3260. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3261. }
  3262. }
  3263. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3264. {
  3265. struct cnic_local *cp = dev->cnic_priv;
  3266. struct cnic_eth_dev *ethdev = cp->ethdev;
  3267. int err = 0;
  3268. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3269. (unsigned long) dev);
  3270. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3271. err = cnic_request_irq(dev);
  3272. return err;
  3273. }
  3274. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3275. u16 sb_id, u8 sb_index,
  3276. u8 disable)
  3277. {
  3278. u32 addr = BAR_CSTRORM_INTMEM +
  3279. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3280. offsetof(struct hc_status_block_data_e1x, index_data) +
  3281. sizeof(struct hc_index_data)*sb_index +
  3282. offsetof(struct hc_index_data, flags);
  3283. u16 flags = CNIC_RD16(dev, addr);
  3284. /* clear and set */
  3285. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3286. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3287. HC_INDEX_DATA_HC_ENABLED);
  3288. CNIC_WR16(dev, addr, flags);
  3289. }
  3290. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3291. {
  3292. struct cnic_local *cp = dev->cnic_priv;
  3293. u8 sb_id = cp->status_blk_num;
  3294. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3295. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3296. offsetof(struct hc_status_block_data_e1x, index_data) +
  3297. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3298. offsetof(struct hc_index_data, timeout), 64 / 12);
  3299. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3300. }
  3301. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3302. {
  3303. }
  3304. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3305. struct client_init_ramrod_data *data)
  3306. {
  3307. struct cnic_local *cp = dev->cnic_priv;
  3308. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) cp->l2_ring;
  3309. dma_addr_t buf_map, ring_map = cp->l2_ring_map;
  3310. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3311. int port = CNIC_PORT(cp);
  3312. int i;
  3313. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3314. u32 val;
  3315. memset(txbd, 0, BCM_PAGE_SIZE);
  3316. buf_map = cp->l2_buf_map;
  3317. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3318. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3319. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3320. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3321. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3322. reg_bd->addr_hi = start_bd->addr_hi;
  3323. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3324. start_bd->nbytes = cpu_to_le16(0x10);
  3325. start_bd->nbd = cpu_to_le16(3);
  3326. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3327. start_bd->general_data = (UNICAST_ADDRESS <<
  3328. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3329. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3330. }
  3331. val = (u64) ring_map >> 32;
  3332. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3333. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3334. val = (u64) ring_map & 0xffffffff;
  3335. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3336. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3337. /* Other ramrod params */
  3338. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3339. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3340. /* reset xstorm per client statistics */
  3341. if (cli < MAX_STAT_COUNTER_ID) {
  3342. val = BAR_XSTRORM_INTMEM +
  3343. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3344. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3345. CNIC_WR(dev, val + i * 4, 0);
  3346. }
  3347. cp->tx_cons_ptr =
  3348. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3349. }
  3350. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3351. struct client_init_ramrod_data *data)
  3352. {
  3353. struct cnic_local *cp = dev->cnic_priv;
  3354. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (cp->l2_ring +
  3355. BCM_PAGE_SIZE);
  3356. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3357. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  3358. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3359. int i;
  3360. int port = CNIC_PORT(cp);
  3361. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3362. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3363. u32 val;
  3364. dma_addr_t ring_map = cp->l2_ring_map;
  3365. /* General data */
  3366. data->general.client_id = cli;
  3367. data->general.statistics_en_flg = 1;
  3368. data->general.statistics_counter_id = cli;
  3369. data->general.activate_flg = 1;
  3370. data->general.sp_client_id = cli;
  3371. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3372. dma_addr_t buf_map;
  3373. int n = (i % cp->l2_rx_ring_size) + 1;
  3374. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3375. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3376. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3377. }
  3378. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3379. rxbd->addr_hi = cpu_to_le32(val);
  3380. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3381. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3382. rxbd->addr_lo = cpu_to_le32(val);
  3383. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3384. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3385. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3386. rxcqe->addr_hi = cpu_to_le32(val);
  3387. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3388. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3389. rxcqe->addr_lo = cpu_to_le32(val);
  3390. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3391. /* Other ramrod params */
  3392. data->rx.client_qzone_id = cl_qzone_id;
  3393. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3394. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3395. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3396. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3397. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3398. data->rx.outer_vlan_removal_enable_flg = 1;
  3399. /* reset tstorm and ustorm per client statistics */
  3400. if (cli < MAX_STAT_COUNTER_ID) {
  3401. val = BAR_TSTRORM_INTMEM +
  3402. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3403. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3404. CNIC_WR(dev, val + i * 4, 0);
  3405. val = BAR_USTRORM_INTMEM +
  3406. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3407. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3408. CNIC_WR(dev, val + i * 4, 0);
  3409. }
  3410. cp->rx_cons_ptr =
  3411. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3412. }
  3413. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3414. {
  3415. struct cnic_local *cp = dev->cnic_priv;
  3416. u32 base, addr, val;
  3417. int port = CNIC_PORT(cp);
  3418. dev->max_iscsi_conn = 0;
  3419. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3420. if (base == 0)
  3421. return;
  3422. addr = BNX2X_SHMEM_ADDR(base,
  3423. dev_info.port_hw_config[port].iscsi_mac_upper);
  3424. val = CNIC_RD(dev, addr);
  3425. dev->mac_addr[0] = (u8) (val >> 8);
  3426. dev->mac_addr[1] = (u8) val;
  3427. addr = BNX2X_SHMEM_ADDR(base,
  3428. dev_info.port_hw_config[port].iscsi_mac_lower);
  3429. val = CNIC_RD(dev, addr);
  3430. dev->mac_addr[2] = (u8) (val >> 24);
  3431. dev->mac_addr[3] = (u8) (val >> 16);
  3432. dev->mac_addr[4] = (u8) (val >> 8);
  3433. dev->mac_addr[5] = (u8) val;
  3434. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3435. val = CNIC_RD(dev, addr);
  3436. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3437. u16 val16;
  3438. addr = BNX2X_SHMEM_ADDR(base,
  3439. drv_lic_key[port].max_iscsi_init_conn);
  3440. val16 = CNIC_RD16(dev, addr);
  3441. if (val16)
  3442. val16 ^= 0x1e1e;
  3443. dev->max_iscsi_conn = val16;
  3444. }
  3445. if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
  3446. int func = CNIC_FUNC(cp);
  3447. u32 mf_cfg_addr;
  3448. mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
  3449. addr = mf_cfg_addr +
  3450. offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
  3451. val = CNIC_RD(dev, addr);
  3452. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3453. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3454. addr = mf_cfg_addr +
  3455. offsetof(struct mf_cfg,
  3456. func_mf_config[func].config);
  3457. val = CNIC_RD(dev, addr);
  3458. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3459. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3460. dev->max_iscsi_conn = 0;
  3461. }
  3462. }
  3463. }
  3464. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3465. {
  3466. struct cnic_local *cp = dev->cnic_priv;
  3467. struct cnic_eth_dev *ethdev = cp->ethdev;
  3468. int func = CNIC_FUNC(cp), ret, i;
  3469. u32 pfid;
  3470. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3471. cp->pfid = func;
  3472. pfid = cp->pfid;
  3473. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3474. cp->iscsi_start_cid);
  3475. if (ret)
  3476. return -ENOMEM;
  3477. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  3478. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3479. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3480. cp->kcq1.sw_prod_idx = 0;
  3481. cp->kcq1.hw_prod_idx_ptr =
  3482. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3483. cp->kcq1.status_idx_ptr =
  3484. &sb->sb.running_index[SM_RX_ID];
  3485. cnic_get_bnx2x_iscsi_info(dev);
  3486. /* Only 1 EQ */
  3487. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3488. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3489. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  3490. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3491. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  3492. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3493. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3494. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  3495. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  3496. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3497. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  3498. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  3499. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3500. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  3501. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  3502. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3503. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  3504. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3505. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  3506. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3507. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  3508. HC_INDEX_ISCSI_EQ_CONS);
  3509. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3510. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3511. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  3512. cp->conn_buf_info.pgtbl[2 * i]);
  3513. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3514. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  3515. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3516. }
  3517. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3518. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  3519. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3520. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3521. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  3522. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3523. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3524. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  3525. cnic_setup_bnx2x_context(dev);
  3526. ret = cnic_init_bnx2x_irq(dev);
  3527. if (ret)
  3528. return ret;
  3529. return 0;
  3530. }
  3531. static void cnic_init_rings(struct cnic_dev *dev)
  3532. {
  3533. struct cnic_local *cp = dev->cnic_priv;
  3534. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3535. return;
  3536. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3537. cnic_init_bnx2_tx_ring(dev);
  3538. cnic_init_bnx2_rx_ring(dev);
  3539. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3540. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3541. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3542. u32 cl_qzone_id, type;
  3543. struct client_init_ramrod_data *data;
  3544. union l5cm_specific_data l5_data;
  3545. struct ustorm_eth_rx_producers rx_prods = {0};
  3546. u32 off, i;
  3547. rx_prods.bd_prod = 0;
  3548. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3549. barrier();
  3550. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3551. off = BAR_USTRORM_INTMEM +
  3552. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli);
  3553. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3554. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  3555. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3556. data = cp->l2_buf;
  3557. memset(data, 0, sizeof(*data));
  3558. cnic_init_bnx2x_tx_ring(dev, data);
  3559. cnic_init_bnx2x_rx_ring(dev, data);
  3560. l5_data.phy_address.lo = cp->l2_buf_map & 0xffffffff;
  3561. l5_data.phy_address.hi = (u64) cp->l2_buf_map >> 32;
  3562. type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3563. & SPE_HDR_CONN_TYPE;
  3564. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3565. SPE_HDR_FUNCTION_ID);
  3566. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3567. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3568. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3569. i = 0;
  3570. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3571. ++i < 10)
  3572. msleep(1);
  3573. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3574. netdev_err(dev->netdev,
  3575. "iSCSI CLIENT_SETUP did not complete\n");
  3576. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3577. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3578. }
  3579. }
  3580. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3581. {
  3582. struct cnic_local *cp = dev->cnic_priv;
  3583. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3584. return;
  3585. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3586. cnic_shutdown_bnx2_rx_ring(dev);
  3587. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3588. struct cnic_local *cp = dev->cnic_priv;
  3589. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3590. union l5cm_specific_data l5_data;
  3591. int i;
  3592. u32 type;
  3593. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3594. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3595. l5_data.phy_address.lo = cli;
  3596. l5_data.phy_address.hi = 0;
  3597. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  3598. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3599. i = 0;
  3600. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3601. ++i < 10)
  3602. msleep(1);
  3603. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3604. netdev_err(dev->netdev,
  3605. "iSCSI CLIENT_HALT did not complete\n");
  3606. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3607. memset(&l5_data, 0, sizeof(l5_data));
  3608. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3609. & SPE_HDR_CONN_TYPE;
  3610. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3611. SPE_HDR_FUNCTION_ID);
  3612. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  3613. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3614. msleep(10);
  3615. }
  3616. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3617. }
  3618. static int cnic_register_netdev(struct cnic_dev *dev)
  3619. {
  3620. struct cnic_local *cp = dev->cnic_priv;
  3621. struct cnic_eth_dev *ethdev = cp->ethdev;
  3622. int err;
  3623. if (!ethdev)
  3624. return -ENODEV;
  3625. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3626. return 0;
  3627. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3628. if (err)
  3629. netdev_err(dev->netdev, "register_cnic failed\n");
  3630. return err;
  3631. }
  3632. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3633. {
  3634. struct cnic_local *cp = dev->cnic_priv;
  3635. struct cnic_eth_dev *ethdev = cp->ethdev;
  3636. if (!ethdev)
  3637. return;
  3638. ethdev->drv_unregister_cnic(dev->netdev);
  3639. }
  3640. static int cnic_start_hw(struct cnic_dev *dev)
  3641. {
  3642. struct cnic_local *cp = dev->cnic_priv;
  3643. struct cnic_eth_dev *ethdev = cp->ethdev;
  3644. int err;
  3645. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3646. return -EALREADY;
  3647. dev->regview = ethdev->io_base;
  3648. cp->chip_id = ethdev->chip_id;
  3649. pci_dev_get(dev->pcidev);
  3650. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3651. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  3652. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3653. err = cp->alloc_resc(dev);
  3654. if (err) {
  3655. netdev_err(dev->netdev, "allocate resource failure\n");
  3656. goto err1;
  3657. }
  3658. err = cp->start_hw(dev);
  3659. if (err)
  3660. goto err1;
  3661. err = cnic_cm_open(dev);
  3662. if (err)
  3663. goto err1;
  3664. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3665. cp->enable_int(dev);
  3666. return 0;
  3667. err1:
  3668. cp->free_resc(dev);
  3669. pci_dev_put(dev->pcidev);
  3670. return err;
  3671. }
  3672. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3673. {
  3674. cnic_disable_bnx2_int_sync(dev);
  3675. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3676. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3677. cnic_init_context(dev, KWQ_CID);
  3678. cnic_init_context(dev, KCQ_CID);
  3679. cnic_setup_5709_context(dev, 0);
  3680. cnic_free_irq(dev);
  3681. cnic_free_resc(dev);
  3682. }
  3683. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3684. {
  3685. struct cnic_local *cp = dev->cnic_priv;
  3686. cnic_free_irq(dev);
  3687. *cp->kcq1.hw_prod_idx_ptr = 0;
  3688. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3689. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  3690. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  3691. cnic_free_resc(dev);
  3692. }
  3693. static void cnic_stop_hw(struct cnic_dev *dev)
  3694. {
  3695. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3696. struct cnic_local *cp = dev->cnic_priv;
  3697. int i = 0;
  3698. /* Need to wait for the ring shutdown event to complete
  3699. * before clearing the CNIC_UP flag.
  3700. */
  3701. while (cp->uio_dev != -1 && i < 15) {
  3702. msleep(100);
  3703. i++;
  3704. }
  3705. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3706. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3707. synchronize_rcu();
  3708. cnic_cm_shutdown(dev);
  3709. cp->stop_hw(dev);
  3710. pci_dev_put(dev->pcidev);
  3711. }
  3712. }
  3713. static void cnic_free_dev(struct cnic_dev *dev)
  3714. {
  3715. int i = 0;
  3716. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3717. msleep(100);
  3718. i++;
  3719. }
  3720. if (atomic_read(&dev->ref_count) != 0)
  3721. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  3722. netdev_info(dev->netdev, "Removed CNIC device\n");
  3723. dev_put(dev->netdev);
  3724. kfree(dev);
  3725. }
  3726. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3727. struct pci_dev *pdev)
  3728. {
  3729. struct cnic_dev *cdev;
  3730. struct cnic_local *cp;
  3731. int alloc_size;
  3732. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3733. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3734. if (cdev == NULL) {
  3735. netdev_err(dev, "allocate dev struct failure\n");
  3736. return NULL;
  3737. }
  3738. cdev->netdev = dev;
  3739. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3740. cdev->register_device = cnic_register_device;
  3741. cdev->unregister_device = cnic_unregister_device;
  3742. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3743. cp = cdev->cnic_priv;
  3744. cp->dev = cdev;
  3745. cp->uio_dev = -1;
  3746. cp->l2_single_buf_size = 0x400;
  3747. cp->l2_rx_ring_size = 3;
  3748. spin_lock_init(&cp->cnic_ulp_lock);
  3749. netdev_info(dev, "Added CNIC device\n");
  3750. return cdev;
  3751. }
  3752. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3753. {
  3754. struct pci_dev *pdev;
  3755. struct cnic_dev *cdev;
  3756. struct cnic_local *cp;
  3757. struct cnic_eth_dev *ethdev = NULL;
  3758. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3759. probe = symbol_get(bnx2_cnic_probe);
  3760. if (probe) {
  3761. ethdev = (*probe)(dev);
  3762. symbol_put(bnx2_cnic_probe);
  3763. }
  3764. if (!ethdev)
  3765. return NULL;
  3766. pdev = ethdev->pdev;
  3767. if (!pdev)
  3768. return NULL;
  3769. dev_hold(dev);
  3770. pci_dev_get(pdev);
  3771. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3772. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3773. u8 rev;
  3774. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3775. if (rev < 0x10) {
  3776. pci_dev_put(pdev);
  3777. goto cnic_err;
  3778. }
  3779. }
  3780. pci_dev_put(pdev);
  3781. cdev = cnic_alloc_dev(dev, pdev);
  3782. if (cdev == NULL)
  3783. goto cnic_err;
  3784. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3785. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3786. cp = cdev->cnic_priv;
  3787. cp->ethdev = ethdev;
  3788. cdev->pcidev = pdev;
  3789. cp->cnic_ops = &cnic_bnx2_ops;
  3790. cp->start_hw = cnic_start_bnx2_hw;
  3791. cp->stop_hw = cnic_stop_bnx2_hw;
  3792. cp->setup_pgtbl = cnic_setup_page_tbl;
  3793. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3794. cp->free_resc = cnic_free_resc;
  3795. cp->start_cm = cnic_cm_init_bnx2_hw;
  3796. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3797. cp->enable_int = cnic_enable_bnx2_int;
  3798. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3799. cp->close_conn = cnic_close_bnx2_conn;
  3800. cp->next_idx = cnic_bnx2_next_idx;
  3801. cp->hw_idx = cnic_bnx2_hw_idx;
  3802. return cdev;
  3803. cnic_err:
  3804. dev_put(dev);
  3805. return NULL;
  3806. }
  3807. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3808. {
  3809. struct pci_dev *pdev;
  3810. struct cnic_dev *cdev;
  3811. struct cnic_local *cp;
  3812. struct cnic_eth_dev *ethdev = NULL;
  3813. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3814. probe = symbol_get(bnx2x_cnic_probe);
  3815. if (probe) {
  3816. ethdev = (*probe)(dev);
  3817. symbol_put(bnx2x_cnic_probe);
  3818. }
  3819. if (!ethdev)
  3820. return NULL;
  3821. pdev = ethdev->pdev;
  3822. if (!pdev)
  3823. return NULL;
  3824. dev_hold(dev);
  3825. cdev = cnic_alloc_dev(dev, pdev);
  3826. if (cdev == NULL) {
  3827. dev_put(dev);
  3828. return NULL;
  3829. }
  3830. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3831. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3832. cp = cdev->cnic_priv;
  3833. cp->ethdev = ethdev;
  3834. cdev->pcidev = pdev;
  3835. cp->cnic_ops = &cnic_bnx2x_ops;
  3836. cp->start_hw = cnic_start_bnx2x_hw;
  3837. cp->stop_hw = cnic_stop_bnx2x_hw;
  3838. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3839. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3840. cp->free_resc = cnic_free_resc;
  3841. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3842. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3843. cp->enable_int = cnic_enable_bnx2x_int;
  3844. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3845. cp->ack_int = cnic_ack_bnx2x_msix;
  3846. cp->close_conn = cnic_close_bnx2x_conn;
  3847. cp->next_idx = cnic_bnx2x_next_idx;
  3848. cp->hw_idx = cnic_bnx2x_hw_idx;
  3849. return cdev;
  3850. }
  3851. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3852. {
  3853. struct ethtool_drvinfo drvinfo;
  3854. struct cnic_dev *cdev = NULL;
  3855. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3856. memset(&drvinfo, 0, sizeof(drvinfo));
  3857. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3858. if (!strcmp(drvinfo.driver, "bnx2"))
  3859. cdev = init_bnx2_cnic(dev);
  3860. if (!strcmp(drvinfo.driver, "bnx2x"))
  3861. cdev = init_bnx2x_cnic(dev);
  3862. if (cdev) {
  3863. write_lock(&cnic_dev_lock);
  3864. list_add(&cdev->list, &cnic_dev_list);
  3865. write_unlock(&cnic_dev_lock);
  3866. }
  3867. }
  3868. return cdev;
  3869. }
  3870. /**
  3871. * netdev event handler
  3872. */
  3873. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3874. void *ptr)
  3875. {
  3876. struct net_device *netdev = ptr;
  3877. struct cnic_dev *dev;
  3878. int if_type;
  3879. int new_dev = 0;
  3880. dev = cnic_from_netdev(netdev);
  3881. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3882. /* Check for the hot-plug device */
  3883. dev = is_cnic_dev(netdev);
  3884. if (dev) {
  3885. new_dev = 1;
  3886. cnic_hold(dev);
  3887. }
  3888. }
  3889. if (dev) {
  3890. struct cnic_local *cp = dev->cnic_priv;
  3891. if (new_dev)
  3892. cnic_ulp_init(dev);
  3893. else if (event == NETDEV_UNREGISTER)
  3894. cnic_ulp_exit(dev);
  3895. if (event == NETDEV_UP) {
  3896. if (cnic_register_netdev(dev) != 0) {
  3897. cnic_put(dev);
  3898. goto done;
  3899. }
  3900. if (!cnic_start_hw(dev))
  3901. cnic_ulp_start(dev);
  3902. }
  3903. rcu_read_lock();
  3904. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  3905. struct cnic_ulp_ops *ulp_ops;
  3906. void *ctx;
  3907. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  3908. if (!ulp_ops || !ulp_ops->indicate_netevent)
  3909. continue;
  3910. ctx = cp->ulp_handle[if_type];
  3911. ulp_ops->indicate_netevent(ctx, event);
  3912. }
  3913. rcu_read_unlock();
  3914. if (event == NETDEV_GOING_DOWN) {
  3915. cnic_ulp_stop(dev);
  3916. cnic_stop_hw(dev);
  3917. cnic_unregister_netdev(dev);
  3918. } else if (event == NETDEV_UNREGISTER) {
  3919. write_lock(&cnic_dev_lock);
  3920. list_del_init(&dev->list);
  3921. write_unlock(&cnic_dev_lock);
  3922. cnic_put(dev);
  3923. cnic_free_dev(dev);
  3924. goto done;
  3925. }
  3926. cnic_put(dev);
  3927. }
  3928. done:
  3929. return NOTIFY_DONE;
  3930. }
  3931. static struct notifier_block cnic_netdev_notifier = {
  3932. .notifier_call = cnic_netdev_event
  3933. };
  3934. static void cnic_release(void)
  3935. {
  3936. struct cnic_dev *dev;
  3937. while (!list_empty(&cnic_dev_list)) {
  3938. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  3939. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3940. cnic_ulp_stop(dev);
  3941. cnic_stop_hw(dev);
  3942. }
  3943. cnic_ulp_exit(dev);
  3944. cnic_unregister_netdev(dev);
  3945. list_del_init(&dev->list);
  3946. cnic_free_dev(dev);
  3947. }
  3948. }
  3949. static int __init cnic_init(void)
  3950. {
  3951. int rc = 0;
  3952. pr_info("%s", version);
  3953. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  3954. if (rc) {
  3955. cnic_release();
  3956. return rc;
  3957. }
  3958. cnic_wq = create_singlethread_workqueue("cnic_wq");
  3959. if (!cnic_wq) {
  3960. cnic_release();
  3961. unregister_netdevice_notifier(&cnic_netdev_notifier);
  3962. return -ENOMEM;
  3963. }
  3964. return 0;
  3965. }
  3966. static void __exit cnic_exit(void)
  3967. {
  3968. unregister_netdevice_notifier(&cnic_netdev_notifier);
  3969. cnic_release();
  3970. destroy_workqueue(cnic_wq);
  3971. }
  3972. module_init(cnic_init);
  3973. module_exit(cnic_exit);