lpd270.c 12 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/lpd270.c
  3. *
  4. * Support for the LogicPD PXA270 Card Engine.
  5. * Derived from the mainstone code, which carries these notices:
  6. *
  7. * Author: Nicolas Pitre
  8. * Created: Nov 05, 2002
  9. * Copyright: MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/sysdev.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/sched.h>
  20. #include <linux/bitops.h>
  21. #include <linux/fb.h>
  22. #include <linux/ioport.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <linux/pwm_backlight.h>
  26. #include <asm/types.h>
  27. #include <asm/setup.h>
  28. #include <asm/memory.h>
  29. #include <asm/mach-types.h>
  30. #include <mach/hardware.h>
  31. #include <asm/irq.h>
  32. #include <asm/sizes.h>
  33. #include <asm/mach/arch.h>
  34. #include <asm/mach/map.h>
  35. #include <asm/mach/irq.h>
  36. #include <asm/mach/flash.h>
  37. #include <mach/pxa-regs.h>
  38. #include <mach/pxa2xx-regs.h>
  39. #include <mach/mfp-pxa27x.h>
  40. #include <mach/lpd270.h>
  41. #include <mach/audio.h>
  42. #include <mach/pxafb.h>
  43. #include <mach/mmc.h>
  44. #include <mach/irda.h>
  45. #include <mach/ohci.h>
  46. #include "generic.h"
  47. #include "devices.h"
  48. static unsigned long lpd270_pin_config[] __initdata = {
  49. /* Chip Selects */
  50. GPIO15_nCS_1, /* Mainboard Flash */
  51. GPIO78_nCS_2, /* CPLD + Ethernet */
  52. /* LCD - 16bpp Active TFT */
  53. GPIO58_LCD_LDD_0,
  54. GPIO59_LCD_LDD_1,
  55. GPIO60_LCD_LDD_2,
  56. GPIO61_LCD_LDD_3,
  57. GPIO62_LCD_LDD_4,
  58. GPIO63_LCD_LDD_5,
  59. GPIO64_LCD_LDD_6,
  60. GPIO65_LCD_LDD_7,
  61. GPIO66_LCD_LDD_8,
  62. GPIO67_LCD_LDD_9,
  63. GPIO68_LCD_LDD_10,
  64. GPIO69_LCD_LDD_11,
  65. GPIO70_LCD_LDD_12,
  66. GPIO71_LCD_LDD_13,
  67. GPIO72_LCD_LDD_14,
  68. GPIO73_LCD_LDD_15,
  69. GPIO74_LCD_FCLK,
  70. GPIO75_LCD_LCLK,
  71. GPIO76_LCD_PCLK,
  72. GPIO77_LCD_BIAS,
  73. GPIO16_PWM0_OUT, /* Backlight */
  74. /* USB Host */
  75. GPIO88_USBH1_PWR,
  76. GPIO89_USBH1_PEN,
  77. /* AC97 */
  78. GPIO45_AC97_SYSCLK,
  79. GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
  80. };
  81. static unsigned int lpd270_irq_enabled;
  82. static void lpd270_mask_irq(unsigned int irq)
  83. {
  84. int lpd270_irq = irq - LPD270_IRQ(0);
  85. __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
  86. lpd270_irq_enabled &= ~(1 << lpd270_irq);
  87. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  88. }
  89. static void lpd270_unmask_irq(unsigned int irq)
  90. {
  91. int lpd270_irq = irq - LPD270_IRQ(0);
  92. lpd270_irq_enabled |= 1 << lpd270_irq;
  93. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  94. }
  95. static struct irq_chip lpd270_irq_chip = {
  96. .name = "CPLD",
  97. .ack = lpd270_mask_irq,
  98. .mask = lpd270_mask_irq,
  99. .unmask = lpd270_unmask_irq,
  100. };
  101. static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
  102. {
  103. unsigned long pending;
  104. pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
  105. do {
  106. GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
  107. if (likely(pending)) {
  108. irq = LPD270_IRQ(0) + __ffs(pending);
  109. desc = irq_desc + irq;
  110. desc_handle_irq(irq, desc);
  111. pending = __raw_readw(LPD270_INT_STATUS) &
  112. lpd270_irq_enabled;
  113. }
  114. } while (pending);
  115. }
  116. static void __init lpd270_init_irq(void)
  117. {
  118. int irq;
  119. pxa27x_init_irq();
  120. __raw_writew(0, LPD270_INT_MASK);
  121. __raw_writew(0, LPD270_INT_STATUS);
  122. /* setup extra LogicPD PXA270 irqs */
  123. for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
  124. set_irq_chip(irq, &lpd270_irq_chip);
  125. set_irq_handler(irq, handle_level_irq);
  126. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  127. }
  128. set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
  129. set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
  130. }
  131. #ifdef CONFIG_PM
  132. static int lpd270_irq_resume(struct sys_device *dev)
  133. {
  134. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  135. return 0;
  136. }
  137. static struct sysdev_class lpd270_irq_sysclass = {
  138. .name = "cpld_irq",
  139. .resume = lpd270_irq_resume,
  140. };
  141. static struct sys_device lpd270_irq_device = {
  142. .cls = &lpd270_irq_sysclass,
  143. };
  144. static int __init lpd270_irq_device_init(void)
  145. {
  146. int ret = -ENODEV;
  147. if (machine_is_logicpd_pxa270()) {
  148. ret = sysdev_class_register(&lpd270_irq_sysclass);
  149. if (ret == 0)
  150. ret = sysdev_register(&lpd270_irq_device);
  151. }
  152. return ret;
  153. }
  154. device_initcall(lpd270_irq_device_init);
  155. #endif
  156. static struct resource smc91x_resources[] = {
  157. [0] = {
  158. .start = LPD270_ETH_PHYS,
  159. .end = (LPD270_ETH_PHYS + 0xfffff),
  160. .flags = IORESOURCE_MEM,
  161. },
  162. [1] = {
  163. .start = LPD270_ETHERNET_IRQ,
  164. .end = LPD270_ETHERNET_IRQ,
  165. .flags = IORESOURCE_IRQ,
  166. },
  167. };
  168. static struct platform_device smc91x_device = {
  169. .name = "smc91x",
  170. .id = 0,
  171. .num_resources = ARRAY_SIZE(smc91x_resources),
  172. .resource = smc91x_resources,
  173. };
  174. static struct resource lpd270_flash_resources[] = {
  175. [0] = {
  176. .start = PXA_CS0_PHYS,
  177. .end = PXA_CS0_PHYS + SZ_64M - 1,
  178. .flags = IORESOURCE_MEM,
  179. },
  180. [1] = {
  181. .start = PXA_CS1_PHYS,
  182. .end = PXA_CS1_PHYS + SZ_64M - 1,
  183. .flags = IORESOURCE_MEM,
  184. },
  185. };
  186. static struct mtd_partition lpd270_flash0_partitions[] = {
  187. {
  188. .name = "Bootloader",
  189. .size = 0x00040000,
  190. .offset = 0,
  191. .mask_flags = MTD_WRITEABLE /* force read-only */
  192. }, {
  193. .name = "Kernel",
  194. .size = 0x00400000,
  195. .offset = 0x00040000,
  196. }, {
  197. .name = "Filesystem",
  198. .size = MTDPART_SIZ_FULL,
  199. .offset = 0x00440000
  200. },
  201. };
  202. static struct flash_platform_data lpd270_flash_data[2] = {
  203. {
  204. .name = "processor-flash",
  205. .map_name = "cfi_probe",
  206. .parts = lpd270_flash0_partitions,
  207. .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
  208. }, {
  209. .name = "mainboard-flash",
  210. .map_name = "cfi_probe",
  211. .parts = NULL,
  212. .nr_parts = 0,
  213. }
  214. };
  215. static struct platform_device lpd270_flash_device[2] = {
  216. {
  217. .name = "pxa2xx-flash",
  218. .id = 0,
  219. .dev = {
  220. .platform_data = &lpd270_flash_data[0],
  221. },
  222. .resource = &lpd270_flash_resources[0],
  223. .num_resources = 1,
  224. }, {
  225. .name = "pxa2xx-flash",
  226. .id = 1,
  227. .dev = {
  228. .platform_data = &lpd270_flash_data[1],
  229. },
  230. .resource = &lpd270_flash_resources[1],
  231. .num_resources = 1,
  232. },
  233. };
  234. static struct platform_pwm_backlight_data lpd270_backlight_data = {
  235. .pwm_id = 0,
  236. .max_brightness = 1,
  237. .dft_brightness = 1,
  238. .pwm_period_ns = 78770,
  239. };
  240. static struct platform_device lpd270_backlight_device = {
  241. .name = "pwm-backlight",
  242. .dev = {
  243. .parent = &pxa27x_device_pwm0.dev,
  244. .platform_data = &lpd270_backlight_data,
  245. },
  246. };
  247. /* 5.7" TFT QVGA (LoLo display number 1) */
  248. static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
  249. .pixclock = 150000,
  250. .xres = 320,
  251. .yres = 240,
  252. .bpp = 16,
  253. .hsync_len = 0x14,
  254. .left_margin = 0x28,
  255. .right_margin = 0x0a,
  256. .vsync_len = 0x02,
  257. .upper_margin = 0x08,
  258. .lower_margin = 0x14,
  259. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  260. };
  261. static struct pxafb_mach_info sharp_lq057q3dc02 = {
  262. .modes = &sharp_lq057q3dc02_mode,
  263. .num_modes = 1,
  264. .lccr0 = 0x07800080,
  265. .lccr3 = 0x00400000,
  266. };
  267. /* 12.1" TFT SVGA (LoLo display number 2) */
  268. static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
  269. .pixclock = 50000,
  270. .xres = 800,
  271. .yres = 600,
  272. .bpp = 16,
  273. .hsync_len = 0x05,
  274. .left_margin = 0x52,
  275. .right_margin = 0x05,
  276. .vsync_len = 0x04,
  277. .upper_margin = 0x14,
  278. .lower_margin = 0x0a,
  279. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  280. };
  281. static struct pxafb_mach_info sharp_lq121s1dg31 = {
  282. .modes = &sharp_lq121s1dg31_mode,
  283. .num_modes = 1,
  284. .lccr0 = 0x07800080,
  285. .lccr3 = 0x00400000,
  286. };
  287. /* 3.6" TFT QVGA (LoLo display number 3) */
  288. static struct pxafb_mode_info sharp_lq036q1da01_mode = {
  289. .pixclock = 150000,
  290. .xres = 320,
  291. .yres = 240,
  292. .bpp = 16,
  293. .hsync_len = 0x0e,
  294. .left_margin = 0x04,
  295. .right_margin = 0x0a,
  296. .vsync_len = 0x03,
  297. .upper_margin = 0x03,
  298. .lower_margin = 0x03,
  299. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  300. };
  301. static struct pxafb_mach_info sharp_lq036q1da01 = {
  302. .modes = &sharp_lq036q1da01_mode,
  303. .num_modes = 1,
  304. .lccr0 = 0x07800080,
  305. .lccr3 = 0x00400000,
  306. };
  307. /* 6.4" TFT VGA (LoLo display number 5) */
  308. static struct pxafb_mode_info sharp_lq64d343_mode = {
  309. .pixclock = 25000,
  310. .xres = 640,
  311. .yres = 480,
  312. .bpp = 16,
  313. .hsync_len = 0x31,
  314. .left_margin = 0x89,
  315. .right_margin = 0x19,
  316. .vsync_len = 0x12,
  317. .upper_margin = 0x22,
  318. .lower_margin = 0x00,
  319. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  320. };
  321. static struct pxafb_mach_info sharp_lq64d343 = {
  322. .modes = &sharp_lq64d343_mode,
  323. .num_modes = 1,
  324. .lccr0 = 0x07800080,
  325. .lccr3 = 0x00400000,
  326. };
  327. /* 10.4" TFT VGA (LoLo display number 7) */
  328. static struct pxafb_mode_info sharp_lq10d368_mode = {
  329. .pixclock = 25000,
  330. .xres = 640,
  331. .yres = 480,
  332. .bpp = 16,
  333. .hsync_len = 0x31,
  334. .left_margin = 0x89,
  335. .right_margin = 0x19,
  336. .vsync_len = 0x12,
  337. .upper_margin = 0x22,
  338. .lower_margin = 0x00,
  339. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  340. };
  341. static struct pxafb_mach_info sharp_lq10d368 = {
  342. .modes = &sharp_lq10d368_mode,
  343. .num_modes = 1,
  344. .lccr0 = 0x07800080,
  345. .lccr3 = 0x00400000,
  346. };
  347. /* 3.5" TFT QVGA (LoLo display number 8) */
  348. static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
  349. .pixclock = 150000,
  350. .xres = 240,
  351. .yres = 320,
  352. .bpp = 16,
  353. .hsync_len = 0x0e,
  354. .left_margin = 0x0a,
  355. .right_margin = 0x0a,
  356. .vsync_len = 0x03,
  357. .upper_margin = 0x05,
  358. .lower_margin = 0x14,
  359. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  360. };
  361. static struct pxafb_mach_info sharp_lq035q7db02_20 = {
  362. .modes = &sharp_lq035q7db02_20_mode,
  363. .num_modes = 1,
  364. .lccr0 = 0x07800080,
  365. .lccr3 = 0x00400000,
  366. };
  367. static struct pxafb_mach_info *lpd270_lcd_to_use;
  368. static int __init lpd270_set_lcd(char *str)
  369. {
  370. if (!strnicmp(str, "lq057q3dc02", 11)) {
  371. lpd270_lcd_to_use = &sharp_lq057q3dc02;
  372. } else if (!strnicmp(str, "lq121s1dg31", 11)) {
  373. lpd270_lcd_to_use = &sharp_lq121s1dg31;
  374. } else if (!strnicmp(str, "lq036q1da01", 11)) {
  375. lpd270_lcd_to_use = &sharp_lq036q1da01;
  376. } else if (!strnicmp(str, "lq64d343", 8)) {
  377. lpd270_lcd_to_use = &sharp_lq64d343;
  378. } else if (!strnicmp(str, "lq10d368", 8)) {
  379. lpd270_lcd_to_use = &sharp_lq10d368;
  380. } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
  381. lpd270_lcd_to_use = &sharp_lq035q7db02_20;
  382. } else {
  383. printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
  384. }
  385. return 1;
  386. }
  387. __setup("lcd=", lpd270_set_lcd);
  388. static struct platform_device *platform_devices[] __initdata = {
  389. &smc91x_device,
  390. &lpd270_backlight_device,
  391. &lpd270_flash_device[0],
  392. &lpd270_flash_device[1],
  393. };
  394. static int lpd270_ohci_init(struct device *dev)
  395. {
  396. /* Set the Power Control Polarity Low and Power Sense
  397. Polarity Low to active low. */
  398. UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
  399. ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
  400. return 0;
  401. }
  402. static struct pxaohci_platform_data lpd270_ohci_platform_data = {
  403. .port_mode = PMM_PERPORT_MODE,
  404. .init = lpd270_ohci_init,
  405. };
  406. static void __init lpd270_init(void)
  407. {
  408. pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
  409. lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
  410. lpd270_flash_data[1].width = 4;
  411. /*
  412. * System bus arbiter setting:
  413. * - Core_Park
  414. * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
  415. */
  416. ARB_CNTRL = ARB_CORE_PARK | 0x234;
  417. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  418. pxa_set_ac97_info(NULL);
  419. if (lpd270_lcd_to_use != NULL)
  420. set_pxa_fb_info(lpd270_lcd_to_use);
  421. pxa_set_ohci_info(&lpd270_ohci_platform_data);
  422. }
  423. static struct map_desc lpd270_io_desc[] __initdata = {
  424. {
  425. .virtual = LPD270_CPLD_VIRT,
  426. .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
  427. .length = LPD270_CPLD_SIZE,
  428. .type = MT_DEVICE,
  429. },
  430. };
  431. static void __init lpd270_map_io(void)
  432. {
  433. pxa_map_io();
  434. iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
  435. /* for use I SRAM as framebuffer. */
  436. PSLR |= 0x00000F04;
  437. PCFR = 0x00000066;
  438. }
  439. MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
  440. /* Maintainer: Peter Barada */
  441. .phys_io = 0x40000000,
  442. .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
  443. .boot_params = 0xa0000100,
  444. .map_io = lpd270_map_io,
  445. .init_irq = lpd270_init_irq,
  446. .timer = &pxa_timer,
  447. .init_machine = lpd270_init,
  448. MACHINE_END