i915_drv.c 17 KB

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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #include <linux/device.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include <linux/console.h>
  35. #include "drm_crtc_helper.h"
  36. static int i915_modeset = -1;
  37. module_param_named(modeset, i915_modeset, int, 0400);
  38. unsigned int i915_fbpercrtc = 0;
  39. module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  40. unsigned int i915_powersave = 1;
  41. module_param_named(powersave, i915_powersave, int, 0400);
  42. unsigned int i915_lvds_downclock = 0;
  43. module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  44. static struct drm_driver driver;
  45. extern int intel_agp_enabled;
  46. #define INTEL_VGA_DEVICE(id, info) { \
  47. .class = PCI_CLASS_DISPLAY_VGA << 8, \
  48. .class_mask = 0xffff00, \
  49. .vendor = 0x8086, \
  50. .device = id, \
  51. .subvendor = PCI_ANY_ID, \
  52. .subdevice = PCI_ANY_ID, \
  53. .driver_data = (unsigned long) info }
  54. const static struct intel_device_info intel_i830_info = {
  55. .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  56. };
  57. const static struct intel_device_info intel_845g_info = {
  58. .is_i8xx = 1,
  59. };
  60. const static struct intel_device_info intel_i85x_info = {
  61. .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  62. };
  63. const static struct intel_device_info intel_i865g_info = {
  64. .is_i8xx = 1,
  65. };
  66. const static struct intel_device_info intel_i915g_info = {
  67. .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
  68. };
  69. const static struct intel_device_info intel_i915gm_info = {
  70. .is_i9xx = 1, .is_mobile = 1,
  71. .cursor_needs_physical = 1,
  72. };
  73. const static struct intel_device_info intel_i945g_info = {
  74. .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
  75. };
  76. const static struct intel_device_info intel_i945gm_info = {
  77. .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
  78. .has_hotplug = 1, .cursor_needs_physical = 1,
  79. };
  80. const static struct intel_device_info intel_i965g_info = {
  81. .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
  82. };
  83. const static struct intel_device_info intel_i965gm_info = {
  84. .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
  85. .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
  86. .has_hotplug = 1,
  87. };
  88. const static struct intel_device_info intel_g33_info = {
  89. .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  90. .has_hotplug = 1,
  91. };
  92. const static struct intel_device_info intel_g45_info = {
  93. .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  94. .has_pipe_cxsr = 1,
  95. .has_hotplug = 1,
  96. };
  97. const static struct intel_device_info intel_gm45_info = {
  98. .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
  99. .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
  100. .has_pipe_cxsr = 1,
  101. .has_hotplug = 1,
  102. };
  103. const static struct intel_device_info intel_pineview_info = {
  104. .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
  105. .need_gfx_hws = 1,
  106. .has_hotplug = 1,
  107. };
  108. const static struct intel_device_info intel_ironlake_d_info = {
  109. .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  110. .has_pipe_cxsr = 1,
  111. .has_hotplug = 1,
  112. };
  113. const static struct intel_device_info intel_ironlake_m_info = {
  114. .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
  115. .need_gfx_hws = 1, .has_rc6 = 1,
  116. .has_hotplug = 1,
  117. };
  118. const static struct intel_device_info intel_sandybridge_d_info = {
  119. .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  120. .has_hotplug = 1, .is_gen6 = 1,
  121. };
  122. const static struct intel_device_info intel_sandybridge_m_info = {
  123. .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  124. .has_hotplug = 1, .is_gen6 = 1,
  125. };
  126. const static struct pci_device_id pciidlist[] = {
  127. INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
  128. INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
  129. INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
  130. INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
  131. INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
  132. INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
  133. INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
  134. INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
  135. INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
  136. INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
  137. INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
  138. INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
  139. INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
  140. INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
  141. INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
  142. INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
  143. INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
  144. INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
  145. INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
  146. INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
  147. INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
  148. INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
  149. INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
  150. INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
  151. INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
  152. INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
  153. INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  154. INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  155. INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  156. INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  157. INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  158. INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  159. {0, 0, 0}
  160. };
  161. #if defined(CONFIG_DRM_I915_KMS)
  162. MODULE_DEVICE_TABLE(pci, pciidlist);
  163. #endif
  164. #define INTEL_PCH_DEVICE_ID_MASK 0xff00
  165. #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
  166. void intel_detect_pch (struct drm_device *dev)
  167. {
  168. struct drm_i915_private *dev_priv = dev->dev_private;
  169. struct pci_dev *pch;
  170. /*
  171. * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  172. * make graphics device passthrough work easy for VMM, that only
  173. * need to expose ISA bridge to let driver know the real hardware
  174. * underneath. This is a requirement from virtualization team.
  175. */
  176. pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  177. if (pch) {
  178. if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  179. int id;
  180. id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  181. if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  182. dev_priv->pch_type = PCH_CPT;
  183. DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  184. }
  185. }
  186. pci_dev_put(pch);
  187. }
  188. }
  189. static int i915_drm_freeze(struct drm_device *dev)
  190. {
  191. struct drm_i915_private *dev_priv = dev->dev_private;
  192. pci_save_state(dev->pdev);
  193. /* If KMS is active, we do the leavevt stuff here */
  194. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  195. int error = i915_gem_idle(dev);
  196. if (error) {
  197. dev_err(&dev->pdev->dev,
  198. "GEM idle failed, resume might fail\n");
  199. return error;
  200. }
  201. drm_irq_uninstall(dev);
  202. }
  203. i915_save_state(dev);
  204. intel_opregion_free(dev, 1);
  205. /* Modeset on resume, not lid events */
  206. dev_priv->modeset_on_lid = 0;
  207. return 0;
  208. }
  209. int i915_suspend(struct drm_device *dev, pm_message_t state)
  210. {
  211. int error;
  212. if (!dev || !dev->dev_private) {
  213. DRM_ERROR("dev: %p\n", dev);
  214. DRM_ERROR("DRM not initialized, aborting suspend.\n");
  215. return -ENODEV;
  216. }
  217. if (state.event == PM_EVENT_PRETHAW)
  218. return 0;
  219. error = i915_drm_freeze(dev);
  220. if (error)
  221. return error;
  222. if (state.event == PM_EVENT_SUSPEND) {
  223. /* Shut down the device */
  224. pci_disable_device(dev->pdev);
  225. pci_set_power_state(dev->pdev, PCI_D3hot);
  226. }
  227. return 0;
  228. }
  229. static int i915_drm_thaw(struct drm_device *dev)
  230. {
  231. struct drm_i915_private *dev_priv = dev->dev_private;
  232. int error = 0;
  233. i915_restore_state(dev);
  234. intel_opregion_init(dev, 1);
  235. /* KMS EnterVT equivalent */
  236. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  237. mutex_lock(&dev->struct_mutex);
  238. dev_priv->mm.suspended = 0;
  239. error = i915_gem_init_ringbuffer(dev);
  240. mutex_unlock(&dev->struct_mutex);
  241. drm_irq_install(dev);
  242. /* Resume the modeset for every activated CRTC */
  243. drm_helper_resume_force_mode(dev);
  244. }
  245. dev_priv->modeset_on_lid = 0;
  246. return error;
  247. }
  248. int i915_resume(struct drm_device *dev)
  249. {
  250. if (pci_enable_device(dev->pdev))
  251. return -EIO;
  252. pci_set_master(dev->pdev);
  253. return i915_drm_thaw(dev);
  254. }
  255. /**
  256. * i965_reset - reset chip after a hang
  257. * @dev: drm device to reset
  258. * @flags: reset domains
  259. *
  260. * Reset the chip. Useful if a hang is detected. Returns zero on successful
  261. * reset or otherwise an error code.
  262. *
  263. * Procedure is fairly simple:
  264. * - reset the chip using the reset reg
  265. * - re-init context state
  266. * - re-init hardware status page
  267. * - re-init ring buffer
  268. * - re-init interrupt state
  269. * - re-init display
  270. */
  271. int i965_reset(struct drm_device *dev, u8 flags)
  272. {
  273. drm_i915_private_t *dev_priv = dev->dev_private;
  274. unsigned long timeout;
  275. u8 gdrst;
  276. /*
  277. * We really should only reset the display subsystem if we actually
  278. * need to
  279. */
  280. bool need_display = true;
  281. mutex_lock(&dev->struct_mutex);
  282. /*
  283. * Clear request list
  284. */
  285. i915_gem_retire_requests(dev);
  286. if (need_display)
  287. i915_save_display(dev);
  288. if (IS_I965G(dev) || IS_G4X(dev)) {
  289. /*
  290. * Set the domains we want to reset, then the reset bit (bit 0).
  291. * Clear the reset bit after a while and wait for hardware status
  292. * bit (bit 1) to be set
  293. */
  294. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  295. pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));
  296. udelay(50);
  297. pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);
  298. /* ...we don't want to loop forever though, 500ms should be plenty */
  299. timeout = jiffies + msecs_to_jiffies(500);
  300. do {
  301. udelay(100);
  302. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  303. } while ((gdrst & 0x1) && time_after(timeout, jiffies));
  304. if (gdrst & 0x1) {
  305. WARN(true, "i915: Failed to reset chip\n");
  306. mutex_unlock(&dev->struct_mutex);
  307. return -EIO;
  308. }
  309. } else {
  310. DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
  311. return -ENODEV;
  312. }
  313. /* Ok, now get things going again... */
  314. /*
  315. * Everything depends on having the GTT running, so we need to start
  316. * there. Fortunately we don't need to do this unless we reset the
  317. * chip at a PCI level.
  318. *
  319. * Next we need to restore the context, but we don't use those
  320. * yet either...
  321. *
  322. * Ring buffer needs to be re-initialized in the KMS case, or if X
  323. * was running at the time of the reset (i.e. we weren't VT
  324. * switched away).
  325. */
  326. if (drm_core_check_feature(dev, DRIVER_MODESET) ||
  327. !dev_priv->mm.suspended) {
  328. drm_i915_ring_buffer_t *ring = &dev_priv->ring;
  329. struct drm_gem_object *obj = ring->ring_obj;
  330. struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
  331. dev_priv->mm.suspended = 0;
  332. /* Stop the ring if it's running. */
  333. I915_WRITE(PRB0_CTL, 0);
  334. I915_WRITE(PRB0_TAIL, 0);
  335. I915_WRITE(PRB0_HEAD, 0);
  336. /* Initialize the ring. */
  337. I915_WRITE(PRB0_START, obj_priv->gtt_offset);
  338. I915_WRITE(PRB0_CTL,
  339. ((obj->size - 4096) & RING_NR_PAGES) |
  340. RING_NO_REPORT |
  341. RING_VALID);
  342. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  343. i915_kernel_lost_context(dev);
  344. else {
  345. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  346. ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  347. ring->space = ring->head - (ring->tail + 8);
  348. if (ring->space < 0)
  349. ring->space += ring->Size;
  350. }
  351. mutex_unlock(&dev->struct_mutex);
  352. drm_irq_uninstall(dev);
  353. drm_irq_install(dev);
  354. mutex_lock(&dev->struct_mutex);
  355. }
  356. /*
  357. * Display needs restore too...
  358. */
  359. if (need_display)
  360. i915_restore_display(dev);
  361. mutex_unlock(&dev->struct_mutex);
  362. return 0;
  363. }
  364. static int __devinit
  365. i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  366. {
  367. return drm_get_dev(pdev, ent, &driver);
  368. }
  369. static void
  370. i915_pci_remove(struct pci_dev *pdev)
  371. {
  372. struct drm_device *dev = pci_get_drvdata(pdev);
  373. drm_put_dev(dev);
  374. }
  375. static int i915_pm_suspend(struct device *dev)
  376. {
  377. struct pci_dev *pdev = to_pci_dev(dev);
  378. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  379. int error;
  380. if (!drm_dev || !drm_dev->dev_private) {
  381. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  382. return -ENODEV;
  383. }
  384. error = i915_drm_freeze(drm_dev);
  385. if (error)
  386. return error;
  387. pci_disable_device(pdev);
  388. pci_set_power_state(pdev, PCI_D3hot);
  389. return 0;
  390. }
  391. static int i915_pm_resume(struct device *dev)
  392. {
  393. struct pci_dev *pdev = to_pci_dev(dev);
  394. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  395. return i915_resume(drm_dev);
  396. }
  397. static int i915_pm_freeze(struct device *dev)
  398. {
  399. struct pci_dev *pdev = to_pci_dev(dev);
  400. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  401. if (!drm_dev || !drm_dev->dev_private) {
  402. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  403. return -ENODEV;
  404. }
  405. return i915_drm_freeze(drm_dev);
  406. }
  407. static int i915_pm_thaw(struct device *dev)
  408. {
  409. struct pci_dev *pdev = to_pci_dev(dev);
  410. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  411. return i915_drm_thaw(drm_dev);
  412. }
  413. static int i915_pm_poweroff(struct device *dev)
  414. {
  415. struct pci_dev *pdev = to_pci_dev(dev);
  416. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  417. return i915_drm_freeze(drm_dev);
  418. }
  419. const struct dev_pm_ops i915_pm_ops = {
  420. .suspend = i915_pm_suspend,
  421. .resume = i915_pm_resume,
  422. .freeze = i915_pm_freeze,
  423. .thaw = i915_pm_thaw,
  424. .poweroff = i915_pm_poweroff,
  425. .restore = i915_pm_resume,
  426. };
  427. static struct vm_operations_struct i915_gem_vm_ops = {
  428. .fault = i915_gem_fault,
  429. .open = drm_gem_vm_open,
  430. .close = drm_gem_vm_close,
  431. };
  432. static struct drm_driver driver = {
  433. /* don't use mtrr's here, the Xserver or user space app should
  434. * deal with them for intel hardware.
  435. */
  436. .driver_features =
  437. DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
  438. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
  439. .load = i915_driver_load,
  440. .unload = i915_driver_unload,
  441. .open = i915_driver_open,
  442. .lastclose = i915_driver_lastclose,
  443. .preclose = i915_driver_preclose,
  444. .postclose = i915_driver_postclose,
  445. /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
  446. .suspend = i915_suspend,
  447. .resume = i915_resume,
  448. .device_is_agp = i915_driver_device_is_agp,
  449. .enable_vblank = i915_enable_vblank,
  450. .disable_vblank = i915_disable_vblank,
  451. .irq_preinstall = i915_driver_irq_preinstall,
  452. .irq_postinstall = i915_driver_irq_postinstall,
  453. .irq_uninstall = i915_driver_irq_uninstall,
  454. .irq_handler = i915_driver_irq_handler,
  455. .reclaim_buffers = drm_core_reclaim_buffers,
  456. .get_map_ofs = drm_core_get_map_ofs,
  457. .get_reg_ofs = drm_core_get_reg_ofs,
  458. .master_create = i915_master_create,
  459. .master_destroy = i915_master_destroy,
  460. #if defined(CONFIG_DEBUG_FS)
  461. .debugfs_init = i915_debugfs_init,
  462. .debugfs_cleanup = i915_debugfs_cleanup,
  463. #endif
  464. .gem_init_object = i915_gem_init_object,
  465. .gem_free_object = i915_gem_free_object,
  466. .gem_vm_ops = &i915_gem_vm_ops,
  467. .ioctls = i915_ioctls,
  468. .fops = {
  469. .owner = THIS_MODULE,
  470. .open = drm_open,
  471. .release = drm_release,
  472. .unlocked_ioctl = drm_ioctl,
  473. .mmap = drm_gem_mmap,
  474. .poll = drm_poll,
  475. .fasync = drm_fasync,
  476. .read = drm_read,
  477. #ifdef CONFIG_COMPAT
  478. .compat_ioctl = i915_compat_ioctl,
  479. #endif
  480. },
  481. .pci_driver = {
  482. .name = DRIVER_NAME,
  483. .id_table = pciidlist,
  484. .probe = i915_pci_probe,
  485. .remove = i915_pci_remove,
  486. .driver.pm = &i915_pm_ops,
  487. },
  488. .name = DRIVER_NAME,
  489. .desc = DRIVER_DESC,
  490. .date = DRIVER_DATE,
  491. .major = DRIVER_MAJOR,
  492. .minor = DRIVER_MINOR,
  493. .patchlevel = DRIVER_PATCHLEVEL,
  494. };
  495. static int __init i915_init(void)
  496. {
  497. if (!intel_agp_enabled) {
  498. DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  499. return -ENODEV;
  500. }
  501. driver.num_ioctls = i915_max_ioctl;
  502. i915_gem_shrinker_init();
  503. /*
  504. * If CONFIG_DRM_I915_KMS is set, default to KMS unless
  505. * explicitly disabled with the module pararmeter.
  506. *
  507. * Otherwise, just follow the parameter (defaulting to off).
  508. *
  509. * Allow optional vga_text_mode_force boot option to override
  510. * the default behavior.
  511. */
  512. #if defined(CONFIG_DRM_I915_KMS)
  513. if (i915_modeset != 0)
  514. driver.driver_features |= DRIVER_MODESET;
  515. #endif
  516. if (i915_modeset == 1)
  517. driver.driver_features |= DRIVER_MODESET;
  518. #ifdef CONFIG_VGA_CONSOLE
  519. if (vgacon_text_force() && i915_modeset == -1)
  520. driver.driver_features &= ~DRIVER_MODESET;
  521. #endif
  522. if (!(driver.driver_features & DRIVER_MODESET)) {
  523. driver.suspend = i915_suspend;
  524. driver.resume = i915_resume;
  525. }
  526. return drm_init(&driver);
  527. }
  528. static void __exit i915_exit(void)
  529. {
  530. i915_gem_shrinker_exit();
  531. drm_exit(&driver);
  532. }
  533. module_init(i915_init);
  534. module_exit(i915_exit);
  535. MODULE_AUTHOR(DRIVER_AUTHOR);
  536. MODULE_DESCRIPTION(DRIVER_DESC);
  537. MODULE_LICENSE("GPL and additional rights");